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clk: sunxi-ng: f1c100s: Add IR mod clock 

For some reason the mod clock for the Allwinner F1C100s CIR (infrared
receiver) peripheral was not modeled in the CCU driver.

Add the clock description to the list, and wire it up in the clock list.
By assigning a new clock ID at the end, it extends the number of clocks.

This allows to use the CIR peripheral on any F1C100s series board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-5-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This commit is contained in:
Andre Przywara 2022-11-07 00:54:27 +00:00 committed by Jernej Skrabec
parent d550f6b0a7
commit f64603c972
3 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
View File

@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
0x0b4, 16, 2, BIT(31), 0);
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
static const char * const ir_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
ir_parents, 0x0b8,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(1), 0);
@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
&mmc1_output_clk.common,
&i2s_clk.common,
&spdif_clk.common,
&ir_clk.common,
&usb_phy0_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_I2S] = &i2s_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,

2
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
View File

@ -29,6 +29,6 @@
/* All bus gates, DRAM gates and mod clocks are exported */
#define CLK_NUMBER (CLK_AVS + 1)
#define CLK_NUMBER (CLK_IR + 1)
#endif /* _CCU_SUNIV_F1C100S_H_ */

2
include/dt-bindings/clock/suniv-ccu-f1c100s.h
View File

@ -67,4 +67,6 @@
#define CLK_CODEC 65
#define CLK_AVS 66
#define CLK_IR 67
#endif