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[MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.
c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged I-caches, but this does not work for flushing other task's icache. This is for example triggered by copy_to_user_page() called from ptrace(2). Use indexed flush for such cases. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
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a94d702049
commit
f6502791d7
2 changed files with 33 additions and 27 deletions
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@ -475,7 +475,7 @@ static inline void local_r4k_flush_cache_page(void *args)
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}
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}
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}
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}
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if (exec) {
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if (exec) {
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if (cpu_has_vtag_icache) {
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if (cpu_has_vtag_icache && mm == current->active_mm) {
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int cpu = smp_processor_id();
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int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0)
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if (cpu_context(cpu, mm) != 0)
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@ -599,7 +599,7 @@ static inline void local_r4k_flush_icache_page(void *args)
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* We're not sure of the virtual address(es) involved here, so
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* We're not sure of the virtual address(es) involved here, so
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* we have to flush the entire I-cache.
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* we have to flush the entire I-cache.
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*/
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*/
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if (cpu_has_vtag_icache) {
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if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) {
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int cpu = smp_processor_id();
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int cpu = smp_processor_id();
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if (cpu_context(cpu, vma->vm_mm) != 0)
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if (cpu_context(cpu, vma->vm_mm) != 0)
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@ -154,6 +154,26 @@ static inline void __sb1_flush_icache_all(void)
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}
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}
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}
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}
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/*
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* Invalidate a range of the icache. The addresses are virtual, and
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* the cache is virtually indexed and tagged. However, we don't
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* necessarily have the right ASID context, so use index ops instead
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* of hit ops.
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*/
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static inline void __sb1_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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start &= ~(icache_line_size - 1);
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end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
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while (start != end) {
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cache_set_op(Index_Invalidate_I, start & icache_index_mask);
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start += icache_line_size;
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}
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mispredict();
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sync();
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}
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/*
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/*
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* Flush the icache for a given physical page. Need to writeback the
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* Flush the icache for a given physical page. Need to writeback the
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* dcache first, then invalidate the icache. If the page isn't
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* dcache first, then invalidate the icache. If the page isn't
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@ -173,8 +193,11 @@ static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long
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/*
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/*
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* Bumping the ASID is probably cheaper than the flush ...
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* Bumping the ASID is probably cheaper than the flush ...
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*/
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*/
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if (cpu_context(cpu, vma->vm_mm) != 0)
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if (vma->vm_mm == current->active_mm) {
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drop_mmu_context(vma->vm_mm, cpu);
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if (cpu_context(cpu, vma->vm_mm) != 0)
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drop_mmu_context(vma->vm_mm, cpu);
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} else
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__sb1_flush_icache_range(addr, addr + PAGE_SIZE);
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}
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}
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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@ -210,26 +233,6 @@ void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsign
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__attribute__((alias("local_sb1_flush_cache_page")));
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__attribute__((alias("local_sb1_flush_cache_page")));
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#endif
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#endif
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/*
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* Invalidate a range of the icache. The addresses are virtual, and
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* the cache is virtually indexed and tagged. However, we don't
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* necessarily have the right ASID context, so use index ops instead
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* of hit ops.
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*/
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static inline void __sb1_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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start &= ~(icache_line_size - 1);
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end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
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while (start != end) {
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cache_set_op(Index_Invalidate_I, start & icache_index_mask);
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start += icache_line_size;
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}
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mispredict();
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sync();
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}
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/*
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/*
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* Invalidate all caches on this CPU
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* Invalidate all caches on this CPU
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@ -326,9 +329,12 @@ static void local_sb1_flush_icache_page(struct vm_area_struct *vma,
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* If there's a context, bump the ASID (cheaper than a flush,
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* If there's a context, bump the ASID (cheaper than a flush,
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* since we don't know VAs!)
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* since we don't know VAs!)
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*/
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*/
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if (cpu_context(cpu, vma->vm_mm) != 0) {
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if (vma->vm_mm == current->active_mm) {
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drop_mmu_context(vma->vm_mm, cpu);
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if (cpu_context(cpu, vma->vm_mm) != 0)
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}
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drop_mmu_context(vma->vm_mm, cpu);
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} else
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__sb1_flush_icache_range(start, start + PAGE_SIZE);
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}
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}
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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