RISC-V Patches for the 5.19 Merge Window, Part 2
This is mostly some DT updates, but also a handful of cleanups and some
fixes. The most user-visible of those are:
* A device tree for the Sundance Polarberry, along with a handful of
fixes and clenups to the PolarFire SOC device trees and bindings.
* The memfd_secret syscall number is now visible to userspace,
* Some improvements to the vm layout dump, which really should have
followed shortly after the sv48 patches but I missed.
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Merge tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
"This is mostly some DT updates, but also a handful of cleanups and
some fixes. The most user-visible of those are:
- A device tree for the Sundance Polarberry, along with a handful of
fixes and clenups to the PolarFire SOC device trees and bindings.
- The memfd_secret syscall number is now visible to userspace,
- Some improvements to the vm layout dump, which really should have
followed shortly after the sv48 patches but I missed"
* tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Move alternative length validation into subsection
riscv: mm: init: make pt_ops_set_[early|late|fixmap] static
riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild
RISC-V: Mark IORESOURCE_EXCLUSIVE for reserved mem instead of IORESOURCE_BUSY
riscv: Wire up memfd_secret in UAPI header
riscv: Fix irq_work when SMP is disabled
riscv: Improve virtual kernel memory layout dump
riscv: Initialize thread pointer before calling C functions
Documentation: riscv: Add sv48 description to VM layout
RISC-V: Only default to spinwait on SBI-0.1 and M-mode
riscv: dts: icicle: sort nodes alphabetically
riscv: microchip: icicle: readability fixes
riscv: dts: microchip: add the sundance polarberry
dt-bindings: riscv: microchip: add polarberry compatible string
dt-bindings: vendor-prefixes: add Sundance DSP
riscv: dts: microchip: make the fabric dtsi board specific
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: remove soc vendor from filenames
riscv: dts: microchip: move sysctrlr out of soc bus
riscv: dts: microchip: remove icicle memory clocks
This commit is contained in:
Linus Torvalds
commit
f66e797b40
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|
@ -20,6 +20,8 @@ properties:
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|||
items:
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- enum:
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- microchip,mpfs-icicle-kit
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- microchip,mpfs-icicle-reference-rtlv2203
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- sundance,polarberry
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- const: microchip,mpfs
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additionalProperties: true
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|
|
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@ -1207,6 +1207,8 @@ patternProperties:
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description: Summit microelectronics
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"^sunchip,.*":
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description: Shenzhen Sunchip Technology Co., Ltd
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"^sundance,.*":
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description: Sundance DSP Inc.
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"^sunplus,.*":
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description: Sunplus Technology Co., Ltd.
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"^SUNW,.*":
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|
|
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@ -61,3 +61,39 @@ RISC-V Linux Kernel SV39
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ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
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ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
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__________________|____________|__________________|_________|____________________________________________________________
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RISC-V Linux Kernel SV48
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------------------------
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::
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========================================================================================================================
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Start addr | Offset | End addr | Size | VM area description
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========================================================================================================================
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| | | |
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0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different per mm
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__________________|____________|__________________|_________|___________________________________________________________
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| | | |
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0000800000000000 | +128 TB | ffff7fffffffffff | ~16M TB | ... huge, almost 64 bits wide hole of non-canonical
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| | | | virtual memory addresses up to the -128 TB
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| | | | starting offset of kernel mappings.
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__________________|____________|__________________|_________|___________________________________________________________
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|
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| Kernel-space virtual memory, shared between all processes:
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____________________________________________________________|___________________________________________________________
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| | | |
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ffff8d7ffee00000 | -114.5 TB | ffff8d7ffeffffff | 2 MB | fixmap
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ffff8d7fff000000 | -114.5 TB | ffff8d7fffffffff | 16 MB | PCI io
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ffff8d8000000000 | -114.5 TB | ffff8f7fffffffff | 2 TB | vmemmap
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ffff8f8000000000 | -112.5 TB | ffffaf7fffffffff | 32 TB | vmalloc/ioremap space
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ffffaf8000000000 | -80.5 TB | ffffef7fffffffff | 64 TB | direct mapping of all physical memory
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ffffef8000000000 | -16.5 TB | fffffffeffffffff | 16.5 TB | kasan
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__________________|____________|__________________|_________|____________________________________________________________
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|
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| Identical layout to the 39-bit one from here on:
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____________________________________________________________|____________________________________________________________
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| | | |
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ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
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ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
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__________________|____________|__________________|_________|____________________________________________________________
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|
|
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@ -2,6 +2,8 @@
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obj-y += kernel/ mm/ net/
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obj-$(CONFIG_BUILTIN_DTB) += boot/dts/
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obj-y += errata/
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obj-$(CONFIG_KVM) += kvm/
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obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += purgatory/
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|
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@ -396,7 +396,7 @@ config RISCV_SBI_V01
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config RISCV_BOOT_SPINWAIT
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bool "Spinwait booting method"
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depends on SMP
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default y
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default y if RISCV_SBI_V01 || RISCV_M_MODE
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help
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This enables support for booting Linux via spinwait method. In the
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spinwait method, all cores randomly jump to Linux. One of the cores
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@ -407,6 +407,12 @@ config RISCV_BOOT_SPINWAIT
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rely on ordered booting via SBI HSM extension which gets chosen
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dynamically at runtime if the firmware supports it.
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Since spinwait is incompatible with sparse hart IDs, it requires
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NR_CPUS be large enough to contain the physical hart ID of the first
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hart to enter Linux.
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If unsure what to do here, say N.
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config KEXEC
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bool "Kexec system call"
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select KEXEC_CORE
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|
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@ -103,9 +103,6 @@ endif
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head-y := arch/riscv/kernel/head.o
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core-y += arch/riscv/errata/
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core-$(CONFIG_KVM) += arch/riscv/kvm/
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libs-y += arch/riscv/lib/
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libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
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|
|
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@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
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|
|
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@ -2,6 +2,8 @@
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/ {
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compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
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core_pwm0: pwm@41000000 {
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x41000000 0x0 0xF0>;
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@ -3,7 +3,8 @@
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/dts-v1/;
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#include "microchip-mpfs.dtsi"
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#include "mpfs.dtsi"
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#include "mpfs-icicle-kit-fabric.dtsi"
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|
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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@ -32,63 +33,29 @@
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x2e000000>;
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clocks = <&clkcfg CLK_DDRC>;
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status = "okay";
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};
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ddrc_cache_hi: memory@1000000000 {
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device_type = "memory";
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reg = <0x10 0x0 0x0 0x40000000>;
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clocks = <&clkcfg CLK_DDRC>;
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status = "okay";
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};
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&mmuart1 {
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&core_pwm0 {
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status = "okay";
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};
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&mmuart2 {
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status = "okay";
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};
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&mmuart3 {
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status = "okay";
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};
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&mmuart4 {
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status = "okay";
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};
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&mmc {
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status = "okay";
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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card-detect-delay = <200>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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};
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&spi0 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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};
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&qspi {
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>;
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status = "okay";
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};
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@ -107,48 +74,57 @@
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&mac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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status = "okay";
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};
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&mac1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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status = "okay";
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|
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phy1: ethernet-phy@9 {
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reg = <9>;
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ti,fifo-depth = <0x1>;
|
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};
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|
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phy0: ethernet-phy@8 {
|
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reg = <8>;
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ti,fifo-depth = <0x1>;
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};
|
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};
|
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|
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&gpio2 {
|
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interrupts = <53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
||||
<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>,
|
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<53>, <53>, <53>, <53>;
|
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status = "okay";
|
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};
|
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|
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&rtc {
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status = "okay";
|
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};
|
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|
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&usb {
|
||||
status = "okay";
|
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dr_mode = "host";
|
||||
};
|
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|
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&mbox {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&syscontroller {
|
||||
&mmc {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
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cap-mmc-highspeed;
|
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card-detect-delay = <200>;
|
||||
mmc-ddr-1_8v;
|
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mmc-hs200-1_8v;
|
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sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -156,6 +132,31 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&core_pwm0 {
|
||||
&qspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&syscontroller {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2020-2022 Microchip Technology Inc */
|
||||
|
||||
/ {
|
||||
fabric_clk3: fabric-clk3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <62500000>;
|
||||
};
|
||||
|
||||
fabric_clk1: fabric-clk1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2020-2022 Microchip Technology Inc */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "mpfs.dtsi"
|
||||
#include "mpfs-polarberry-fabric.dtsi"
|
||||
|
||||
/* Clock frequency (in Hz) of the rtcclk */
|
||||
#define MTIMER_FREQ 1000000
|
||||
|
||||
/ {
|
||||
model = "Sundance PolarBerry";
|
||||
compatible = "sundance,polarberry", "microchip,mpfs";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &mac1;
|
||||
serial0 = &mmuart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
timebase-frequency = <MTIMER_FREQ>;
|
||||
};
|
||||
|
||||
ddrc_cache_lo: memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x2e000000>;
|
||||
};
|
||||
|
||||
ddrc_cache_hi: memory@1000000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x10 0x00000000 0x0 0xC0000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* phy0 is connected to mac0, but the port itself is on the (optional) carrier
|
||||
* board.
|
||||
*/
|
||||
&mac0 {
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&phy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mac1 {
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&phy1>;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
ti,fifo-depth = <0x01>;
|
||||
};
|
||||
|
||||
phy0: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
ti,fifo-depth = <0x01>;
|
||||
};
|
||||
};
|
||||
|
||||
&mbox {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&syscontroller {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -3,7 +3,6 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "dt-bindings/clock/microchip,mpfs-clock.h"
|
||||
#include "microchip-mpfs-fabric.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
|
|
@ -146,6 +145,11 @@
|
|||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
syscontroller: syscontroller {
|
||||
compatible = "microchip,mpfs-sys-controller";
|
||||
mboxes = <&mbox 0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -446,10 +450,5 @@
|
|||
#mbox-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscontroller: syscontroller {
|
||||
compatible = "microchip,mpfs-sys-controller";
|
||||
mboxes = <&mbox 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -27,9 +27,9 @@
|
|||
\new_c
|
||||
.option pop
|
||||
889 :
|
||||
.previous
|
||||
.org . - (889b - 888b) + (887b - 886b)
|
||||
.org . - (887b - 886b) + (889b - 888b)
|
||||
.previous
|
||||
.endif
|
||||
.endm
|
||||
|
||||
|
|
@ -94,9 +94,9 @@
|
|||
new_c "\n" \
|
||||
".option pop\n" \
|
||||
"889 :\n" \
|
||||
".previous\n" \
|
||||
".org . - (887b - 886b) + (889b - 888b)\n" \
|
||||
".org . - (889b - 888b) + (887b - 886b)\n" \
|
||||
".previous\n" \
|
||||
".endif\n"
|
||||
|
||||
#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
static inline bool arch_irq_work_has_interrupt(void)
|
||||
{
|
||||
return true;
|
||||
return IS_ENABLED(CONFIG_SMP);
|
||||
}
|
||||
extern void arch_irq_work_raise(void);
|
||||
#endif /* _ASM_RISCV_IRQ_WORK_H */
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
*/
|
||||
|
||||
#define __ARCH_WANT_SYS_CLONE
|
||||
#define __ARCH_WANT_MEMFD_SECRET
|
||||
|
||||
#ifdef CONFIG_COMPAT
|
||||
#define __ARCH_WANT_COMPAT_TRUNCATE64
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#endif /* __LP64__ */
|
||||
|
||||
#define __ARCH_WANT_SYS_CLONE3
|
||||
#define __ARCH_WANT_MEMFD_SECRET
|
||||
|
||||
#include <asm-generic/unistd.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -298,6 +298,7 @@ clear_bss_done:
|
|||
REG_S a0, (a2)
|
||||
|
||||
/* Initialize page tables and relocate to virtual addresses */
|
||||
la tp, init_task
|
||||
la sp, init_thread_union + THREAD_SIZE
|
||||
XIP_FIXUP_OFFSET sp
|
||||
#ifdef CONFIG_BUILTIN_DTB
|
||||
|
|
|
|||
|
|
@ -190,7 +190,7 @@ static void __init init_resources(void)
|
|||
res = &mem_res[res_idx--];
|
||||
|
||||
res->name = "Reserved";
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_EXCLUSIVE;
|
||||
res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region));
|
||||
res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1;
|
||||
|
||||
|
|
@ -215,7 +215,7 @@ static void __init init_resources(void)
|
|||
|
||||
if (unlikely(memblock_is_nomap(region))) {
|
||||
res->name = "Reserved";
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_EXCLUSIVE;
|
||||
} else {
|
||||
res->name = "System RAM";
|
||||
res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
|
||||
|
|
|
|||
|
|
@ -76,38 +76,74 @@ static void __init zone_sizes_init(void)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
|
||||
|
||||
#define LOG2_SZ_1K ilog2(SZ_1K)
|
||||
#define LOG2_SZ_1M ilog2(SZ_1M)
|
||||
#define LOG2_SZ_1G ilog2(SZ_1G)
|
||||
#define LOG2_SZ_1T ilog2(SZ_1T)
|
||||
|
||||
static inline void print_mlk(char *name, unsigned long b, unsigned long t)
|
||||
{
|
||||
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld kB)\n", name, b, t,
|
||||
(((t) - (b)) >> 10));
|
||||
(((t) - (b)) >> LOG2_SZ_1K));
|
||||
}
|
||||
|
||||
static inline void print_mlm(char *name, unsigned long b, unsigned long t)
|
||||
{
|
||||
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld MB)\n", name, b, t,
|
||||
(((t) - (b)) >> 20));
|
||||
(((t) - (b)) >> LOG2_SZ_1M));
|
||||
}
|
||||
|
||||
static inline void print_mlg(char *name, unsigned long b, unsigned long t)
|
||||
{
|
||||
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld GB)\n", name, b, t,
|
||||
(((t) - (b)) >> LOG2_SZ_1G));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
static inline void print_mlt(char *name, unsigned long b, unsigned long t)
|
||||
{
|
||||
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld TB)\n", name, b, t,
|
||||
(((t) - (b)) >> LOG2_SZ_1T));
|
||||
}
|
||||
#else
|
||||
#define print_mlt(n, b, t) do {} while (0)
|
||||
#endif
|
||||
|
||||
static inline void print_ml(char *name, unsigned long b, unsigned long t)
|
||||
{
|
||||
unsigned long diff = t - b;
|
||||
|
||||
if (IS_ENABLED(CONFIG_64BIT) && (diff >> LOG2_SZ_1T) >= 10)
|
||||
print_mlt(name, b, t);
|
||||
else if ((diff >> LOG2_SZ_1G) >= 10)
|
||||
print_mlg(name, b, t);
|
||||
else if ((diff >> LOG2_SZ_1M) >= 10)
|
||||
print_mlm(name, b, t);
|
||||
else
|
||||
print_mlk(name, b, t);
|
||||
}
|
||||
|
||||
static void __init print_vm_layout(void)
|
||||
{
|
||||
pr_notice("Virtual kernel memory layout:\n");
|
||||
print_mlk("fixmap", (unsigned long)FIXADDR_START,
|
||||
(unsigned long)FIXADDR_TOP);
|
||||
print_mlm("pci io", (unsigned long)PCI_IO_START,
|
||||
(unsigned long)PCI_IO_END);
|
||||
print_mlm("vmemmap", (unsigned long)VMEMMAP_START,
|
||||
(unsigned long)VMEMMAP_END);
|
||||
print_mlm("vmalloc", (unsigned long)VMALLOC_START,
|
||||
(unsigned long)VMALLOC_END);
|
||||
print_mlm("lowmem", (unsigned long)PAGE_OFFSET,
|
||||
(unsigned long)high_memory);
|
||||
print_ml("fixmap", (unsigned long)FIXADDR_START,
|
||||
(unsigned long)FIXADDR_TOP);
|
||||
print_ml("pci io", (unsigned long)PCI_IO_START,
|
||||
(unsigned long)PCI_IO_END);
|
||||
print_ml("vmemmap", (unsigned long)VMEMMAP_START,
|
||||
(unsigned long)VMEMMAP_END);
|
||||
print_ml("vmalloc", (unsigned long)VMALLOC_START,
|
||||
(unsigned long)VMALLOC_END);
|
||||
print_ml("lowmem", (unsigned long)PAGE_OFFSET,
|
||||
(unsigned long)high_memory);
|
||||
if (IS_ENABLED(CONFIG_64BIT)) {
|
||||
#ifdef CONFIG_KASAN
|
||||
print_mlm("kasan", KASAN_SHADOW_START, KASAN_SHADOW_END);
|
||||
print_ml("kasan", KASAN_SHADOW_START, KASAN_SHADOW_END);
|
||||
#endif
|
||||
|
||||
print_mlm("kernel", (unsigned long)KERNEL_LINK_ADDR,
|
||||
(unsigned long)ADDRESS_SPACE_END);
|
||||
print_ml("kernel", (unsigned long)KERNEL_LINK_ADDR,
|
||||
(unsigned long)ADDRESS_SPACE_END);
|
||||
}
|
||||
}
|
||||
#else
|
||||
|
|
@ -843,7 +879,7 @@ static void __init create_fdt_early_page_table(pgd_t *pgdir, uintptr_t dtb_pa)
|
|||
* MMU is not enabled, the page tables are allocated directly using
|
||||
* early_pmd/pud/p4d and the address returned is the physical one.
|
||||
*/
|
||||
void __init pt_ops_set_early(void)
|
||||
static void __init pt_ops_set_early(void)
|
||||
{
|
||||
pt_ops.alloc_pte = alloc_pte_early;
|
||||
pt_ops.get_pte_virt = get_pte_virt_early;
|
||||
|
|
@ -865,7 +901,7 @@ void __init pt_ops_set_early(void)
|
|||
* Note that this is called with MMU disabled, hence kernel_mapping_pa_to_va,
|
||||
* but it will be used as described above.
|
||||
*/
|
||||
void __init pt_ops_set_fixmap(void)
|
||||
static void __init pt_ops_set_fixmap(void)
|
||||
{
|
||||
pt_ops.alloc_pte = kernel_mapping_pa_to_va((uintptr_t)alloc_pte_fixmap);
|
||||
pt_ops.get_pte_virt = kernel_mapping_pa_to_va((uintptr_t)get_pte_virt_fixmap);
|
||||
|
|
@ -883,7 +919,7 @@ void __init pt_ops_set_fixmap(void)
|
|||
* MMU is enabled and page table setup is complete, so from now, we can use
|
||||
* generic page allocation functions to setup page table.
|
||||
*/
|
||||
void __init pt_ops_set_late(void)
|
||||
static void __init pt_ops_set_late(void)
|
||||
{
|
||||
pt_ops.alloc_pte = alloc_pte_late;
|
||||
pt_ops.get_pte_virt = get_pte_virt_late;
|
||||
|
|
|
|||
Loading…
Reference in New Issue