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drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
The other DDI .enable_clock() functions are trying to protect us against pll==NULL. A bit tempted to throw out all the WARNs as just unnecessary noise, but I guess they might have some use when poking around the shared_dpll code (not sure it wouldn't oops elsewhere though). So let's unify it all and sprinkle in the missing WARNs for icl/dg1. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-11-ville.syrjala@linux.intel.com
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@ -1606,6 +1606,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
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struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
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enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
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if (drm_WARN_ON(&dev_priv->drm, !pll))
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return;
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/*
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/*
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* If we fail this, something went very wrong: first 2 PLLs should be
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* If we fail this, something went very wrong: first 2 PLLs should be
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* used by first 2 phys and last 2 PLLs by last phys
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* used by first 2 phys and last 2 PLLs by last phys
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@ -1663,6 +1666,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
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sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
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sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
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}
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}
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if (drm_WARN_ON(&dev_priv->drm, !pll))
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return;
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mutex_lock(&dev_priv->dpll.lock);
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mutex_lock(&dev_priv->dpll.lock);
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/*
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/*
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