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MIPS: math-emu: Set FIR feature flags for full emulation
Implement FIR feature flags in the FPU emulator according to features supported and architecture level requirements. The W, L and F64 bits have only been added at level #2 even though the features they refer to were also included with the MIPS64r1 ISA and the W fixed-point format also with the MIPS32r1 ISA. This is only relevant for the full emulation mode and the emulated CFC1 instruction as well as ptrace(2) accesses. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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9cb60e2026
commit
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2 changed files with 25 additions and 3 deletions
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@ -20,6 +20,7 @@
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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@ -31,11 +32,30 @@
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#include <asm/spram.h>
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#include <asm/uaccess.h>
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/*
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* Set the FIR feature flags for the FPU emulator.
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*/
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static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
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{
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u32 value;
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value = 0;
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
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value |= MIPS_FPIR_D | MIPS_FPIR_S;
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if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
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value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
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c->fpu_id = value;
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}
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static int mips_fpu_disabled;
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static int __init fpu_disable(char *s)
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{
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cpu_data[0].options &= ~MIPS_CPU_FPU;
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boot_cpu_data.options &= ~MIPS_CPU_FPU;
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cpu_set_nofpu_id(&boot_cpu_data);
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mips_fpu_disabled = 1;
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return 1;
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@ -1382,7 +1402,8 @@ void cpu_probe(void)
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if (c->fpu_id & MIPS_FPIR_FREP)
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c->options |= MIPS_CPU_FRE;
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}
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}
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} else
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cpu_set_nofpu_id(c);
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if (cpu_has_mips_r2_r6) {
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c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
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@ -45,6 +45,7 @@
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#include <asm/signal.h>
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#include <asm/uaccess.h>
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#include <asm/cpu-info.h>
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#include <asm/processor.h>
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#include <asm/fpu_emulator.h>
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#include <asm/fpu.h>
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@ -853,7 +854,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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(void *)xcp->cp0_epc,
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MIPSInst_RT(ir), value);
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} else if (MIPSInst_RD(ir) == FPCREG_RID)
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value = 0;
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value = current_cpu_data.fpu_id;
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else
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value = 0;
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if (MIPSInst_RT(ir))
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