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drm/radeon: protect against div by 0 in backend setup
Make sure at least one RB is enabled in r6xx_remap_render_backend() to avoid an division by zero in some corner cases. See: https://bugzilla.redhat.com/show_bug.cgi?id=892233 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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1 changed files with 5 additions and 2 deletions
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@ -1462,12 +1462,15 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev,
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u32 disabled_rb_mask)
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{
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u32 rendering_pipe_num, rb_num_width, req_rb_num;
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u32 pipe_rb_ratio, pipe_rb_remain;
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u32 pipe_rb_ratio, pipe_rb_remain, tmp;
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u32 data = 0, mask = 1 << (max_rb_num - 1);
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unsigned i, j;
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/* mask out the RBs that don't exist on that asic */
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disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
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tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
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/* make sure at least one RB is available */
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if ((tmp & 0xff) != 0xff)
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disabled_rb_mask = tmp;
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rendering_pipe_num = 1 << tiling_pipe_num;
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req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
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