From 81f652afa6adde6c2db248e9ae83de16c25ddb50 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 17 Sep 2020 20:59:24 +0100 Subject: [PATCH 01/80] pinctrl: renesas: r8a7790: Add VIN1-B and VIN2-G pins, groups and functions Add pins, groups and functions for the VIN1-B [data/sync/field/clkenb/clk] and VIN2-G8. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Ulrich Hecht Link: https://lore.kernel.org/r/20200917195924.20384-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7790.c | 132 +++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 60f973c5dffe..3f48d3d879f7 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -3866,6 +3866,72 @@ static const unsigned int vin1_data18_mux[] = { VI1_R4_MARK, VI1_R5_MARK, VI1_R6_MARK, VI1_R7_MARK, }; +static const union vin_data vin1_data_b_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), + }, +}; +static const union vin_data vin1_data_b_mux = { + .data24 = { + /* B */ + VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, + }, +}; +static const unsigned int vin1_data18_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), +}; +static const unsigned int vin1_data18_b_mux[] = { + /* B */ + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, +}; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(1, 24), /* HSYNC */ RCAR_GP_PIN(1, 25), /* VSYNC */ @@ -3874,24 +3940,50 @@ static const unsigned int vin1_sync_mux[] = { VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, }; +static const unsigned int vin1_sync_b_pins[] = { + RCAR_GP_PIN(1, 24), /* HSYNC */ + RCAR_GP_PIN(1, 25), /* VSYNC */ +}; +static const unsigned int vin1_sync_b_mux[] = { + VI1_HSYNC_N_B_MARK, + VI1_VSYNC_N_B_MARK, +}; static const unsigned int vin1_field_pins[] = { RCAR_GP_PIN(1, 13), }; static const unsigned int vin1_field_mux[] = { VI1_FIELD_MARK, }; +static const unsigned int vin1_field_b_pins[] = { + RCAR_GP_PIN(1, 13), +}; +static const unsigned int vin1_field_b_mux[] = { + VI1_FIELD_B_MARK, +}; static const unsigned int vin1_clkenb_pins[] = { RCAR_GP_PIN(1, 26), }; static const unsigned int vin1_clkenb_mux[] = { VI1_CLKENB_MARK, }; +static const unsigned int vin1_clkenb_b_pins[] = { + RCAR_GP_PIN(1, 26), +}; +static const unsigned int vin1_clkenb_b_mux[] = { + VI1_CLKENB_B_MARK, +}; static const unsigned int vin1_clk_pins[] = { RCAR_GP_PIN(2, 9), }; static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +static const unsigned int vin1_clk_b_pins[] = { + RCAR_GP_PIN(3, 15), +}; +static const unsigned int vin1_clk_b_mux[] = { + VI1_CLK_B_MARK, +}; /* - VIN2 ----------------------------------------------------------------- */ static const union vin_data vin2_data_pins = { .data24 = { @@ -3959,6 +4051,18 @@ static const unsigned int vin2_data18_mux[] = { VI2_R4_MARK, VI2_R5_MARK, VI2_R6_MARK, VI2_R7_MARK, }; +static const unsigned int vin2_g8_pins[] = { + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin2_g8_mux[] = { + VI2_G0_MARK, VI2_G1_MARK, + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, +}; static const unsigned int vin2_sync_pins[] = { RCAR_GP_PIN(1, 16), /* HSYNC */ RCAR_GP_PIN(1, 21), /* VSYNC */ @@ -4026,7 +4130,7 @@ static const unsigned int vin3_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[298]; + struct sh_pfc_pin_group common[311]; struct sh_pfc_pin_group automotive[1]; } pinmux_groups = { .common = { @@ -4310,15 +4414,28 @@ static const struct { VIN_DATA_PIN_GROUP(vin1_data, 10), VIN_DATA_PIN_GROUP(vin1_data, 8), VIN_DATA_PIN_GROUP(vin1_data, 4), + VIN_DATA_PIN_GROUP(vin1_data, 24, _b), + VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + SH_PFC_PIN_GROUP(vin1_data18_b), + VIN_DATA_PIN_GROUP(vin1_data, 16, _b), + VIN_DATA_PIN_GROUP(vin1_data, 12, _b), + VIN_DATA_PIN_GROUP(vin1_data, 10, _b), + VIN_DATA_PIN_GROUP(vin1_data, 8, _b), + VIN_DATA_PIN_GROUP(vin1_data, 4, _b), SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_field_b), SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clkenb_b), SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_clk_b), VIN_DATA_PIN_GROUP(vin2_data, 24), SH_PFC_PIN_GROUP(vin2_data18), VIN_DATA_PIN_GROUP(vin2_data, 16), VIN_DATA_PIN_GROUP(vin2_data, 8), VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_g8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), @@ -4784,10 +4901,22 @@ static const char * const vin1_groups[] = { "vin1_data10", "vin1_data8", "vin1_data4", + "vin1_data24_b", + "vin1_data20_b", + "vin1_data18_b", + "vin1_data16_b", + "vin1_data12_b", + "vin1_data10_b", + "vin1_data8_b", + "vin1_data4_b", "vin1_sync", + "vin1_sync_b", "vin1_field", + "vin1_field_b", "vin1_clkenb", + "vin1_clkenb_b", "vin1_clk", + "vin1_clk_b", }; static const char * const vin2_groups[] = { @@ -4796,6 +4925,7 @@ static const char * const vin2_groups[] = { "vin2_data16", "vin2_data8", "vin2_data4", + "vin2_g8", "vin2_sync", "vin2_field", "vin2_clkenb", From c5564a50d99019f3c713fa306d5feecc3e909b10 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Tue, 20 Oct 2020 06:15:20 -0700 Subject: [PATCH 02/80] pinctrl: samsung: s3c24xx: remove unneeded break A break is not needed if it is preceded by a return. Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20201020131520.29117-1-trix@redhat.com Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index 5e24838a582f..2223ead5bd72 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -108,19 +108,14 @@ static int s3c24xx_eint_get_trigger(unsigned int type) switch (type) { case IRQ_TYPE_EDGE_RISING: return EINT_EDGE_RISING; - break; case IRQ_TYPE_EDGE_FALLING: return EINT_EDGE_FALLING; - break; case IRQ_TYPE_EDGE_BOTH: return EINT_EDGE_BOTH; - break; case IRQ_TYPE_LEVEL_HIGH: return EINT_LEVEL_HIGH; - break; case IRQ_TYPE_LEVEL_LOW: return EINT_LEVEL_LOW; - break; default: return -EINVAL; } From 866c9c55cb283e1d86e67f065dfe42a05a760b65 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 26 Oct 2020 21:23:25 +0200 Subject: [PATCH 03/80] pinctrl: intel: Add Intel Lakefield pin controller support This driver adds pinctrl/GPIO support for Intel Lakefield SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Ricardo Neri Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 8 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-lakefield.c | 375 ++++++++++++++++++++++ 3 files changed, 384 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-lakefield.c diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 28e5f824ba45..24a6fbcfbfc1 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -119,6 +119,14 @@ config PINCTRL_JASPERLAKE This pinctrl driver provides an interface that allows configuring of Intel Jasper Lake PCH pins and using them as GPIOs. +config PINCTRL_LAKEFIELD + tristate "Intel Lakefield SoC pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Lakefield SoC pins and using them as GPIOs. + config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 1c1c316f98b9..1ddfddecd3de 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_EMMITSBURG) += pinctrl-emmitsburg.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o +obj-$(CONFIG_PINCTRL_LAKEFIELD) += pinctrl-lakefield.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c new file mode 100644 index 000000000000..3c6283c4827f --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Lakefield PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko + */ + +#include +#include +#include + +#include + +#include "pinctrl-intel.h" + +#define LKF_PAD_OWN 0x020 +#define LKF_PADCFGLOCK 0x070 +#define LKF_HOSTSW_OWN 0x090 +#define LKF_GPI_IS 0x100 +#define LKF_GPI_IE 0x110 + +#define LKF_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define LKF_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = LKF_PAD_OWN, \ + .padcfglock_offset = LKF_PADCFGLOCK, \ + .hostown_offset = LKF_HOSTSW_OWN, \ + .is_offset = LKF_GPI_IS, \ + .ie_offset = LKF_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Lakefield */ +static const struct pinctrl_pin_desc lkf_pins[] = { + /* EAST */ + PINCTRL_PIN(0, "MDSI_A_TE0"), + PINCTRL_PIN(1, "MDSI_A_TE1"), + PINCTRL_PIN(2, "PANEL0_AVDD_EN"), + PINCTRL_PIN(3, "PANEL0_BKLTEN"), + PINCTRL_PIN(4, "PANEL0_BKLTCTL"), + PINCTRL_PIN(5, "PANEL1_AVDD_EN"), + PINCTRL_PIN(6, "PANEL1_BKLTEN"), + PINCTRL_PIN(7, "PANEL1_BKLTCTL"), + PINCTRL_PIN(8, "THC0_SPI1_IO_0"), + PINCTRL_PIN(9, "THC0_SPI1_IO_1"), + PINCTRL_PIN(10, "THC0_SPI1_IO_2"), + PINCTRL_PIN(11, "THC0_SPI1_IO_3"), + PINCTRL_PIN(12, "THC0_SPI1_CSB"), + PINCTRL_PIN(13, "THC0_SPI1_CLK"), + PINCTRL_PIN(14, "THC0_SPI1_RESETB"), + PINCTRL_PIN(15, "THC0_SPI1_CLK_FB"), + PINCTRL_PIN(16, "SPI_TOUCH_CLK_FB"), + PINCTRL_PIN(17, "THC1_SPI2_IO_0"), + PINCTRL_PIN(18, "THC1_SPI2_IO_1"), + PINCTRL_PIN(19, "THC1_SPI2_IO_2"), + PINCTRL_PIN(20, "THC1_SPI2_IO_3"), + PINCTRL_PIN(21, "THC1_SPI2_CSB"), + PINCTRL_PIN(22, "THC1_SPI2_CLK"), + PINCTRL_PIN(23, "THC1_SPI2_RESETB"), + PINCTRL_PIN(24, "THC1_SPI2_CLK_FB"), + PINCTRL_PIN(25, "eSPI_IO_0"), + PINCTRL_PIN(26, "eSPI_IO_1"), + PINCTRL_PIN(27, "eSPI_IO_2"), + PINCTRL_PIN(28, "eSPI_IO_3"), + PINCTRL_PIN(29, "eSPI_CSB"), + PINCTRL_PIN(30, "eSPI_RESETB"), + PINCTRL_PIN(31, "eSPI_CLK"), + PINCTRL_PIN(32, "eSPI_CLK_FB"), + PINCTRL_PIN(33, "FAST_SPI0_IO_0"), + PINCTRL_PIN(34, "FAST_SPI0_IO_1"), + PINCTRL_PIN(35, "FAST_SPI0_IO_2"), + PINCTRL_PIN(36, "FAST_SPI0_IO_3"), + PINCTRL_PIN(37, "FAST_SPI0_CSB_0"), + PINCTRL_PIN(38, "FAST_SPI0_CSB_2"), + PINCTRL_PIN(39, "FAST_SPI0_CLK"), + PINCTRL_PIN(40, "FAST_SPI_CLK_FB"), + PINCTRL_PIN(41, "FAST_SPI0_CSB_1"), + PINCTRL_PIN(42, "ISH_GP_12"), + PINCTRL_PIN(43, "THC0_SPI1_INTB"), + PINCTRL_PIN(44, "THC1_SPI2_INTB"), + PINCTRL_PIN(45, "PANEL0_AVEE_EN"), + PINCTRL_PIN(46, "PANEL0_VIO_EN"), + PINCTRL_PIN(47, "PANEL1_AVEE_EN"), + PINCTRL_PIN(48, "PANEL1_VIO_EN"), + PINCTRL_PIN(49, "PANEL0_RESET"), + PINCTRL_PIN(50, "PANEL1_RESET"), + PINCTRL_PIN(51, "ISH_GP_15"), + PINCTRL_PIN(52, "ISH_GP_16"), + PINCTRL_PIN(53, "ISH_GP_17"), + PINCTRL_PIN(54, "ISH_GP_18"), + PINCTRL_PIN(55, "ISH_GP_19"), + PINCTRL_PIN(56, "ISH_GP_20"), + PINCTRL_PIN(57, "ISH_GP_21"), + PINCTRL_PIN(58, "ISH_GP_22"), + PINCTRL_PIN(59, "ISH_GP_23"), + /* NORTHWEST */ + PINCTRL_PIN(60, "MCSI_GPIO_0"), + PINCTRL_PIN(61, "MCSI_GPIO_1"), + PINCTRL_PIN(62, "MCSI_GPIO_2"), + PINCTRL_PIN(63, "MCSI_GPIO_3"), + PINCTRL_PIN(64, "LPSS_I2C0_SDA"), + PINCTRL_PIN(65, "LPSS_I2C0_SCL"), + PINCTRL_PIN(66, "LPSS_I2C1_SDA"), + PINCTRL_PIN(67, "LPSS_I2C1_SCL"), + PINCTRL_PIN(68, "LPSS_I2C2_SDA"), + PINCTRL_PIN(69, "LPSS_I2C2_SCL"), + PINCTRL_PIN(70, "LPSS_I2C3_SDA"), + PINCTRL_PIN(71, "LPSS_I2C3_SCL"), + PINCTRL_PIN(72, "LPSS_I2C4_SDA"), + PINCTRL_PIN(73, "LPSS_I2C4_SCL"), + PINCTRL_PIN(74, "LPSS_I2C5_SDA"), + PINCTRL_PIN(75, "LPSS_I2C5_SCL"), + PINCTRL_PIN(76, "LPSS_I3C0_SDA"), + PINCTRL_PIN(77, "LPSS_I3C0_SCL"), + PINCTRL_PIN(78, "LPSS_I3C0_SCL_FB"), + PINCTRL_PIN(79, "LPSS_I3C1_SDA"), + PINCTRL_PIN(80, "LPSS_I3C1_SCL"), + PINCTRL_PIN(81, "LPSS_I3C1_SCL_FB"), + PINCTRL_PIN(82, "ISH_I2C0_SDA"), + PINCTRL_PIN(83, "ISH_I2C0_SCL"), + PINCTRL_PIN(84, "ISH_I2C1_SCL"), + PINCTRL_PIN(85, "ISH_I2C1_SDA"), + PINCTRL_PIN(86, "DBG_PMODE"), + PINCTRL_PIN(87, "BJTAG_TCK"), + PINCTRL_PIN(88, "BJTAG_TDI"), + PINCTRL_PIN(89, "BJTAGX"), + PINCTRL_PIN(90, "BPREQ_B"), + PINCTRL_PIN(91, "BJTAG_TMS"), + PINCTRL_PIN(92, "BPRDY_B"), + PINCTRL_PIN(93, "BJTAG_TDO"), + PINCTRL_PIN(94, "BJTAG_TRST_B_0"), + PINCTRL_PIN(95, "ISH_I3C0_SDA"), + PINCTRL_PIN(96, "ISH_I3C0_SCL"), + PINCTRL_PIN(97, "ISH_I3C0_SCL_FB"), + PINCTRL_PIN(98, "AVS_I2S_BCLK_0"), + PINCTRL_PIN(99, "AVS_I2S_MCLK_0"), + PINCTRL_PIN(100, "AVS_I2S_SFRM_0"), + PINCTRL_PIN(101, "AVS_I2S_RXD_0"), + PINCTRL_PIN(102, "AVS_I2S_TXD_0"), + PINCTRL_PIN(103, "AVS_I2S_BCLK_1"), + PINCTRL_PIN(104, "AVS_I2S_SFRM_1"), + PINCTRL_PIN(105, "AVS_I2S_RXD_1"), + PINCTRL_PIN(106, "AVS_I2S_TXD_1"), + PINCTRL_PIN(107, "AVS_I2S_BCLK_2"), + PINCTRL_PIN(108, "AVS_I2S_SFRM_2"), + PINCTRL_PIN(109, "AVS_I2S_RXD_2"), + PINCTRL_PIN(110, "AVS_I2S_TXD_2"), + PINCTRL_PIN(111, "AVS_I2S_BCLK_3"), + PINCTRL_PIN(112, "AVS_I2S_SFRM_3"), + PINCTRL_PIN(113, "AVS_I2S_RXD_3"), + PINCTRL_PIN(114, "AVS_I2S_TXD_3"), + PINCTRL_PIN(115, "AVS_I2S_BCLK_4"), + PINCTRL_PIN(116, "AVS_I2S_SFRM_4"), + PINCTRL_PIN(117, "AVS_I2S_RXD_4"), + PINCTRL_PIN(118, "AVS_I2S_TXD_4"), + PINCTRL_PIN(119, "AVS_I2S_SFRM_5"), + PINCTRL_PIN(120, "AVS_I2S_RXD_5"), + PINCTRL_PIN(121, "AVS_I2S_TXD_5"), + PINCTRL_PIN(122, "AVS_I2S_BCLK_5"), + PINCTRL_PIN(123, "AVS_SNDW_CLK_0"), + PINCTRL_PIN(124, "AVS_SNDW_DATA_0"), + PINCTRL_PIN(125, "AVS_SNDW_CLK_1"), + PINCTRL_PIN(126, "AVS_SNDW_DATA_1"), + PINCTRL_PIN(127, "AVS_SNDW_CLK_2"), + PINCTRL_PIN(128, "AVS_SNDW_DATA_2"), + PINCTRL_PIN(129, "AVS_SNDW_CLK_3"), + PINCTRL_PIN(130, "AVS_SNDW_DATA_3"), + PINCTRL_PIN(131, "VISA_PTI_CH0_D0_internal"), + PINCTRL_PIN(132, "VISA_PTI_CH0_D1_internal"), + PINCTRL_PIN(133, "VISA_PTI_CH0_D2_internal"), + PINCTRL_PIN(134, "VISA_PTI_CH0_D3_internal"), + PINCTRL_PIN(135, "VISA_PTI_CH0_D4_internal"), + PINCTRL_PIN(136, "VISA_PTI_CH0_D5_internal"), + PINCTRL_PIN(137, "VISA_PTI_CH0_D6_internal"), + PINCTRL_PIN(138, "VISA_PTI_CH0_D7_internal"), + PINCTRL_PIN(139, "VISA_PTI_CH0_CLK_internal"), + PINCTRL_PIN(140, "VISA_PTI_CH1_D0_internal"), + PINCTRL_PIN(141, "VISA_PTI_CH1_D1_internal"), + PINCTRL_PIN(142, "VISA_PTI_CH1_D2_internal"), + PINCTRL_PIN(143, "VISA_PTI_CH1_D3_internal"), + PINCTRL_PIN(144, "VISA_PTI_CH1_D4_internal"), + PINCTRL_PIN(145, "VISA_PTI_CH1_D5_internal"), + PINCTRL_PIN(146, "VISA_PTI_CH1_D6_internal"), + PINCTRL_PIN(147, "VISA_PTI_CH1_D7_internal"), + PINCTRL_PIN(148, "VISA_PTI_CH1_CLK_internal"), + /* WEST */ + PINCTRL_PIN(149, "LPSS_UART0_TXD"), + PINCTRL_PIN(150, "LPSS_UART0_RXD"), + PINCTRL_PIN(151, "LPSS_UART0_RTS_B"), + PINCTRL_PIN(152, "LPSS_UART0_CTS_B"), + PINCTRL_PIN(153, "LPSS_UART1_RXD"), + PINCTRL_PIN(154, "LPSS_UART1_TXD"), + PINCTRL_PIN(155, "LPSS_UART1_RTS_B"), + PINCTRL_PIN(156, "LPSS_UART1_CTS_B"), + PINCTRL_PIN(157, "ISH_UART0_RXD"), + PINCTRL_PIN(158, "ISH_UART0_TXD"), + PINCTRL_PIN(159, "ISH_UART0_RTSB"), + PINCTRL_PIN(160, "ISH_UART0_CTSB"), + PINCTRL_PIN(161, "LPSS_SSP_0_CLK"), + PINCTRL_PIN(162, "LPSS_SSP_0_CLK_FB"), + PINCTRL_PIN(163, "LPSS_SSP_0_FS0"), + PINCTRL_PIN(164, "LPSS_SSP_0_FS1"), + PINCTRL_PIN(165, "LPSS_SSP_0_RXD"), + PINCTRL_PIN(166, "LPSS_SSP_0_TXD"), + PINCTRL_PIN(167, "ISH_UART1_RXD"), + PINCTRL_PIN(168, "ISH_UART1_TXD"), + PINCTRL_PIN(169, "ISH_UART1_RTSB"), + PINCTRL_PIN(170, "ISH_UART1_CTSB"), + PINCTRL_PIN(171, "LPSS_SSP_1_FS0"), + PINCTRL_PIN(172, "LPSS_SSP_1_FS1"), + PINCTRL_PIN(173, "LPSS_SSP_1_CLK"), + PINCTRL_PIN(174, "LPSS_SSP_1_CLK_FB"), + PINCTRL_PIN(175, "LPSS_SSP_1_RXD"), + PINCTRL_PIN(176, "LPSS_SSP_1_TXD"), + PINCTRL_PIN(177, "LPSS_SSP_2_CLK"), + PINCTRL_PIN(178, "LPSS_SSP_2_CLK_FB"), + PINCTRL_PIN(179, "LPSS_SSP_2_FS0"), + PINCTRL_PIN(180, "LPSS_SSP_2_FS1"), + PINCTRL_PIN(181, "LPSS_SSP_2_RXD"), + PINCTRL_PIN(182, "LPSS_SSP_2_TXD"), + PINCTRL_PIN(183, "ISH_SPI0_CSB0"), + PINCTRL_PIN(184, "ISH_SPI0_CSB1"), + PINCTRL_PIN(185, "ISH_SPI0_CLK"), + PINCTRL_PIN(186, "ISH_SPI0_MISO"), + PINCTRL_PIN(187, "ISH_SPI0_MOSI"), + PINCTRL_PIN(188, "ISH_GP_0"), + PINCTRL_PIN(189, "ISH_GP_1"), + PINCTRL_PIN(190, "ISH_GP_2"), + PINCTRL_PIN(191, "ISH_GP_13"), + PINCTRL_PIN(192, "ISH_GP_3"), + PINCTRL_PIN(193, "ISH_GP_4"), + PINCTRL_PIN(194, "ISH_GP_5"), + PINCTRL_PIN(195, "ISH_GP_6"), + PINCTRL_PIN(196, "ISH_GP_7"), + PINCTRL_PIN(197, "ISH_GP_8"), + PINCTRL_PIN(198, "ISH_GP_9"), + PINCTRL_PIN(199, "ISH_GP_10"), + PINCTRL_PIN(200, "ISH_GP_11"), + PINCTRL_PIN(201, "ISH_GP_14"), + PINCTRL_PIN(202, "ISH_GP_15"), + PINCTRL_PIN(203, "ISH_GP_22"), + PINCTRL_PIN(204, "ISH_GP_12"), + PINCTRL_PIN(205, "ISH_GP_30_USB_OC"), + PINCTRL_PIN(206, "LPDDRx_RESET0_n"), + PINCTRL_PIN(207, "UFS_RESET_B"), + PINCTRL_PIN(208, "UFS_REFCLK0"), + PINCTRL_PIN(209, "EMMC_SD_CLK"), + PINCTRL_PIN(210, "EMMC_SD_D0"), + PINCTRL_PIN(211, "EMMC_SD_D1"), + PINCTRL_PIN(212, "EMMC_SD_D2"), + PINCTRL_PIN(213, "EMMC_SD_D3"), + PINCTRL_PIN(214, "EMMC_D4"), + PINCTRL_PIN(215, "EMMC_D5"), + PINCTRL_PIN(216, "EMMC_D6"), + PINCTRL_PIN(217, "EMMC_D7"), + PINCTRL_PIN(218, "EMMC_SD_CMD"), + PINCTRL_PIN(219, "EMMC_RCLK"), + PINCTRL_PIN(220, "SDCARD_CLK_FB"), + PINCTRL_PIN(221, "SD_Virtual_GPIO"), + PINCTRL_PIN(222, "OSC_CLK_OUT_NFC"), + PINCTRL_PIN(223, "OSC_CLK_OUT_CAM_0"), + PINCTRL_PIN(224, "OSC_CLK_OUT_CAM_1"), + PINCTRL_PIN(225, "OSC_CLK_OUT_CAM_2"), + PINCTRL_PIN(226, "OSC_CLK_OUT_CAM_3"), + PINCTRL_PIN(227, "PCIe_LINKDOWN"), + PINCTRL_PIN(228, "NFC_CLK_REQ"), + PINCTRL_PIN(229, "PCIE_CLKREQ_N_DEV2"), + PINCTRL_PIN(230, "PCIE_CLKREQ_N_DEV3"), + PINCTRL_PIN(231, "PCIE_CLKREQ_N_DEV4"), + PINCTRL_PIN(232, "PCIE_CLKREQ_N_DEV1"), + PINCTRL_PIN(233, "PCIE_CLKREQ_N_DEV0"), + PINCTRL_PIN(234, "GMBUS_1_SCL"), + PINCTRL_PIN(235, "GMBUS_1_SDA"), + PINCTRL_PIN(236, "GMBUS_0_SCL"), + PINCTRL_PIN(237, "GMBUS_0_SDA"), + /* SOUTHEAST */ + PINCTRL_PIN(238, "COMPUTE_PMIC_SVID_DATA"), + PINCTRL_PIN(239, "COMPUTE_PMIC_SVID_CLK"), + PINCTRL_PIN(240, "COMPUTE_PMIC_SVID_ALERT_B"), + PINCTRL_PIN(241, "ROP_PMIC_I2C_SCL"), + PINCTRL_PIN(242, "ROP_PMIC_I2C_SDA"), + PINCTRL_PIN(243, "ISH_TYPEC_I2C2_SDA"), + PINCTRL_PIN(244, "ISH_TYPEC_I2C2_SCL"), + PINCTRL_PIN(245, "COMPUTE_PMU_PROCHOT_B"), + PINCTRL_PIN(246, "PMU_CATERR_B"), + PINCTRL_PIN(247, "COMPUTE_PMIC_VR_READY"), + PINCTRL_PIN(248, "FORCE_FW_RELOAD"), + PINCTRL_PIN(249, "ROP_PMIC_IRQ_ISH_GPIO31_TPC_ALERT_B"), + PINCTRL_PIN(250, "ROP_PMIC_RESET_B"), + PINCTRL_PIN(251, "ROP_PMIC_STNBY_SLP_S0_B"), + PINCTRL_PIN(252, "ROP_PMIC_THERMTRIP_B"), + PINCTRL_PIN(253, "MODEM_CLKREQ"), + PINCTRL_PIN(254, "TPC0_BSSB_SBU1"), + PINCTRL_PIN(255, "TPC0_BSSB_SBU2"), + PINCTRL_PIN(256, "OSC_CLK_OUT_CAM_4"), + PINCTRL_PIN(257, "HPD1"), + PINCTRL_PIN(258, "HPD0"), + PINCTRL_PIN(259, "PMC_TIME_SYNC_0"), + PINCTRL_PIN(260, "PMC_TIME_SYNC_1"), + PINCTRL_PIN(261, "OSC_CLK_OUT_CAM_5"), + PINCTRL_PIN(262, "ISH_GP_20"), + PINCTRL_PIN(263, "ISH_GP_16"), + PINCTRL_PIN(264, "ISH_GP_17"), + PINCTRL_PIN(265, "ISH_GP_18"), + PINCTRL_PIN(266, "ISH_GP_19"), +}; + +static const struct intel_padgroup lkf_community0_gpps[] = { + LKF_GPP(0, 0, 31, 0), /* EAST_0 */ + LKF_GPP(1, 32, 59, 32), /* EAST_1 */ +}; + +static const struct intel_padgroup lkf_community1_gpps[] = { + LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */ + LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */ + LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */ +}; + +static const struct intel_padgroup lkf_community2_gpps[] = { + LKF_GPP(0, 149, 180, 160), /* WEST_0 */ + LKF_GPP(1, 181, 212, 192), /* WEST_1 */ + LKF_GPP(2, 213, 237, 224), /* WEST_2 */ +}; + +static const struct intel_padgroup lkf_community3_gpps[] = { + LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */ +}; + +static const struct intel_community lkf_communities[] = { + LKF_COMMUNITY(0, 0, 59, lkf_community0_gpps), /* EAST */ + LKF_COMMUNITY(1, 60, 148, lkf_community1_gpps), /* NORTHWEST */ + LKF_COMMUNITY(2, 149, 237, lkf_community2_gpps), /* WEST */ + LKF_COMMUNITY(3, 238, 266, lkf_community3_gpps), /* SOUTHEAST */ +}; + +static const struct intel_pinctrl_soc_data lkf_soc_data = { + .pins = lkf_pins, + .npins = ARRAY_SIZE(lkf_pins), + .communities = lkf_communities, + .ncommunities = ARRAY_SIZE(lkf_communities), +}; + +static const struct acpi_device_id lkf_pinctrl_acpi_match[] = { + { "INT34C4", (kernel_ulong_t)&lkf_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, lkf_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(lkf_pinctrl_pm_ops); + +static struct platform_driver lkf_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "lakefield-pinctrl", + .acpi_match_table = lkf_pinctrl_acpi_match, + .pm = &lkf_pinctrl_pm_ops, + }, +}; +module_platform_driver(lkf_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_DESCRIPTION("Intel Lakefield PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); From 4670abbb298ed72be4d020d44f494deca21bff1e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 29 Oct 2020 13:17:28 +0200 Subject: [PATCH 04/80] pinctrl: intel: Add blank line before endif in Kconfig Add a blank line before endif directive in Kconfig for better readability. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 24a6fbcfbfc1..44b66bfe5021 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -151,4 +151,5 @@ config PINCTRL_TIGERLAKE help This pinctrl driver provides an interface that allows configuring of Intel Tiger Lake PCH pins and using them as GPIOs. + endif From c969afb4e55a2c6eec7c4195f67c5227be991393 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 2 Nov 2020 14:21:07 +0200 Subject: [PATCH 05/80] pinctrl: intel: Add Intel Elkhart Lake pin controller support This driver adds pinctrl/GPIO support for Intel Elkhart Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 8 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-elkhartlake.c | 513 ++++++++++++++++++++ 3 files changed, 522 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-elkhartlake.c diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 44b66bfe5021..3be9b939f4a9 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -87,6 +87,14 @@ config PINCTRL_DENVERTON This pinctrl driver provides an interface that allows configuring of Intel Denverton SoC pins and using them as GPIOs. +config PINCTRL_ELKHARTLAKE + tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Elkhart Lake SoC pins and using them as GPIOs. + config PINCTRL_EMMITSBURG tristate "Intel Emmitsburg pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 1ddfddecd3de..914162aa6ab4 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o +obj-$(CONFIG_PINCTRL_ELKHARTLAKE) += pinctrl-elkhartlake.o obj-$(CONFIG_PINCTRL_EMMITSBURG) += pinctrl-emmitsburg.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c new file mode 100644 index 000000000000..4702bdfa10e3 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Elkhart Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2019, Intel Corporation + * Author: Andy Shevchenko + */ + +#include +#include +#include + +#include + +#include "pinctrl-intel.h" + +#define EHL_PAD_OWN 0x020 +#define EHL_PADCFGLOCK 0x080 +#define EHL_HOSTSW_OWN 0x0b0 +#define EHL_GPI_IS 0x100 +#define EHL_GPI_IE 0x120 + +#define EHL_GPP(r, s, e) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + } + +#define EHL_COMMUNITY(s, e, g) \ + { \ + .padown_offset = EHL_PAD_OWN, \ + .padcfglock_offset = EHL_PADCFGLOCK, \ + .hostown_offset = EHL_HOSTSW_OWN, \ + .is_offset = EHL_GPI_IS, \ + .ie_offset = EHL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Elkhart Lake */ +static const struct pinctrl_pin_desc ehl_community0_pins[] = { + /* GPP_B */ + PINCTRL_PIN(0, "CORE_VID_0"), + PINCTRL_PIN(1, "CORE_VID_1"), + PINCTRL_PIN(2, "VRALERTB"), + PINCTRL_PIN(3, "CPU_GP_2"), + PINCTRL_PIN(4, "CPU_GP_3"), + PINCTRL_PIN(5, "OSE_I2C0_SCLK"), + PINCTRL_PIN(6, "OSE_I2C0_SDAT"), + PINCTRL_PIN(7, "OSE_I2C1_SCLK"), + PINCTRL_PIN(8, "OSE_I2C1_SDAT"), + PINCTRL_PIN(9, "I2C5_SDA"), + PINCTRL_PIN(10, "I2C5_SCL"), + PINCTRL_PIN(11, "PMCALERTB"), + PINCTRL_PIN(12, "SLP_S0B"), + PINCTRL_PIN(13, "PLTRSTB"), + PINCTRL_PIN(14, "SPKR"), + PINCTRL_PIN(15, "GSPI0_CS0B"), + PINCTRL_PIN(16, "GSPI0_CLK"), + PINCTRL_PIN(17, "GSPI0_MISO"), + PINCTRL_PIN(18, "GSPI0_MOSI"), + PINCTRL_PIN(19, "GSPI1_CS0B"), + PINCTRL_PIN(20, "GSPI1_CLK"), + PINCTRL_PIN(21, "GSPI1_MISO"), + PINCTRL_PIN(22, "GSPI1_MOSI"), + PINCTRL_PIN(23, "GPPC_B_23"), + PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), + /* GPP_T */ + PINCTRL_PIN(26, "OSE_QEPA_2"), + PINCTRL_PIN(27, "OSE_QEPB_2"), + PINCTRL_PIN(28, "OSE_QEPI_2"), + PINCTRL_PIN(29, "GPPC_T_3"), + PINCTRL_PIN(30, "RGMII0_INT"), + PINCTRL_PIN(31, "RGMII0_RESETB"), + PINCTRL_PIN(32, "RGMII0_AUXTS"), + PINCTRL_PIN(33, "RGMII0_PPS"), + PINCTRL_PIN(34, "USB2_OCB_2"), + PINCTRL_PIN(35, "OSE_HSUART2_EN"), + PINCTRL_PIN(36, "OSE_HSUART2_RE"), + PINCTRL_PIN(37, "USB2_OCB_3"), + PINCTRL_PIN(38, "OSE_UART2_RXD"), + PINCTRL_PIN(39, "OSE_UART2_TXD"), + PINCTRL_PIN(40, "OSE_UART2_RTSB"), + PINCTRL_PIN(41, "OSE_UART2_CTSB"), + /* GPP_G */ + PINCTRL_PIN(42, "SD3_CMD"), + PINCTRL_PIN(43, "SD3_D0"), + PINCTRL_PIN(44, "SD3_D1"), + PINCTRL_PIN(45, "SD3_D2"), + PINCTRL_PIN(46, "SD3_D3"), + PINCTRL_PIN(47, "SD3_CDB"), + PINCTRL_PIN(48, "SD3_CLK"), + PINCTRL_PIN(49, "I2S2_SCLK"), + PINCTRL_PIN(50, "I2S2_SFRM"), + PINCTRL_PIN(51, "I2S2_TXD"), + PINCTRL_PIN(52, "I2S2_RXD"), + PINCTRL_PIN(53, "I2S3_SCLK"), + PINCTRL_PIN(54, "I2S3_SFRM"), + PINCTRL_PIN(55, "I2S3_TXD"), + PINCTRL_PIN(56, "I2S3_RXD"), + PINCTRL_PIN(57, "ESPI_IO_0"), + PINCTRL_PIN(58, "ESPI_IO_1"), + PINCTRL_PIN(59, "ESPI_IO_2"), + PINCTRL_PIN(60, "ESPI_IO_3"), + PINCTRL_PIN(61, "I2S1_SCLK"), + PINCTRL_PIN(62, "ESPI_CSB"), + PINCTRL_PIN(63, "ESPI_CLK"), + PINCTRL_PIN(64, "ESPI_RESETB"), + PINCTRL_PIN(65, "SD3_WP"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), +}; + +static const struct intel_padgroup ehl_community0_gpps[] = { + EHL_GPP(0, 0, 25), /* GPP_B */ + EHL_GPP(1, 26, 41), /* GPP_T */ + EHL_GPP(2, 42, 66), /* GPP_G */ +}; + +static const struct intel_community ehl_community0[] = { + EHL_COMMUNITY(0, 66, ehl_community0_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community0_soc_data = { + .uid = "0", + .pins = ehl_community0_pins, + .npins = ARRAY_SIZE(ehl_community0_pins), + .communities = ehl_community0, + .ncommunities = ARRAY_SIZE(ehl_community0), +}; + +static const struct pinctrl_pin_desc ehl_community1_pins[] = { + /* GPP_V */ + PINCTRL_PIN(0, "EMMC_CMD"), + PINCTRL_PIN(1, "EMMC_DATA0"), + PINCTRL_PIN(2, "EMMC_DATA1"), + PINCTRL_PIN(3, "EMMC_DATA2"), + PINCTRL_PIN(4, "EMMC_DATA3"), + PINCTRL_PIN(5, "EMMC_DATA4"), + PINCTRL_PIN(6, "EMMC_DATA5"), + PINCTRL_PIN(7, "EMMC_DATA6"), + PINCTRL_PIN(8, "EMMC_DATA7"), + PINCTRL_PIN(9, "EMMC_RCLK"), + PINCTRL_PIN(10, "EMMC_CLK"), + PINCTRL_PIN(11, "EMMC_RESETB"), + PINCTRL_PIN(12, "OSE_TGPIO0"), + PINCTRL_PIN(13, "OSE_TGPIO1"), + PINCTRL_PIN(14, "OSE_TGPIO2"), + PINCTRL_PIN(15, "OSE_TGPIO3"), + /* GPP_H */ + PINCTRL_PIN(16, "RGMII1_INT"), + PINCTRL_PIN(17, "RGMII1_RESETB"), + PINCTRL_PIN(18, "RGMII1_AUXTS"), + PINCTRL_PIN(19, "RGMII1_PPS"), + PINCTRL_PIN(20, "I2C2_SDA"), + PINCTRL_PIN(21, "I2C2_SCL"), + PINCTRL_PIN(22, "I2C3_SDA"), + PINCTRL_PIN(23, "I2C3_SCL"), + PINCTRL_PIN(24, "I2C4_SDA"), + PINCTRL_PIN(25, "I2C4_SCL"), + PINCTRL_PIN(26, "SRCCLKREQB_4"), + PINCTRL_PIN(27, "SRCCLKREQB_5"), + PINCTRL_PIN(28, "OSE_UART1_RXD"), + PINCTRL_PIN(29, "OSE_UART1_TXD"), + PINCTRL_PIN(30, "GPPC_H_14"), + PINCTRL_PIN(31, "OSE_UART1_CTSB"), + PINCTRL_PIN(32, "PCIE_LNK_DOWN"), + PINCTRL_PIN(33, "SD_PWR_EN_B"), + PINCTRL_PIN(34, "CPU_C10_GATEB"), + PINCTRL_PIN(35, "GPPC_H_19"), + PINCTRL_PIN(36, "OSE_PWM7"), + PINCTRL_PIN(37, "OSE_HSUART1_DE"), + PINCTRL_PIN(38, "OSE_HSUART1_RE"), + PINCTRL_PIN(39, "OSE_HSUART1_EN"), + /* GPP_D */ + PINCTRL_PIN(40, "OSE_QEPA_0"), + PINCTRL_PIN(41, "OSE_QEPB_0"), + PINCTRL_PIN(42, "OSE_QEPI_0"), + PINCTRL_PIN(43, "OSE_PWM6"), + PINCTRL_PIN(44, "OSE_PWM2"), + PINCTRL_PIN(45, "SRCCLKREQB_0"), + PINCTRL_PIN(46, "SRCCLKREQB_1"), + PINCTRL_PIN(47, "SRCCLKREQB_2"), + PINCTRL_PIN(48, "SRCCLKREQB_3"), + PINCTRL_PIN(49, "OSE_SPI0_CSB"), + PINCTRL_PIN(50, "OSE_SPI0_SCLK"), + PINCTRL_PIN(51, "OSE_SPI0_MISO"), + PINCTRL_PIN(52, "OSE_SPI0_MOSI"), + PINCTRL_PIN(53, "OSE_QEPA_1"), + PINCTRL_PIN(54, "OSE_QEPB_1"), + PINCTRL_PIN(55, "OSE_PWM3"), + PINCTRL_PIN(56, "OSE_QEPI_1"), + PINCTRL_PIN(57, "OSE_PWM4"), + PINCTRL_PIN(58, "OSE_PWM5"), + PINCTRL_PIN(59, "I2S_MCLK1_OUT"), + PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"), + /* GPP_U */ + PINCTRL_PIN(61, "RGMII2_INT"), + PINCTRL_PIN(62, "RGMII2_RESETB"), + PINCTRL_PIN(63, "RGMII2_PPS"), + PINCTRL_PIN(64, "RGMII2_AUXTS"), + PINCTRL_PIN(65, "ISI_SPIM_CS"), + PINCTRL_PIN(66, "ISI_SPIM_SCLK"), + PINCTRL_PIN(67, "ISI_SPIM_MISO"), + PINCTRL_PIN(68, "OSE_QEPA_3"), + PINCTRL_PIN(69, "ISI_SPIS_CS"), + PINCTRL_PIN(70, "ISI_SPIS_SCLK"), + PINCTRL_PIN(71, "ISI_SPIS_MISO"), + PINCTRL_PIN(72, "OSE_QEPB_3"), + PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"), + PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"), + PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"), + PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"), + PINCTRL_PIN(77, "ISI_OKNOK_0"), + PINCTRL_PIN(78, "ISI_OKNOK_1"), + PINCTRL_PIN(79, "ISI_ALERT"), + PINCTRL_PIN(80, "OSE_QEPI_3"), + PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"), + PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"), + PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"), + PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(85, "CNV_BTEN"), + PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(87, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(88, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(89, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(92, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(93, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(96, "vUART0_TXD"), + PINCTRL_PIN(97, "vUART0_RXD"), + PINCTRL_PIN(98, "vUART0_CTS_B"), + PINCTRL_PIN(99, "vUART0_RTS_B"), + PINCTRL_PIN(100, "vOSE_UART0_TXD"), + PINCTRL_PIN(101, "vOSE_UART0_RXD"), + PINCTRL_PIN(102, "vOSE_UART0_CTS_B"), + PINCTRL_PIN(103, "vOSE_UART0_RTS_B"), + PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(108, "vI2S2_SCLK"), + PINCTRL_PIN(109, "vI2S2_SFRM"), + PINCTRL_PIN(110, "vI2S2_TXD"), + PINCTRL_PIN(111, "vI2S2_RXD"), + PINCTRL_PIN(112, "vSD3_CD_B"), +}; + +static const struct intel_padgroup ehl_community1_gpps[] = { + EHL_GPP(0, 0, 15), /* GPP_V */ + EHL_GPP(1, 16, 39), /* GPP_H */ + EHL_GPP(2, 40, 60), /* GPP_D */ + EHL_GPP(3, 61, 84), /* GPP_U */ + EHL_GPP(4, 85, 112), /* vGPIO */ +}; + +static const struct intel_community ehl_community1[] = { + EHL_COMMUNITY(0, 112, ehl_community1_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community1_soc_data = { + .uid = "1", + .pins = ehl_community1_pins, + .npins = ARRAY_SIZE(ehl_community1_pins), + .communities = ehl_community1, + .ncommunities = ARRAY_SIZE(ehl_community1), +}; + +static const struct pinctrl_pin_desc ehl_community3_pins[] = { + /* CPU */ + PINCTRL_PIN(0, "HDACPU_SDI"), + PINCTRL_PIN(1, "HDACPU_SDO"), + PINCTRL_PIN(2, "HDACPU_BCLK"), + PINCTRL_PIN(3, "PM_SYNC"), + PINCTRL_PIN(4, "PECI"), + PINCTRL_PIN(5, "CPUPWRGD"), + PINCTRL_PIN(6, "THRMTRIPB"), + PINCTRL_PIN(7, "PLTRST_CPUB"), + PINCTRL_PIN(8, "PM_DOWN"), + PINCTRL_PIN(9, "TRIGGER_IN"), + PINCTRL_PIN(10, "TRIGGER_OUT"), + PINCTRL_PIN(11, "UFS_RESETB"), + PINCTRL_PIN(12, "CLKOUT_CPURTC"), + PINCTRL_PIN(13, "VCCST_OVERRIDE"), + PINCTRL_PIN(14, "C10_WAKE"), + PINCTRL_PIN(15, "PROCHOTB"), + PINCTRL_PIN(16, "CATERRB"), + /* GPP_S */ + PINCTRL_PIN(17, "UFS_REF_CLK_0"), + PINCTRL_PIN(18, "UFS_REF_CLK_1"), + /* GPP_A */ + PINCTRL_PIN(19, "RGMII0_TXDATA_3"), + PINCTRL_PIN(20, "RGMII0_TXDATA_2"), + PINCTRL_PIN(21, "RGMII0_TXDATA_1"), + PINCTRL_PIN(22, "RGMII0_TXDATA_0"), + PINCTRL_PIN(23, "RGMII0_TXCLK"), + PINCTRL_PIN(24, "RGMII0_TXCTL"), + PINCTRL_PIN(25, "RGMII0_RXCLK"), + PINCTRL_PIN(26, "RGMII0_RXDATA_3"), + PINCTRL_PIN(27, "RGMII0_RXDATA_2"), + PINCTRL_PIN(28, "RGMII0_RXDATA_1"), + PINCTRL_PIN(29, "RGMII0_RXDATA_0"), + PINCTRL_PIN(30, "RGMII1_TXDATA_3"), + PINCTRL_PIN(31, "RGMII1_TXDATA_2"), + PINCTRL_PIN(32, "RGMII1_TXDATA_1"), + PINCTRL_PIN(33, "RGMII1_TXDATA_0"), + PINCTRL_PIN(34, "RGMII1_TXCLK"), + PINCTRL_PIN(35, "RGMII1_TXCTL"), + PINCTRL_PIN(36, "RGMII1_RXCLK"), + PINCTRL_PIN(37, "RGMII1_RXCTL"), + PINCTRL_PIN(38, "RGMII1_RXDATA_3"), + PINCTRL_PIN(39, "RGMII1_RXDATA_2"), + PINCTRL_PIN(40, "RGMII1_RXDATA_1"), + PINCTRL_PIN(41, "RGMII1_RXDATA_0"), + PINCTRL_PIN(42, "RGMII0_RXCTL"), + /* vGPIO_3 */ + PINCTRL_PIN(43, "ESPI_USB_OCB_0"), + PINCTRL_PIN(44, "ESPI_USB_OCB_1"), + PINCTRL_PIN(45, "ESPI_USB_OCB_2"), + PINCTRL_PIN(46, "ESPI_USB_OCB_3"), +}; + +static const struct intel_padgroup ehl_community3_gpps[] = { + EHL_GPP(0, 0, 16), /* CPU */ + EHL_GPP(1, 17, 18), /* GPP_S */ + EHL_GPP(2, 19, 42), /* GPP_A */ + EHL_GPP(3, 43, 46), /* vGPIO_3 */ +}; + +static const struct intel_community ehl_community3[] = { + EHL_COMMUNITY(0, 46, ehl_community3_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community3_soc_data = { + .uid = "3", + .pins = ehl_community3_pins, + .npins = ARRAY_SIZE(ehl_community3_pins), + .communities = ehl_community3, + .ncommunities = ARRAY_SIZE(ehl_community3), +}; + +static const struct pinctrl_pin_desc ehl_community4_pins[] = { + /* GPP_C */ + PINCTRL_PIN(0, "SMBCLK"), + PINCTRL_PIN(1, "SMBDATA"), + PINCTRL_PIN(2, "OSE_PWM0"), + PINCTRL_PIN(3, "RGMII0_MDC"), + PINCTRL_PIN(4, "RGMII0_MDIO"), + PINCTRL_PIN(5, "OSE_PWM1"), + PINCTRL_PIN(6, "RGMII1_MDC"), + PINCTRL_PIN(7, "RGMII1_MDIO"), + PINCTRL_PIN(8, "OSE_TGPIO4"), + PINCTRL_PIN(9, "OSE_HSUART0_EN"), + PINCTRL_PIN(10, "OSE_TGPIO5"), + PINCTRL_PIN(11, "OSE_HSUART0_RE"), + PINCTRL_PIN(12, "OSE_UART0_RXD"), + PINCTRL_PIN(13, "OSE_UART0_TXD"), + PINCTRL_PIN(14, "OSE_UART0_RTSB"), + PINCTRL_PIN(15, "OSE_UART0_CTSB"), + PINCTRL_PIN(16, "RGMII2_MDIO"), + PINCTRL_PIN(17, "RGMII2_MDC"), + PINCTRL_PIN(18, "OSE_I2C4_SDAT"), + PINCTRL_PIN(19, "OSE_I2C4_SCLK"), + PINCTRL_PIN(20, "OSE_UART4_RXD"), + PINCTRL_PIN(21, "OSE_UART4_TXD"), + PINCTRL_PIN(22, "OSE_UART4_RTSB"), + PINCTRL_PIN(23, "OSE_UART4_CTSB"), + /* GPP_F */ + PINCTRL_PIN(24, "CNV_BRI_DT"), + PINCTRL_PIN(25, "CNV_BRI_RSP"), + PINCTRL_PIN(26, "CNV_RGI_DT"), + PINCTRL_PIN(27, "CNV_RGI_RSP"), + PINCTRL_PIN(28, "CNV_RF_RESET_B"), + PINCTRL_PIN(29, "EMMC_HIP_MON"), + PINCTRL_PIN(30, "CNV_PA_BLANKING"), + PINCTRL_PIN(31, "OSE_I2S1_SCLK"), + PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), + PINCTRL_PIN(33, "BOOTMPC"), + PINCTRL_PIN(34, "OSE_I2S1_SFRM"), + PINCTRL_PIN(35, "GPPC_F_11"), + PINCTRL_PIN(36, "GSXDOUT"), + PINCTRL_PIN(37, "GSXSLOAD"), + PINCTRL_PIN(38, "GSXDIN"), + PINCTRL_PIN(39, "GSXSRESETB"), + PINCTRL_PIN(40, "GSXCLK"), + PINCTRL_PIN(41, "GPPC_F_17"), + PINCTRL_PIN(42, "OSE_I2S1_TXD"), + PINCTRL_PIN(43, "OSE_I2S1_RXD"), + PINCTRL_PIN(44, "EXT_PWR_GATEB"), + PINCTRL_PIN(45, "EXT_PWR_GATE2B"), + PINCTRL_PIN(46, "VNN_CTRL"), + PINCTRL_PIN(47, "V1P05_CTRL"), + PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), + /* HVCMOS */ + PINCTRL_PIN(49, "L_BKLTEN"), + PINCTRL_PIN(50, "L_BKLTCTL"), + PINCTRL_PIN(51, "L_VDDEN"), + PINCTRL_PIN(52, "SYS_PWROK"), + PINCTRL_PIN(53, "SYS_RESETB"), + PINCTRL_PIN(54, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(55, "SATA_LEDB"), + PINCTRL_PIN(56, "GPPC_E_1"), + PINCTRL_PIN(57, "GPPC_E_2"), + PINCTRL_PIN(58, "DDSP_HPD_B"), + PINCTRL_PIN(59, "SATA_DEVSLP_0"), + PINCTRL_PIN(60, "DDPB_CTRLDATA"), + PINCTRL_PIN(61, "GPPC_E_6"), + PINCTRL_PIN(62, "DDPB_CTRLCLK"), + PINCTRL_PIN(63, "GPPC_E_8"), + PINCTRL_PIN(64, "USB2_OCB_0"), + PINCTRL_PIN(65, "GPPC_E_10"), + PINCTRL_PIN(66, "GPPC_E_11"), + PINCTRL_PIN(67, "GPPC_E_12"), + PINCTRL_PIN(68, "GPPC_E_13"), + PINCTRL_PIN(69, "DDSP_HPD_A"), + PINCTRL_PIN(70, "OSE_I2S0_RXD"), + PINCTRL_PIN(71, "OSE_I2S0_TXD"), + PINCTRL_PIN(72, "DDSP_HPD_C"), + PINCTRL_PIN(73, "DDPA_CTRLDATA"), + PINCTRL_PIN(74, "DDPA_CTRLCLK"), + PINCTRL_PIN(75, "OSE_I2S0_SCLK"), + PINCTRL_PIN(76, "OSE_I2S0_SFRM"), + PINCTRL_PIN(77, "DDPC_CTRLDATA"), + PINCTRL_PIN(78, "DDPC_CTRLCLK"), + PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), +}; + +static const struct intel_padgroup ehl_community4_gpps[] = { + EHL_GPP(0, 0, 23), /* GPP_C */ + EHL_GPP(1, 24, 48), /* GPP_F */ + EHL_GPP(2, 49, 54), /* HVCMOS */ + EHL_GPP(3, 55, 79), /* GPP_E */ +}; + +static const struct intel_community ehl_community4[] = { + EHL_COMMUNITY(0, 79, ehl_community4_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community4_soc_data = { + .uid = "4", + .pins = ehl_community4_pins, + .npins = ARRAY_SIZE(ehl_community4_pins), + .communities = ehl_community4, + .ncommunities = ARRAY_SIZE(ehl_community4), +}; + +static const struct pinctrl_pin_desc ehl_community5_pins[] = { + /* GPP_R */ + PINCTRL_PIN(0, "HDA_BCLK"), + PINCTRL_PIN(1, "HDA_SYNC"), + PINCTRL_PIN(2, "HDA_SDO"), + PINCTRL_PIN(3, "HDA_SDI_0"), + PINCTRL_PIN(4, "HDA_RSTB"), + PINCTRL_PIN(5, "HDA_SDI_1"), + PINCTRL_PIN(6, "GPP_R_6"), + PINCTRL_PIN(7, "GPP_R_7"), +}; + +static const struct intel_padgroup ehl_community5_gpps[] = { + EHL_GPP(0, 0, 7), /* GPP_R */ +}; + +static const struct intel_community ehl_community5[] = { + EHL_COMMUNITY(0, 7, ehl_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community5_soc_data = { + .uid = "5", + .pins = ehl_community5_pins, + .npins = ARRAY_SIZE(ehl_community5_pins), + .communities = ehl_community5, + .ncommunities = ARRAY_SIZE(ehl_community5), +}; + +static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = { + &ehl_community0_soc_data, + &ehl_community1_soc_data, + &ehl_community3_soc_data, + &ehl_community4_soc_data, + &ehl_community5_soc_data, + NULL +}; + +static const struct acpi_device_id ehl_pinctrl_acpi_match[] = { + { "INTC1020", (kernel_ulong_t)ehl_soc_data_array }, + { } +}; +MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops); + +static struct platform_driver ehl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_uid, + .driver = { + .name = "elkhartlake-pinctrl", + .acpi_match_table = ehl_pinctrl_acpi_match, + .pm = &ehl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(ehl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); From e789e61f9e852a4cc31042810b34552f6de667b2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 29 Oct 2020 13:13:15 +0200 Subject: [PATCH 06/80] pinctrl: intel: Add Intel Alder Lake-S pin controller support This driver adds pinctrl/GPIO support for Intel Alder Lake-S SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 8 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-alderlake.c | 437 ++++++++++++++++++++++ 3 files changed, 446 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-alderlake.c diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 3be9b939f4a9..fb1495bd77c4 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -55,6 +55,14 @@ config PINCTRL_INTEL select GPIOLIB select GPIOLIB_IRQCHIP +config PINCTRL_ALDERLAKE + tristate "Intel Alder Lake pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Alder Lake PCH pins and using them as GPIOs. + config PINCTRL_BROXTON tristate "Intel Broxton pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 914162aa6ab4..181ffcf34d62 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o +obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c new file mode 100644 index 000000000000..efb664f12b5d --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Alder Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko + */ + +#include +#include +#include + +#include + +#include "pinctrl-intel.h" + +#define ADL_PAD_OWN 0x0a0 +#define ADL_PADCFGLOCK 0x110 +#define ADL_HOSTSW_OWN 0x150 +#define ADL_GPI_IS 0x200 +#define ADL_GPI_IE 0x220 + +#define ADL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define ADL_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = ADL_PAD_OWN, \ + .padcfglock_offset = ADL_PADCFGLOCK, \ + .hostown_offset = ADL_HOSTSW_OWN, \ + .is_offset = ADL_GPI_IS, \ + .ie_offset = ADL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Alder Lake-S */ +static const struct pinctrl_pin_desc adls_pins[] = { + /* GPP_I */ + PINCTRL_PIN(0, "EXT_PWR_GATEB"), + PINCTRL_PIN(1, "DDSP_HPD_1"), + PINCTRL_PIN(2, "DDSP_HPD_2"), + PINCTRL_PIN(3, "DDSP_HPD_3"), + PINCTRL_PIN(4, "DDSP_HPD_4"), + PINCTRL_PIN(5, "DDPB_CTRLCLK"), + PINCTRL_PIN(6, "DDPB_CTRLDATA"), + PINCTRL_PIN(7, "DDPC_CTRLCLK"), + PINCTRL_PIN(8, "DDPC_CTRLDATA"), + PINCTRL_PIN(9, "GSPI0_CS1B"), + PINCTRL_PIN(10, "GSPI1_CS1B"), + PINCTRL_PIN(11, "USB2_OCB_4"), + PINCTRL_PIN(12, "USB2_OCB_5"), + PINCTRL_PIN(13, "USB2_OCB_6"), + PINCTRL_PIN(14, "USB2_OCB_7"), + PINCTRL_PIN(15, "GSPI0_CS0B"), + PINCTRL_PIN(16, "GSPI0_CLK"), + PINCTRL_PIN(17, "GSPI0_MISO"), + PINCTRL_PIN(18, "GSPI0_MOSI"), + PINCTRL_PIN(19, "GSPI1_CS0B"), + PINCTRL_PIN(20, "GSPI1_CLK"), + PINCTRL_PIN(21, "GSPI1_MISO"), + PINCTRL_PIN(22, "GSPI1_MOSI"), + PINCTRL_PIN(23, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(24, "GSPI1_CLK_LOOPBK"), + /* GPP_R */ + PINCTRL_PIN(25, "HDA_BCLK"), + PINCTRL_PIN(26, "HDA_SYNC"), + PINCTRL_PIN(27, "HDA_SDO"), + PINCTRL_PIN(28, "HDA_SDI_0"), + PINCTRL_PIN(29, "HDA_RSTB"), + PINCTRL_PIN(30, "HDA_SDI_1"), + PINCTRL_PIN(31, "GPP_R_6"), + PINCTRL_PIN(32, "GPP_R_7"), + PINCTRL_PIN(33, "GPP_R_8"), + PINCTRL_PIN(34, "DDSP_HPD_A"), + PINCTRL_PIN(35, "DDSP_HPD_B"), + PINCTRL_PIN(36, "DDSP_HPD_C"), + PINCTRL_PIN(37, "ISH_SPI_CSB"), + PINCTRL_PIN(38, "ISH_SPI_CLK"), + PINCTRL_PIN(39, "ISH_SPI_MISO"), + PINCTRL_PIN(40, "ISH_SPI_MOSI"), + PINCTRL_PIN(41, "DDP1_CTRLCLK"), + PINCTRL_PIN(42, "DDP1_CTRLDATA"), + PINCTRL_PIN(43, "DDP2_CTRLCLK"), + PINCTRL_PIN(44, "DDP2_CTRLDATA"), + PINCTRL_PIN(45, "DDPA_CTRLCLK"), + PINCTRL_PIN(46, "DDPA_CTRLDATA"), + PINCTRL_PIN(47, "GSPI2_CLK_LOOPBK"), + /* GPP_J */ + PINCTRL_PIN(48, "CNV_PA_BLANKING"), + PINCTRL_PIN(49, "CPU_C10_GATEB"), + PINCTRL_PIN(50, "CNV_BRI_DT"), + PINCTRL_PIN(51, "CNV_BRI_RSP"), + PINCTRL_PIN(52, "CNV_RGI_DT"), + PINCTRL_PIN(53, "CNV_RGI_RSP"), + PINCTRL_PIN(54, "CNV_MFUART2_RXD"), + PINCTRL_PIN(55, "CNV_MFUART2_TXD"), + PINCTRL_PIN(56, "SRCCLKREQB_16"), + PINCTRL_PIN(57, "SRCCLKREQB_17"), + PINCTRL_PIN(58, "BSSB_LS_RX"), + PINCTRL_PIN(59, "BSSB_LS_TX"), + /* vGPIO */ + PINCTRL_PIN(60, "CNV_BTEN"), + PINCTRL_PIN(61, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(62, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(63, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(64, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(65, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(66, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(67, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(68, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(69, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(70, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(71, "vUART0_TXD"), + PINCTRL_PIN(72, "vUART0_RXD"), + PINCTRL_PIN(73, "vUART0_CTS_B"), + PINCTRL_PIN(74, "vUART0_RTS_B"), + PINCTRL_PIN(75, "vISH_UART0_TXD"), + PINCTRL_PIN(76, "vISH_UART0_RXD"), + PINCTRL_PIN(77, "vISH_UART0_CTS_B"), + PINCTRL_PIN(78, "vISH_UART0_RTS_B"), + PINCTRL_PIN(79, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(80, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(81, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(82, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(83, "vI2S2_SCLK"), + PINCTRL_PIN(84, "vI2S2_SFRM"), + PINCTRL_PIN(85, "vI2S2_TXD"), + PINCTRL_PIN(86, "vI2S2_RXD"), + /* vGPIO_0 */ + PINCTRL_PIN(87, "ESPI_USB_OCB_0"), + PINCTRL_PIN(88, "ESPI_USB_OCB_1"), + PINCTRL_PIN(89, "ESPI_USB_OCB_2"), + PINCTRL_PIN(90, "ESPI_USB_OCB_3"), + PINCTRL_PIN(91, "USB_CPU_OCB_0"), + PINCTRL_PIN(92, "USB_CPU_OCB_1"), + PINCTRL_PIN(93, "USB_CPU_OCB_2"), + PINCTRL_PIN(94, "USB_CPU_OCB_3"), + /* GPP_B */ + PINCTRL_PIN(95, "PCIE_LNK_DOWN"), + PINCTRL_PIN(96, "ISH_UART0_RTSB"), + PINCTRL_PIN(97, "VRALERTB"), + PINCTRL_PIN(98, "CPU_GP_2"), + PINCTRL_PIN(99, "CPU_GP_3"), + PINCTRL_PIN(100, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(101, "CLKOUT_48"), + PINCTRL_PIN(102, "ISH_GP_7"), + PINCTRL_PIN(103, "ISH_GP_0"), + PINCTRL_PIN(104, "ISH_GP_1"), + PINCTRL_PIN(105, "ISH_GP_2"), + PINCTRL_PIN(106, "I2S_MCLK"), + PINCTRL_PIN(107, "SLP_S0B"), + PINCTRL_PIN(108, "PLTRSTB"), + PINCTRL_PIN(109, "SPKR"), + PINCTRL_PIN(110, "ISH_GP_3"), + PINCTRL_PIN(111, "ISH_GP_4"), + PINCTRL_PIN(112, "ISH_GP_5"), + PINCTRL_PIN(113, "PMCALERTB"), + PINCTRL_PIN(114, "FUSA_DIAGTEST_EN"), + PINCTRL_PIN(115, "FUSA_DIAGTEST_MODE"), + PINCTRL_PIN(116, "GPP_B_21"), + PINCTRL_PIN(117, "GPP_B_22"), + PINCTRL_PIN(118, "SML1ALERTB"), + /* GPP_G */ + PINCTRL_PIN(119, "GPP_G_0"), + PINCTRL_PIN(120, "GPP_G_1"), + PINCTRL_PIN(121, "DNX_FORCE_RELOAD"), + PINCTRL_PIN(122, "GMII_MDC_0"), + PINCTRL_PIN(123, "GMII_MDIO_0"), + PINCTRL_PIN(124, "SLP_DRAMB"), + PINCTRL_PIN(125, "GPP_G_6"), + PINCTRL_PIN(126, "GPP_G_7"), + /* GPP_H */ + PINCTRL_PIN(127, "SRCCLKREQB_18"), + PINCTRL_PIN(128, "GPP_H_1"), + PINCTRL_PIN(129, "SRCCLKREQB_8"), + PINCTRL_PIN(130, "SRCCLKREQB_9"), + PINCTRL_PIN(131, "SRCCLKREQB_10"), + PINCTRL_PIN(132, "SRCCLKREQB_11"), + PINCTRL_PIN(133, "SRCCLKREQB_12"), + PINCTRL_PIN(134, "SRCCLKREQB_13"), + PINCTRL_PIN(135, "SRCCLKREQB_14"), + PINCTRL_PIN(136, "SRCCLKREQB_15"), + PINCTRL_PIN(137, "SML2CLK"), + PINCTRL_PIN(138, "SML2DATA"), + PINCTRL_PIN(139, "SML2ALERTB"), + PINCTRL_PIN(140, "SML3CLK"), + PINCTRL_PIN(141, "SML3DATA"), + PINCTRL_PIN(142, "SML3ALERTB"), + PINCTRL_PIN(143, "SML4CLK"), + PINCTRL_PIN(144, "SML4DATA"), + PINCTRL_PIN(145, "SML4ALERTB"), + PINCTRL_PIN(146, "ISH_I2C0_SDA"), + PINCTRL_PIN(147, "ISH_I2C0_SCL"), + PINCTRL_PIN(148, "ISH_I2C1_SDA"), + PINCTRL_PIN(149, "ISH_I2C1_SCL"), + PINCTRL_PIN(150, "TIME_SYNC_0"), + /* SPI0 */ + PINCTRL_PIN(151, "SPI0_IO_2"), + PINCTRL_PIN(152, "SPI0_IO_3"), + PINCTRL_PIN(153, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(154, "SPI0_MISO_IO_1"), + PINCTRL_PIN(155, "SPI0_TPM_CSB"), + PINCTRL_PIN(156, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(157, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(158, "SPI0_CLK"), + PINCTRL_PIN(159, "SPI0_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(160, "ESPI_IO_0"), + PINCTRL_PIN(161, "ESPI_IO_1"), + PINCTRL_PIN(162, "ESPI_IO_2"), + PINCTRL_PIN(163, "ESPI_IO_3"), + PINCTRL_PIN(164, "ESPI_CS0B"), + PINCTRL_PIN(165, "ESPI_CLK"), + PINCTRL_PIN(166, "ESPI_RESETB"), + PINCTRL_PIN(167, "ESPI_CS1B"), + PINCTRL_PIN(168, "ESPI_CS2B"), + PINCTRL_PIN(169, "ESPI_CS3B"), + PINCTRL_PIN(170, "ESPI_ALERT0B"), + PINCTRL_PIN(171, "ESPI_ALERT1B"), + PINCTRL_PIN(172, "ESPI_ALERT2B"), + PINCTRL_PIN(173, "ESPI_ALERT3B"), + PINCTRL_PIN(174, "GPP_A_14"), + PINCTRL_PIN(175, "ESPI_CLK_LOOPBK"), + /* GPP_C */ + PINCTRL_PIN(176, "SMBCLK"), + PINCTRL_PIN(177, "SMBDATA"), + PINCTRL_PIN(178, "SMBALERTB"), + PINCTRL_PIN(179, "ISH_UART0_RXD"), + PINCTRL_PIN(180, "ISH_UART0_TXD"), + PINCTRL_PIN(181, "SML0ALERTB"), + PINCTRL_PIN(182, "ISH_I2C2_SDA"), + PINCTRL_PIN(183, "ISH_I2C2_SCL"), + PINCTRL_PIN(184, "UART0_RXD"), + PINCTRL_PIN(185, "UART0_TXD"), + PINCTRL_PIN(186, "UART0_RTSB"), + PINCTRL_PIN(187, "UART0_CTSB"), + PINCTRL_PIN(188, "UART1_RXD"), + PINCTRL_PIN(189, "UART1_TXD"), + PINCTRL_PIN(190, "UART1_RTSB"), + PINCTRL_PIN(191, "UART1_CTSB"), + PINCTRL_PIN(192, "I2C0_SDA"), + PINCTRL_PIN(193, "I2C0_SCL"), + PINCTRL_PIN(194, "I2C1_SDA"), + PINCTRL_PIN(195, "I2C1_SCL"), + PINCTRL_PIN(196, "UART2_RXD"), + PINCTRL_PIN(197, "UART2_TXD"), + PINCTRL_PIN(198, "UART2_RTSB"), + PINCTRL_PIN(199, "UART2_CTSB"), + /* GPP_S */ + PINCTRL_PIN(200, "SNDW1_CLK"), + PINCTRL_PIN(201, "SNDW1_DATA"), + PINCTRL_PIN(202, "SNDW2_CLK"), + PINCTRL_PIN(203, "SNDW2_DATA"), + PINCTRL_PIN(204, "SNDW3_CLK"), + PINCTRL_PIN(205, "SNDW3_DATA"), + PINCTRL_PIN(206, "SNDW4_CLK"), + PINCTRL_PIN(207, "SNDW4_DATA"), + /* GPP_E */ + PINCTRL_PIN(208, "SATAXPCIE_0"), + PINCTRL_PIN(209, "SATAXPCIE_1"), + PINCTRL_PIN(210, "SATAXPCIE_2"), + PINCTRL_PIN(211, "CPU_GP_0"), + PINCTRL_PIN(212, "SATA_DEVSLP_0"), + PINCTRL_PIN(213, "SATA_DEVSLP_1"), + PINCTRL_PIN(214, "SATA_DEVSLP_2"), + PINCTRL_PIN(215, "CPU_GP_1"), + PINCTRL_PIN(216, "SATA_LEDB"), + PINCTRL_PIN(217, "USB2_OCB_0"), + PINCTRL_PIN(218, "USB2_OCB_1"), + PINCTRL_PIN(219, "USB2_OCB_2"), + PINCTRL_PIN(220, "USB2_OCB_3"), + PINCTRL_PIN(221, "SPI1_CSB"), + PINCTRL_PIN(222, "SPI1_CLK"), + PINCTRL_PIN(223, "SPI1_MISO_IO_1"), + PINCTRL_PIN(224, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(225, "SPI1_IO_2"), + PINCTRL_PIN(226, "SPI1_IO_3"), + PINCTRL_PIN(227, "GPP_E_19"), + PINCTRL_PIN(228, "GPP_E_20"), + PINCTRL_PIN(229, "ISH_UART0_CTSB"), + PINCTRL_PIN(230, "SPI1_CLK_LOOPBK"), + /* GPP_K */ + PINCTRL_PIN(231, "GSXDOUT"), + PINCTRL_PIN(232, "GSXSLOAD"), + PINCTRL_PIN(233, "GSXDIN"), + PINCTRL_PIN(234, "GSXSRESETB"), + PINCTRL_PIN(235, "GSXCLK"), + PINCTRL_PIN(236, "ADR_COMPLETE"), + PINCTRL_PIN(237, "GPP_K_6"), + PINCTRL_PIN(238, "GPP_K_7"), + PINCTRL_PIN(239, "CORE_VID_0"), + PINCTRL_PIN(240, "CORE_VID_1"), + PINCTRL_PIN(241, "GPP_K_10"), + PINCTRL_PIN(242, "GPP_K_11"), + PINCTRL_PIN(243, "SYS_PWROK"), + PINCTRL_PIN(244, "SYS_RESETB"), + PINCTRL_PIN(245, "MLK_RSTB"), + /* GPP_F */ + PINCTRL_PIN(246, "SATAXPCIE_3"), + PINCTRL_PIN(247, "SATAXPCIE_4"), + PINCTRL_PIN(248, "SATAXPCIE_5"), + PINCTRL_PIN(249, "SATAXPCIE_6"), + PINCTRL_PIN(250, "SATAXPCIE_7"), + PINCTRL_PIN(251, "SATA_DEVSLP_3"), + PINCTRL_PIN(252, "SATA_DEVSLP_4"), + PINCTRL_PIN(253, "SATA_DEVSLP_5"), + PINCTRL_PIN(254, "SATA_DEVSLP_6"), + PINCTRL_PIN(255, "SATA_DEVSLP_7"), + PINCTRL_PIN(256, "SATA_SCLOCK"), + PINCTRL_PIN(257, "SATA_SLOAD"), + PINCTRL_PIN(258, "SATA_SDATAOUT1"), + PINCTRL_PIN(259, "SATA_SDATAOUT0"), + PINCTRL_PIN(260, "PS_ONB"), + PINCTRL_PIN(261, "M2_SKT2_CFG_0"), + PINCTRL_PIN(262, "M2_SKT2_CFG_1"), + PINCTRL_PIN(263, "M2_SKT2_CFG_2"), + PINCTRL_PIN(264, "M2_SKT2_CFG_3"), + PINCTRL_PIN(265, "L_VDDEN"), + PINCTRL_PIN(266, "L_BKLTEN"), + PINCTRL_PIN(267, "L_BKLTCTL"), + PINCTRL_PIN(268, "VNN_CTRL"), + PINCTRL_PIN(269, "GPP_F_23"), + /* GPP_D */ + PINCTRL_PIN(270, "SRCCLKREQB_0"), + PINCTRL_PIN(271, "SRCCLKREQB_1"), + PINCTRL_PIN(272, "SRCCLKREQB_2"), + PINCTRL_PIN(273, "SRCCLKREQB_3"), + PINCTRL_PIN(274, "SML1CLK"), + PINCTRL_PIN(275, "I2S2_SFRM"), + PINCTRL_PIN(276, "I2S2_TXD"), + PINCTRL_PIN(277, "I2S2_RXD"), + PINCTRL_PIN(278, "I2S2_SCLK"), + PINCTRL_PIN(279, "SML0CLK"), + PINCTRL_PIN(280, "SML0DATA"), + PINCTRL_PIN(281, "SRCCLKREQB_4"), + PINCTRL_PIN(282, "SRCCLKREQB_5"), + PINCTRL_PIN(283, "SRCCLKREQB_6"), + PINCTRL_PIN(284, "SRCCLKREQB_7"), + PINCTRL_PIN(285, "SML1DATA"), + PINCTRL_PIN(286, "GSPI3_CS0B"), + PINCTRL_PIN(287, "GSPI3_CLK"), + PINCTRL_PIN(288, "GSPI3_MISO"), + PINCTRL_PIN(289, "GSPI3_MOSI"), + PINCTRL_PIN(290, "UART3_RXD"), + PINCTRL_PIN(291, "UART3_TXD"), + PINCTRL_PIN(292, "UART3_RTSB"), + PINCTRL_PIN(293, "UART3_CTSB"), + PINCTRL_PIN(294, "GSPI3_CLK_LOOPBK"), + /* JTAG */ + PINCTRL_PIN(295, "JTAG_TDO"), + PINCTRL_PIN(296, "JTAGX"), + PINCTRL_PIN(297, "PRDYB"), + PINCTRL_PIN(298, "PREQB"), + PINCTRL_PIN(299, "JTAG_TDI"), + PINCTRL_PIN(300, "JTAG_TMS"), + PINCTRL_PIN(301, "JTAG_TCK"), + PINCTRL_PIN(302, "DBG_PMODE"), + PINCTRL_PIN(303, "CPU_TRSTB"), +}; + +static const struct intel_padgroup adls_community0_gpps[] = { + ADL_GPP(0, 0, 24, 0), /* GPP_I */ + ADL_GPP(1, 25, 47, 32), /* GPP_R */ + ADL_GPP(2, 48, 59, 64), /* GPP_J */ + ADL_GPP(3, 60, 86, 96), /* vGPIO */ + ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */ +}; + +static const struct intel_padgroup adls_community1_gpps[] = { + ADL_GPP(0, 95, 118, 160), /* GPP_B */ + ADL_GPP(1, 119, 126, 192), /* GPP_G */ + ADL_GPP(2, 127, 150, 224), /* GPP_H */ +}; + +static const struct intel_padgroup adls_community3_gpps[] = { + ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ + ADL_GPP(1, 160, 175, 256), /* GPP_A */ + ADL_GPP(2, 176, 199, 288), /* GPP_C */ +}; + +static const struct intel_padgroup adls_community4_gpps[] = { + ADL_GPP(0, 200, 207, 320), /* GPP_S */ + ADL_GPP(1, 208, 230, 352), /* GPP_E */ + ADL_GPP(2, 231, 245, 384), /* GPP_K */ + ADL_GPP(3, 246, 269, 416), /* GPP_F */ +}; + +static const struct intel_padgroup adls_community5_gpps[] = { + ADL_GPP(0, 270, 294, 448), /* GPP_D */ + ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ +}; + +static const struct intel_community adls_communities[] = { + ADL_COMMUNITY(0, 0, 94, adls_community0_gpps), + ADL_COMMUNITY(1, 95, 150, adls_community1_gpps), + ADL_COMMUNITY(2, 151, 199, adls_community3_gpps), + ADL_COMMUNITY(3, 200, 269, adls_community4_gpps), + ADL_COMMUNITY(4, 270, 303, adls_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data adls_soc_data = { + .pins = adls_pins, + .npins = ARRAY_SIZE(adls_pins), + .communities = adls_communities, + .ncommunities = ARRAY_SIZE(adls_communities), +}; + +static const struct acpi_device_id adl_pinctrl_acpi_match[] = { + { "INTC1056", (kernel_ulong_t)&adls_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops); + +static struct platform_driver adl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "alderlake-pinctrl", + .acpi_match_table = adl_pinctrl_acpi_match, + .pm = &adl_pinctrl_pm_ops, + }, +}; +module_platform_driver(adl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); From 0ddebf8580fa32b1827dcc5230a6db6260096f5e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 2 Nov 2020 14:39:11 +0200 Subject: [PATCH 07/80] pinctrl: lynxpoint: Unify initcall location in the code Like in the other Intel pin control drivers, attach initcalls to the corresponding functions. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 96589d01fe35..849979d5d646 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -967,13 +967,12 @@ static int __init lp_gpio_init(void) { return platform_driver_register(&lp_gpio_driver); } +subsys_initcall(lp_gpio_init); static void __exit lp_gpio_exit(void) { platform_driver_unregister(&lp_gpio_driver); } - -subsys_initcall(lp_gpio_init); module_exit(lp_gpio_exit); MODULE_AUTHOR("Mathias Nyman (Intel)"); From 9c65441ec823c7889fc3cd1f00208401cf7044d8 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 26 Oct 2020 11:30:25 -0700 Subject: [PATCH 08/80] pinctrl/meson: enable building as modules Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules. The default is still built-in, this only adds the option of building as modules. Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/Kconfig | 17 +++++++++-------- drivers/pinctrl/meson/pinctrl-meson-a1.c | 4 +++- drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 3 +++ drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 +++- drivers/pinctrl/meson/pinctrl-meson-g12a.c | 4 +++- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 4 +++- drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 +++- drivers/pinctrl/meson/pinctrl-meson.c | 8 ++++++++ drivers/pinctrl/meson/pinctrl-meson.h | 1 + drivers/pinctrl/meson/pinctrl-meson8-pmx.c | 2 ++ 10 files changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 3cb119105ddb..b2855e341a75 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig PINCTRL_MESON - bool "Amlogic SoC pinctrl drivers" + tristate "Amlogic SoC pinctrl drivers" depends on ARCH_MESON depends on OF + default y select PINMUX select PINCONF select GENERIC_PINCONF @@ -25,37 +26,37 @@ config PINCTRL_MESON8B default y config PINCTRL_MESON_GXBB - bool "Meson gxbb SoC pinctrl driver" + tristate "Meson gxbb SoC pinctrl driver" depends on ARM64 select PINCTRL_MESON8_PMX default y config PINCTRL_MESON_GXL - bool "Meson gxl SoC pinctrl driver" + tristate "Meson gxl SoC pinctrl driver" depends on ARM64 select PINCTRL_MESON8_PMX default y config PINCTRL_MESON8_PMX - bool + tristate config PINCTRL_MESON_AXG - bool "Meson axg Soc pinctrl driver" + tristate "Meson axg Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX default y config PINCTRL_MESON_AXG_PMX - bool + tristate config PINCTRL_MESON_G12A - bool "Meson g12a Soc pinctrl driver" + tristate "Meson g12a Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX default y config PINCTRL_MESON_A1 - bool "Meson a1 Soc pinctrl driver" + tristate "Meson a1 Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX default y diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c index 8abf750eac7e..79f5d753d7e1 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-a1.c +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c @@ -925,6 +925,7 @@ static const struct of_device_id meson_a1_pinctrl_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, meson_a1_pinctrl_dt_match); static struct platform_driver meson_a1_pinctrl_driver = { .probe = meson_pinctrl_probe, @@ -934,4 +935,5 @@ static struct platform_driver meson_a1_pinctrl_driver = { }, }; -builtin_platform_driver(meson_a1_pinctrl_driver); +module_platform_driver(meson_a1_pinctrl_driver); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c index e8931d9cf863..80c43683c789 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -116,3 +116,6 @@ const struct pinmux_ops meson_axg_pmx_ops = { .get_function_groups = meson_pmx_get_groups, .gpio_request_enable = meson_axg_pmx_request_gpio, }; +EXPORT_SYMBOL_GPL(meson_axg_pmx_ops); + +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index 072765db93d7..7bfecdfba177 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -1080,6 +1080,7 @@ static const struct of_device_id meson_axg_pinctrl_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, meson_axg_pinctrl_dt_match); static struct platform_driver meson_axg_pinctrl_driver = { .probe = meson_pinctrl_probe, @@ -1089,4 +1090,5 @@ static struct platform_driver meson_axg_pinctrl_driver = { }, }; -builtin_platform_driver(meson_axg_pinctrl_driver); +module_platform_driver(meson_axg_pinctrl_driver); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 41850e3c0091..cd9656b13836 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1410,6 +1410,7 @@ static const struct of_device_id meson_g12a_pinctrl_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, meson_g12a_pinctrl_dt_match); static struct platform_driver meson_g12a_pinctrl_driver = { .probe = meson_pinctrl_probe, @@ -1419,4 +1420,5 @@ static struct platform_driver meson_g12a_pinctrl_driver = { }, }; -builtin_platform_driver(meson_g12a_pinctrl_driver); +module_platform_driver(meson_g12a_pinctrl_driver); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index d130c635f74b..f51fc3939252 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -900,6 +900,7 @@ static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, meson_gxbb_pinctrl_dt_match); static struct platform_driver meson_gxbb_pinctrl_driver = { .probe = meson_pinctrl_probe, @@ -908,4 +909,5 @@ static struct platform_driver meson_gxbb_pinctrl_driver = { .of_match_table = meson_gxbb_pinctrl_dt_match, }, }; -builtin_platform_driver(meson_gxbb_pinctrl_driver); +module_platform_driver(meson_gxbb_pinctrl_driver); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 32552d795bb2..51408996255b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -861,6 +861,7 @@ static const struct of_device_id meson_gxl_pinctrl_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, meson_gxl_pinctrl_dt_match); static struct platform_driver meson_gxl_pinctrl_driver = { .probe = meson_pinctrl_probe, @@ -869,4 +870,5 @@ static struct platform_driver meson_gxl_pinctrl_driver = { .of_match_table = meson_gxl_pinctrl_dt_match, }, }; -builtin_platform_driver(meson_gxl_pinctrl_driver); +module_platform_driver(meson_gxl_pinctrl_driver); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 20683cd072bb..49851444a6e3 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -152,6 +152,7 @@ int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) return pc->data->num_funcs; } +EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count); const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, unsigned selector) @@ -160,6 +161,7 @@ const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, return pc->data->funcs[selector].name; } +EXPORT_SYMBOL_GPL(meson_pmx_get_func_name); int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, const char * const **groups, @@ -172,6 +174,7 @@ int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, return 0; } +EXPORT_SYMBOL_GPL(meson_pmx_get_groups); static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, unsigned int pin, @@ -723,6 +726,7 @@ int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc) return 0; } +EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra); int meson_a1_parse_dt_extra(struct meson_pinctrl *pc) { @@ -732,6 +736,7 @@ int meson_a1_parse_dt_extra(struct meson_pinctrl *pc) return 0; } +EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra); int meson_pinctrl_probe(struct platform_device *pdev) { @@ -766,3 +771,6 @@ int meson_pinctrl_probe(struct platform_device *pdev) return meson_gpiolib_register(pc); } +EXPORT_SYMBOL_GPL(meson_pinctrl_probe); + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index f8b0ff9d419a..ff5372e0a475 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -10,6 +10,7 @@ #include #include #include +#include struct meson_pinctrl; diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c index 66a908f9f13d..f767b6923f9f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c @@ -100,3 +100,5 @@ const struct pinmux_ops meson8_pmx_ops = { .get_function_groups = meson_pmx_get_groups, .gpio_request_enable = meson8_pmx_request_gpio, }; +EXPORT_SYMBOL_GPL(meson8_pmx_ops); +MODULE_LICENSE("GPL v2"); From b507cb92477ad85902783a183c5ce01d16296687 Mon Sep 17 00:00:00 2001 From: He Zhe Date: Wed, 28 Oct 2020 18:39:21 +0800 Subject: [PATCH 09/80] pinctrl: core: Add missing #ifdef CONFIG_GPIOLIB To fix the following build warnings when CONFIG_GPIOLIB=n. drivers/pinctrl/core.c:1607:20: warning: unused variable 'chip' [-Wunused-variable] 1608 | struct gpio_chip *chip; | ^~~~ drivers/pinctrl/core.c:1606:15: warning: unused variable 'gpio_num' [-Wunused-variable] 1607 | unsigned int gpio_num; | ^~~~~~~~ drivers/pinctrl/core.c:1605:29: warning: unused variable 'range' [-Wunused-variable] 1606 | struct pinctrl_gpio_range *range; | ^~~~~ Fixes: f1b206cf7c57 ("pinctrl: core: print gpio in pins debugfs file") Signed-off-by: He Zhe Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201028103921.22486-1-zhe.he@windriver.com Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 3663d87f51a0..9fc4433fece4 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1602,9 +1602,11 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *ops = pctldev->desc->pctlops; unsigned i, pin; +#ifdef CONFIG_GPIOLIB struct pinctrl_gpio_range *range; unsigned int gpio_num; struct gpio_chip *chip; +#endif seq_printf(s, "registered pins: %d\n", pctldev->desc->npins); From a4da45dda6475816f4c8b9e0d512261991ba31e5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 15:51:17 +0100 Subject: [PATCH 10/80] pinctrl: Remove hole in pinctrl_gpio_range On 64-bit platforms, pointer size and alignment are 64-bit, hence two 4-byte holes are present before the pins and gc members of the pinctrl_gpio_range structure. Get rid of these holes by moving the pins pointer. This reduces kernel size of an arm64 Rockchip kernel by ca. 512 bytes. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028145117.1731876-1-geert+renesas@glider.be Signed-off-by: Linus Walleij --- include/linux/pinctrl/pinctrl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 2aef59df93d7..70b45d28e7a9 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -51,8 +51,8 @@ struct pinctrl_pin_desc { * @id: an ID number for the chip in this range * @base: base offset of the GPIO range * @pin_base: base pin number of the GPIO range if pins == NULL - * @pins: enumeration of pins in GPIO range or NULL * @npins: number of pins in the GPIO range, including the base number + * @pins: enumeration of pins in GPIO range or NULL * @gc: an optional pointer to a gpio_chip */ struct pinctrl_gpio_range { @@ -61,8 +61,8 @@ struct pinctrl_gpio_range { unsigned int id; unsigned int base; unsigned int pin_base; - unsigned const *pins; unsigned int npins; + unsigned const *pins; struct gpio_chip *gc; }; From 0e74abf3a0a3a711145f11f3a782432a2df5f744 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Wed, 7 Oct 2020 19:06:11 +0300 Subject: [PATCH 11/80] pinctrl: qcom: add pinctrl driver for msm8953 Add inititial pinctrl driver for MSM8953 platform. Compatible SoCs are: MSM8953, APQ8053, SDM(SDA)450, SDM(SDA)632. Based off CAF implementation. Signed-off-by: Prasad Sodagudi Signed-off-by: Vladimir Lypak Acked-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201007160611.942754-1-junak.pub@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-msm8953.c | 1844 ++++++++++++++++++++++++ 3 files changed, 1855 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8953.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 5fe7b8aaf69d..98d075447a32 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -111,6 +111,16 @@ config PINCTRL_MSM8916 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. +config PINCTRL_MSM8953 + tristate "Qualcomm 8953 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8953 platform. + The Qualcomm APQ8053, SDM450, SDM632 platforms are also + supported by this driver. + config PINCTRL_MSM8976 tristate "Qualcomm 8976 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 9e3d9c91a444..5072e66fd3ab 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c new file mode 100644 index 000000000000..e0c939ff3d54 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -0,0 +1,1844 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc msm8953_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "SDC1_CLK"), + PINCTRL_PIN(143, "SDC1_CMD"), + PINCTRL_PIN(144, "SDC1_DATA"), + PINCTRL_PIN(145, "SDC1_RCLK"), + PINCTRL_PIN(146, "SDC2_CLK"), + PINCTRL_PIN(147, "SDC2_CMD"), + PINCTRL_PIN(148, "SDC2_DATA"), + PINCTRL_PIN(149, "QDSD_CLK"), + PINCTRL_PIN(150, "QDSD_CMD"), + PINCTRL_PIN(151, "QDSD_DATA0"), + PINCTRL_PIN(152, "QDSD_DATA1"), + PINCTRL_PIN(153, "QDSD_DATA2"), + PINCTRL_PIN(154, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); + +static const unsigned int qdsd_clk_pins[] = { 142 }; +static const unsigned int qdsd_cmd_pins[] = { 143 }; +static const unsigned int qdsd_data0_pins[] = { 144 }; +static const unsigned int qdsd_data1_pins[] = { 145 }; +static const unsigned int qdsd_data2_pins[] = { 146 }; +static const unsigned int qdsd_data3_pins[] = { 147 }; +static const unsigned int sdc1_clk_pins[] = { 148 }; +static const unsigned int sdc1_cmd_pins[] = { 149 }; +static const unsigned int sdc1_data_pins[] = { 150 }; +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc2_clk_pins[] = { 152 }; +static const unsigned int sdc2_cmd_pins[] = { 153 }; +static const unsigned int sdc2_data_pins[] = { 154 }; + +enum msm8953_functions { + msm_mux_accel_int, + msm_mux_adsp_ext, + msm_mux_alsp_int, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_atest_tsens, + msm_mux_atest_wlan0, + msm_mux_atest_wlan1, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp1_spi, + msm_mux_blsp3_spi, + msm_mux_blsp6_spi, + msm_mux_blsp7_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_uart2, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_cam0_ldo, + msm_mux_cam1_ldo, + msm_mux_cam1_rst, + msm_mux_cam1_standby, + msm_mux_cam2_rst, + msm_mux_cam2_standby, + msm_mux_cam3_rst, + msm_mux_cam3_standby, + msm_mux_cam_irq, + msm_mux_cam_mclk, + msm_mux_cap_int, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cdc_pdm0, + msm_mux_codec_int1, + msm_mux_codec_int2, + msm_mux_codec_reset, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dac_calib0, + msm_mux_dac_calib1, + msm_mux_dac_calib2, + msm_mux_dac_calib3, + msm_mux_dac_calib4, + msm_mux_dac_calib5, + msm_mux_dac_calib6, + msm_mux_dac_calib7, + msm_mux_dac_calib8, + msm_mux_dac_calib9, + msm_mux_dac_calib10, + msm_mux_dac_calib11, + msm_mux_dac_calib12, + msm_mux_dac_calib13, + msm_mux_dac_calib14, + msm_mux_dac_calib15, + msm_mux_dac_calib16, + msm_mux_dac_calib17, + msm_mux_dac_calib18, + msm_mux_dac_calib19, + msm_mux_dac_calib20, + msm_mux_dac_calib21, + msm_mux_dac_calib22, + msm_mux_dac_calib23, + msm_mux_dac_calib24, + msm_mux_dac_calib25, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_ebi_cdc, + msm_mux_ebi_ch0, + msm_mux_ext_lpass, + msm_mux_flash_strobe, + msm_mux_fp_int, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_gsm0_tx, + msm_mux_gsm1_tx, + msm_mux_gyro_int, + msm_mux_hall_int, + msm_mux_hdmi_int, + msm_mux_key_focus, + msm_mux_key_home, + msm_mux_key_snapshot, + msm_mux_key_volp, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_m_voc, + msm_mux_mag_int, + msm_mux_mdp_vsync, + msm_mux_mipi_dsi0, + msm_mux_modem_tsync, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_nav_pps_in_a, + msm_mux_nav_pps_in_b, + msm_mux_nav_tsync, + msm_mux_nfc_disable, + msm_mux_nfc_dwl, + msm_mux_nfc_irq, + msm_mux_ois_sync, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pressure_int, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_down, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_sd_write, + msm_mux_sdcard_det, + msm_mux_sec_mi2s, + msm_mux_sec_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_b, + msm_mux_smb_int, + msm_mux_ss_switch, + msm_mux_ssbi_wtr1, + msm_mux_ts_resout, + msm_mux_ts_sample, + msm_mux_ts_xvdd, + msm_mux_tsens_max, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_us_emitter, + msm_mux_us_euro, + msm_mux_wcss_bt, + msm_mux_wcss_fm, + msm_mux_wcss_wlan, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan2, + msm_mux_wsa_en, + msm_mux_wsa_io, + msm_mux_wsa_irq, + msm_mux__, +}; + +static const char * const accel_int_groups[] = { + "gpio42", +}; + +static const char * const adsp_ext_groups[] = { + "gpio1", +}; + +static const char * const alsp_int_groups[] = { + "gpio43", +}; + +static const char * const atest_bbrx0_groups[] = { + "gpio17", +}; + +static const char * const atest_bbrx1_groups[] = { + "gpio16", +}; + +static const char * const atest_char0_groups[] = { + "gpio68", +}; + +static const char * const atest_char1_groups[] = { + "gpio67", +}; + +static const char * const atest_char2_groups[] = { + "gpio75", +}; + +static const char * const atest_char3_groups[] = { + "gpio63", +}; + +static const char * const atest_char_groups[] = { + "gpio120", +}; + +static const char * const atest_gpsadc_dtest0_native_groups[] = { + "gpio7", +}; + +static const char * const atest_gpsadc_dtest1_native_groups[] = { + "gpio18", +}; + +static const char * const atest_tsens_groups[] = { + "gpio120", +}; + +static const char * const atest_wlan0_groups[] = { + "gpio22", +}; + +static const char * const atest_wlan1_groups[] = { + "gpio23", +}; + +static const char * const bimc_dte0_groups[] = { + "gpio63", "gpio65", +}; + +static const char * const bimc_dte1_groups[] = { + "gpio121", "gpio122", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio41", "gpio50", +}; + +static const char * const blsp6_spi_groups[] = { + "gpio47", "gpio48", +}; + +static const char * const blsp7_spi_groups[] = { + "gpio89", "gpio90", +}; + +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; + +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; + +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; + +static const char * const blsp_i2c5_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; + +static const char * const blsp_i2c7_groups[] = { + "gpio135", "gpio136", +}; + +static const char * const blsp_i2c8_groups[] = { + "gpio98", "gpio99", +}; + +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const blsp_spi7_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const blsp_spi8_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_uart4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const cam0_ldo_groups[] = { + "gpio50", +}; + +static const char * const cam1_ldo_groups[] = { + "gpio134", +}; + +static const char * const cam1_rst_groups[] = { + "gpio40", +}; + +static const char * const cam1_standby_groups[] = { + "gpio39", +}; + +static const char * const cam2_rst_groups[] = { + "gpio129", +}; + +static const char * const cam2_standby_groups[] = { + "gpio130", +}; + +static const char * const cam3_rst_groups[] = { + "gpio131", +}; + +static const char * const cam3_standby_groups[] = { + "gpio132", +}; + +static const char * const cam_irq_groups[] = { + "gpio35", +}; + +static const char * const cam_mclk_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio128", +}; + +static const char * const cap_int_groups[] = { + "gpio13", +}; + +static const char * const cci_async_groups[] = { + "gpio38", +}; + +static const char * const cci_i2c_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const cci_timer0_groups[] = { + "gpio33", +}; + +static const char * const cci_timer1_groups[] = { + "gpio34", +}; + +static const char * const cci_timer2_groups[] = { + "gpio35", +}; + +static const char * const cci_timer3_groups[] = { + "gpio36", +}; + +static const char * const cci_timer4_groups[] = { + "gpio41", +}; + +static const char * const cdc_pdm0_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", + "gpio74", +}; + +static const char * const codec_int1_groups[] = { + "gpio73", +}; + +static const char * const codec_int2_groups[] = { + "gpio74", +}; + +static const char * const codec_reset_groups[] = { + "gpio67", +}; + +static const char * const cri_trng0_groups[] = { + "gpio85", +}; + +static const char * const cri_trng1_groups[] = { + "gpio86", +}; + +static const char * const cri_trng_groups[] = { + "gpio87", +}; + +static const char * const dac_calib0_groups[] = { + "gpio4", +}; + +static const char * const dac_calib1_groups[] = { + "gpio12", +}; + +static const char * const dac_calib2_groups[] = { + "gpio13", +}; + +static const char * const dac_calib3_groups[] = { + "gpio28", +}; + +static const char * const dac_calib4_groups[] = { + "gpio29", +}; + +static const char * const dac_calib5_groups[] = { + "gpio39", +}; + +static const char * const dac_calib6_groups[] = { + "gpio40", +}; + +static const char * const dac_calib7_groups[] = { + "gpio41", +}; + +static const char * const dac_calib8_groups[] = { + "gpio42", +}; + +static const char * const dac_calib9_groups[] = { + "gpio43", +}; + +static const char * const dac_calib10_groups[] = { + "gpio44", +}; + +static const char * const dac_calib11_groups[] = { + "gpio45", +}; + +static const char * const dac_calib12_groups[] = { + "gpio46", +}; + +static const char * const dac_calib13_groups[] = { + "gpio47", +}; + +static const char * const dac_calib14_groups[] = { + "gpio48", +}; + +static const char * const dac_calib15_groups[] = { + "gpio20", +}; + +static const char * const dac_calib16_groups[] = { + "gpio21", +}; + +static const char * const dac_calib17_groups[] = { + "gpio67", +}; + +static const char * const dac_calib18_groups[] = { + "gpio115", +}; + +static const char * const dac_calib19_groups[] = { + "gpio30", +}; + +static const char * const dac_calib20_groups[] = { + "gpio128", +}; + +static const char * const dac_calib21_groups[] = { + "gpio129", +}; + +static const char * const dac_calib22_groups[] = { + "gpio130", +}; + +static const char * const dac_calib23_groups[] = { + "gpio131", +}; + +static const char * const dac_calib24_groups[] = { + "gpio132", +}; + +static const char * const dac_calib25_groups[] = { + "gpio133", +}; + +static const char * const dbg_out_groups[] = { + "gpio63", +}; + +static const char * const ddr_bist_groups[] = { + "gpio129", "gpio130", "gpio131", "gpio132", +}; + +static const char * const dmic0_clk_groups[] = { + "gpio89", +}; + +static const char * const dmic0_data_groups[] = { + "gpio90", +}; + +static const char * const ebi_cdc_groups[] = { + "gpio67", "gpio69", "gpio118", "gpio119", "gpio120", "gpio123", +}; + +static const char * const ebi_ch0_groups[] = { + "gpio75", +}; + +static const char * const ext_lpass_groups[] = { + "gpio81", +}; + +static const char * const flash_strobe_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const fp_int_groups[] = { + "gpio48", +}; + +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio42", +}; + +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio6", "gpio41", +}; + +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio43", +}; + +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio10", +}; + +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio44", +}; + +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio11", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio98", "gpio99", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio87", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", +}; + +static const char * const gsm0_tx_groups[] = { + "gpio117", +}; + +static const char * const gsm1_tx_groups[] = { + "gpio115", +}; + +static const char * const gyro_int_groups[] = { + "gpio45", +}; + +static const char * const hall_int_groups[] = { + "gpio12", +}; + +static const char * const hdmi_int_groups[] = { + "gpio90", +}; + +static const char * const key_focus_groups[] = { + "gpio87", +}; + +static const char * const key_home_groups[] = { + "gpio88", +}; + +static const char * const key_snapshot_groups[] = { + "gpio86", +}; + +static const char * const key_volp_groups[] = { + "gpio85", +}; + +static const char * const ldo_en_groups[] = { + "gpio5", +}; + +static const char * const ldo_update_groups[] = { + "gpio4", +}; + +static const char * const lpass_slimbus0_groups[] = { + "gpio71", +}; + +static const char * const lpass_slimbus1_groups[] = { + "gpio72", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio70", +}; + +static const char * const m_voc_groups[] = { + "gpio17", "gpio21", +}; + +static const char * const mag_int_groups[] = { + "gpio44", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio24", "gpio25", +}; + +static const char * const mipi_dsi0_groups[] = { + "gpio61", +}; + +static const char * const modem_tsync_groups[] = { + "gpio113", +}; + +static const char * const mss_lte_groups[] = { + "gpio82", "gpio83", +}; + +static const char * const nav_pps_groups[] = { + "gpio113", +}; + +static const char * const nav_pps_in_a_groups[] = { + "gpio111", +}; + +static const char * const nav_pps_in_b_groups[] = { + "gpio113", +}; + +static const char * const nav_tsync_groups[] = { + "gpio113", +}; + +static const char * const nfc_disable_groups[] = { + "gpio16", +}; + +static const char * const nfc_dwl_groups[] = { + "gpio62", +}; + +static const char * const nfc_irq_groups[] = { + "gpio17", +}; + +static const char * const ois_sync_groups[] = { + "gpio36", +}; + +static const char * const pa_indicator_groups[] = { + "gpio112", +}; + +static const char * const pbs0_groups[] = { + "gpio85", +}; + +static const char * const pbs1_groups[] = { + "gpio86", +}; + +static const char * const pbs2_groups[] = { + "gpio87", +}; + +static const char * const pressure_int_groups[] = { + "gpio46", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio66", "gpio88", "gpio91", "gpio93", "gpio94", "gpio95", +}; + +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio25", +}; + +static const char * const pri_mi2s_mclk_b_groups[] = { + "gpio69", +}; + +static const char * const pri_mi2s_ws_groups[] = { + "gpio92", +}; + +static const char * const prng_rosc_groups[] = { + "gpio2", +}; + +static const char * const pwr_crypto_enabled_a_groups[] = { + "gpio36", +}; + +static const char * const pwr_crypto_enabled_b_groups[] = { + "gpio13", +}; + +static const char * const pwr_down_groups[] = { + "gpio89", +}; + +static const char * const pwr_modem_enabled_a_groups[] = { + "gpio29", +}; + +static const char * const pwr_modem_enabled_b_groups[] = { + "gpio9", +}; + +static const char * const pwr_nav_enabled_a_groups[] = { + "gpio35", +}; + +static const char * const pwr_nav_enabled_b_groups[] = { + "gpio12", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio17", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio91", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio21", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio48", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio41", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio3", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio2", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio25", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio16", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio22", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio18", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio20", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio19", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio38", "gpio39", + "gpio40", "gpio50", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio8", "gpio9", "gpio12", "gpio13", "gpio23", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio66", "gpio86", "gpio87", + "gpio88", "gpio92", +}; + +static const char * const sd_write_groups[] = { + "gpio50", +}; + +static const char * const sdcard_det_groups[] = { + "gpio133", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const sec_mi2s_mclk_a_groups[] = { + "gpio25", +}; + +static const char * const sec_mi2s_mclk_b_groups[] = { + "gpio66", +}; + +static const char * const smb_int_groups[] = { + "gpio1", +}; + +static const char * const ss_switch_groups[] = { + "gpio139", +}; + +static const char * const ssbi_wtr1_groups[] = { + "gpio114", "gpio123", +}; + +static const char * const ts_resout_groups[] = { + "gpio64", +}; + +static const char * const ts_sample_groups[] = { + "gpio65", +}; + +static const char * const ts_xvdd_groups[] = { + "gpio60", +}; + +static const char * const tsens_max_groups[] = { + "gpio139", +}; + +static const char * const uim1_clk_groups[] = { + "gpio52", +}; + +static const char * const uim1_data_groups[] = { + "gpio51", +}; + +static const char * const uim1_present_groups[] = { + "gpio54", +}; + +static const char * const uim1_reset_groups[] = { + "gpio53", +}; + +static const char * const uim2_clk_groups[] = { + "gpio56", +}; + +static const char * const uim2_data_groups[] = { + "gpio55", +}; + +static const char * const uim2_present_groups[] = { + "gpio58", +}; + +static const char * const uim2_reset_groups[] = { + "gpio57", +}; + +static const char * const uim_batt_groups[] = { + "gpio49", +}; + +static const char * const us_emitter_groups[] = { + "gpio68", +}; + +static const char * const us_euro_groups[] = { + "gpio63", +}; + +static const char * const wcss_bt_groups[] = { + "gpio75", "gpio83", "gpio84", +}; + +static const char * const wcss_fm_groups[] = { + "gpio81", "gpio82", +}; + +static const char * const wcss_wlan0_groups[] = { + "gpio78", +}; + +static const char * const wcss_wlan1_groups[] = { + "gpio77", +}; + +static const char * const wcss_wlan2_groups[] = { + "gpio76", +}; + +static const char * const wcss_wlan_groups[] = { + "gpio79", "gpio80", +}; + +static const char * const wsa_en_groups[] = { + "gpio96", +}; + +static const char * const wsa_io_groups[] = { + "gpio94", "gpio95", +}; + +static const char * const wsa_irq_groups[] = { + "gpio97", +}; + +static const struct msm_function msm8953_functions[] = { + FUNCTION(accel_int), + FUNCTION(adsp_ext), + FUNCTION(alsp_int), + FUNCTION(atest_bbrx0), + FUNCTION(atest_bbrx1), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_gpsadc_dtest0_native), + FUNCTION(atest_gpsadc_dtest1_native), + FUNCTION(atest_tsens), + FUNCTION(atest_wlan0), + FUNCTION(atest_wlan1), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp1_spi), + FUNCTION(blsp3_spi), + FUNCTION(blsp6_spi), + FUNCTION(blsp7_spi), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), + FUNCTION(blsp_spi8), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(cam0_ldo), + FUNCTION(cam1_ldo), + FUNCTION(cam1_rst), + FUNCTION(cam1_standby), + FUNCTION(cam2_rst), + FUNCTION(cam2_standby), + FUNCTION(cam3_rst), + FUNCTION(cam3_standby), + FUNCTION(cam_irq), + FUNCTION(cam_mclk), + FUNCTION(cap_int), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cdc_pdm0), + FUNCTION(codec_int1), + FUNCTION(codec_int2), + FUNCTION(codec_reset), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dac_calib0), + FUNCTION(dac_calib1), + FUNCTION(dac_calib10), + FUNCTION(dac_calib11), + FUNCTION(dac_calib12), + FUNCTION(dac_calib13), + FUNCTION(dac_calib14), + FUNCTION(dac_calib15), + FUNCTION(dac_calib16), + FUNCTION(dac_calib17), + FUNCTION(dac_calib18), + FUNCTION(dac_calib19), + FUNCTION(dac_calib2), + FUNCTION(dac_calib20), + FUNCTION(dac_calib21), + FUNCTION(dac_calib22), + FUNCTION(dac_calib23), + FUNCTION(dac_calib24), + FUNCTION(dac_calib25), + FUNCTION(dac_calib3), + FUNCTION(dac_calib4), + FUNCTION(dac_calib5), + FUNCTION(dac_calib6), + FUNCTION(dac_calib7), + FUNCTION(dac_calib8), + FUNCTION(dac_calib9), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(dmic0_clk), + FUNCTION(dmic0_data), + FUNCTION(ebi_cdc), + FUNCTION(ebi_ch0), + FUNCTION(ext_lpass), + FUNCTION(flash_strobe), + FUNCTION(fp_int), + FUNCTION(gcc_gp1_clk_a), + FUNCTION(gcc_gp1_clk_b), + FUNCTION(gcc_gp2_clk_a), + FUNCTION(gcc_gp2_clk_b), + FUNCTION(gcc_gp3_clk_a), + FUNCTION(gcc_gp3_clk_b), + FUNCTION(gcc_plltest), + FUNCTION(gcc_tlmm), + FUNCTION(gpio), + FUNCTION(gsm0_tx), + FUNCTION(gsm1_tx), + FUNCTION(gyro_int), + FUNCTION(hall_int), + FUNCTION(hdmi_int), + FUNCTION(key_focus), + FUNCTION(key_home), + FUNCTION(key_snapshot), + FUNCTION(key_volp), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(lpass_slimbus), + FUNCTION(lpass_slimbus0), + FUNCTION(lpass_slimbus1), + FUNCTION(m_voc), + FUNCTION(mag_int), + FUNCTION(mdp_vsync), + FUNCTION(mipi_dsi0), + FUNCTION(modem_tsync), + FUNCTION(mss_lte), + FUNCTION(nav_pps), + FUNCTION(nav_pps_in_a), + FUNCTION(nav_pps_in_b), + FUNCTION(nav_tsync), + FUNCTION(nfc_disable), + FUNCTION(nfc_dwl), + FUNCTION(nfc_irq), + FUNCTION(ois_sync), + FUNCTION(pa_indicator), + FUNCTION(pbs0), + FUNCTION(pbs1), + FUNCTION(pbs2), + FUNCTION(pressure_int), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_mclk_a), + FUNCTION(pri_mi2s_mclk_b), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(pwr_crypto_enabled_a), + FUNCTION(pwr_crypto_enabled_b), + FUNCTION(pwr_down), + FUNCTION(pwr_modem_enabled_a), + FUNCTION(pwr_modem_enabled_b), + FUNCTION(pwr_nav_enabled_a), + FUNCTION(pwr_nav_enabled_b), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(sd_write), + FUNCTION(sdcard_det), + FUNCTION(sec_mi2s), + FUNCTION(sec_mi2s_mclk_a), + FUNCTION(sec_mi2s_mclk_b), + FUNCTION(smb_int), + FUNCTION(ss_switch), + FUNCTION(ssbi_wtr1), + FUNCTION(ts_resout), + FUNCTION(ts_sample), + FUNCTION(ts_xvdd), + FUNCTION(tsens_max), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(uim_batt), + FUNCTION(us_emitter), + FUNCTION(us_euro), + FUNCTION(wcss_bt), + FUNCTION(wcss_fm), + FUNCTION(wcss_wlan), + FUNCTION(wcss_wlan0), + FUNCTION(wcss_wlan1), + FUNCTION(wcss_wlan2), + FUNCTION(wsa_en), + FUNCTION(wsa_io), + FUNCTION(wsa_irq), +}; + +static const struct msm_pingroup msm8953_groups[] = { + PINGROUP(0, blsp_spi1, _, _, _, _, _, _, _, _), + PINGROUP(1, blsp_spi1, adsp_ext, _, _, _, _, _, _, _), + PINGROUP(2, blsp_spi1, blsp_i2c1, prng_rosc, _, _, _, qdss_cti_trig_out_b0, _, _), + PINGROUP(3, blsp_spi1, blsp_i2c1, _, _, _, qdss_cti_trig_out_a1, _, _, _), + PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, _, dac_calib0, _, _, _, _), + PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, _, _, _, _, _, _), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, _, _, _, _, _), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, _, atest_gpsadc_dtest0_native, _, _, _, _), + PINGROUP(8, blsp_spi3, _, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(9, blsp_spi3, pwr_modem_enabled_b, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(10, blsp_spi3, blsp_i2c3, gcc_gp2_clk_b, _, _, _, _, _, _), + PINGROUP(11, blsp_spi3, blsp_i2c3, gcc_gp3_clk_b, _, _, _, _, _, _), + PINGROUP(12, blsp_spi4, blsp_uart4, pwr_nav_enabled_b, _, _, + qdss_tracedata_b, _, dac_calib1, _), + PINGROUP(13, blsp_spi4, blsp_uart4, pwr_crypto_enabled_b, _, _, _, + qdss_tracedata_b, _, dac_calib2), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(16, blsp_spi5, blsp_uart5, _, _, qdss_traceclk_a, _, atest_bbrx1, _, _), + PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, _, atest_bbrx0, _, _, _), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, + qdss_tracectl_a, _, atest_gpsadc_dtest1_native, _, _, _), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(20, blsp_spi6, blsp_uart6, _, _, _, qdss_tracectl_b, _, dac_calib15, _), + PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, _, _, _, qdss_cti_trig_in_b0, _, dac_calib16), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, _, atest_wlan0, _, _, _), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, _, atest_wlan1, _, _, _), + PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _), + PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, + qdss_cti_trig_out_b1, _, _, _, _, _), + PINGROUP(26, cam_mclk, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(27, cam_mclk, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(28, cam_mclk, _, _, _, qdss_tracedata_a, _, dac_calib3, _, _), + PINGROUP(29, cci_i2c, pwr_modem_enabled_a, _, _, _, qdss_tracedata_a, _, dac_calib4, _), + PINGROUP(30, cci_i2c, _, _, _, qdss_tracedata_a, _, dac_calib19, _, _), + PINGROUP(31, cci_i2c, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(32, cci_i2c, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(33, cci_timer0, _, _, _, _, qdss_tracedata_a, _, _, _), + PINGROUP(34, cci_timer1, _, _, _, _, qdss_tracedata_a, _, _, _), + PINGROUP(35, cci_timer2, blsp1_spi, pwr_nav_enabled_a, _, _, _, qdss_tracedata_a, _, _), + PINGROUP(36, cci_timer3, blsp1_spi, _, pwr_crypto_enabled_a, _, _, _, qdss_tracedata_a, _), + PINGROUP(37, _, _, _, _, _, _, _, _, _), + PINGROUP(38, cci_async, _, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(39, _, _, _, qdss_tracedata_a, _, dac_calib5, _, _, _), + PINGROUP(40, _, _, qdss_tracedata_a, _, dac_calib6, _, _, _, _), + PINGROUP(41, cci_timer4, blsp3_spi, gcc_gp1_clk_b, _, _, + qdss_cti_trig_out_a0, _, dac_calib7, _), + PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, _, dac_calib8, _, _, _, _, _), + PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, _, dac_calib9, _, _, _, _, _), + PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, _, dac_calib10, _, _, _, _, _), + PINGROUP(45, _, qdss_tracedata_b, _, dac_calib11, _, _, _, _, _), + PINGROUP(46, qdss_tracedata_b, _, dac_calib12, _, _, _, _, _, _), + PINGROUP(47, blsp6_spi, qdss_tracedata_b, _, dac_calib13, _, _, _, _, _), + PINGROUP(48, blsp6_spi, _, qdss_cti_trig_in_b1, _, dac_calib14, _, _, _, _), + PINGROUP(49, uim_batt, _, _, _, _, _, _, _, _), + PINGROUP(50, blsp3_spi, sd_write, _, _, _, qdss_tracedata_a, _, _, _), + PINGROUP(51, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(52, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(53, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(54, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(55, uim2_data, _, _, _, _, _, _, _, _), + PINGROUP(56, uim2_clk, _, _, _, _, _, _, _, _), + PINGROUP(57, uim2_reset, _, _, _, _, _, _, _, _), + PINGROUP(58, uim2_present, _, _, _, _, _, _, _, _), + PINGROUP(59, _, _, _, _, _, _, _, _, _), + PINGROUP(60, _, _, _, _, _, _, _, _, _), + PINGROUP(61, _, _, _, _, _, _, _, _, _), + PINGROUP(62, _, _, _, _, _, _, _, _, _), + PINGROUP(63, atest_char3, dbg_out, bimc_dte0, _, _, _, _, _, _), + PINGROUP(64, _, _, _, _, _, _, _, _, _), + PINGROUP(65, bimc_dte0, _, _, _, _, _, _, _, _), + PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(67, cdc_pdm0, atest_char1, ebi_cdc, _, dac_calib17, _, _, _, _), + PINGROUP(68, cdc_pdm0, atest_char0, _, _, _, _, _, _, _), + PINGROUP(69, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, _, _, _, _, _, _), + PINGROUP(70, lpass_slimbus, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(71, lpass_slimbus0, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(72, lpass_slimbus1, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(73, cdc_pdm0, _, _, _, _, _, _, _, _), + PINGROUP(74, cdc_pdm0, _, _, _, _, _, _, _, _), + PINGROUP(75, wcss_bt, atest_char2, _, ebi_ch0, _, _, _, _, _), + PINGROUP(76, wcss_wlan2, _, _, _, _, _, _, _, _), + PINGROUP(77, wcss_wlan1, _, _, _, _, _, _, _, _), + PINGROUP(78, wcss_wlan0, _, _, _, _, _, _, _, _), + PINGROUP(79, wcss_wlan, _, _, _, _, _, _, _, _), + PINGROUP(80, wcss_wlan, _, _, _, _, _, _, _, _), + PINGROUP(81, wcss_fm, ext_lpass, _, _, _, _, _, _, _), + PINGROUP(82, wcss_fm, mss_lte, _, _, _, _, _, _, _), + PINGROUP(83, wcss_bt, mss_lte, _, _, _, _, _, _, _), + PINGROUP(84, wcss_bt, _, _, _, _, _, _, _, _), + PINGROUP(85, pbs0, cri_trng0, _, _, _, _, _, _, _), + PINGROUP(86, pbs1, cri_trng1, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(87, pbs2, cri_trng, qdss_tracedata_b, gcc_tlmm, _, _, _, _, _), + PINGROUP(88, pri_mi2s, _, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(89, dmic0_clk, blsp7_spi, _, _, _, _, _, _, _), + PINGROUP(90, dmic0_data, blsp7_spi, _, _, _, _, _, _, _), + PINGROUP(91, pri_mi2s, _, _, _, qdss_cti_trig_in_a1, _, _, _, _), + PINGROUP(92, pri_mi2s_ws, _, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(93, pri_mi2s, _, _, _, _, _, _, _, _), + PINGROUP(94, wsa_io, pri_mi2s, _, _, _, _, _, _, _), + PINGROUP(95, wsa_io, pri_mi2s, _, _, _, _, _, _, _), + PINGROUP(96, blsp_spi8, _, _, _, _, _, _, _, _), + PINGROUP(97, blsp_spi8, _, _, _, _, _, _, _, _), + PINGROUP(98, blsp_i2c8, blsp_spi8, gcc_plltest, _, _, _, _, _, _), + PINGROUP(99, blsp_i2c8, blsp_spi8, gcc_plltest, _, _, _, _, _, _), + PINGROUP(100, _, _, _, _, _, _, _, _, _), + PINGROUP(101, _, _, _, _, _, _, _, _, _), + PINGROUP(102, _, _, _, _, _, _, _, _, _), + PINGROUP(103, _, _, _, _, _, _, _, _, _), + PINGROUP(104, _, _, _, _, _, _, _, _, _), + PINGROUP(105, _, _, _, _, _, _, _, _, _), + PINGROUP(106, _, _, _, _, _, _, _, _, _), + PINGROUP(107, _, _, _, _, _, _, _, _, _), + PINGROUP(108, _, _, _, _, _, _, _, _, _), + PINGROUP(109, _, _, _, _, _, _, _, _, _), + PINGROUP(110, _, _, _, _, _, _, _, _, _), + PINGROUP(111, _, _, nav_pps_in_a, _, _, _, _, _, _), + PINGROUP(112, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(113, _, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, _, _, _, _), + PINGROUP(114, _, ssbi_wtr1, _, _, _, _, _, _, _), + PINGROUP(115, _, gsm1_tx, _, dac_calib18, _, _, _, _, _), + PINGROUP(116, _, _, _, _, _, _, _, _, _), + PINGROUP(117, gsm0_tx, _, _, _, _, _, _, _, _), + PINGROUP(118, _, ebi_cdc, _, _, _, _, _, _, _), + PINGROUP(119, _, ebi_cdc, _, _, _, _, _, _, _), + PINGROUP(120, _, atest_char, ebi_cdc, _, atest_tsens, _, _, _, _), + PINGROUP(121, _, _, _, bimc_dte1, _, _, _, _, _), + PINGROUP(122, _, _, _, bimc_dte1, _, _, _, _, _), + PINGROUP(123, _, ssbi_wtr1, ebi_cdc, _, _, _, _, _, _), + PINGROUP(124, _, _, _, _, _, _, _, _, _), + PINGROUP(125, _, _, _, _, _, _, _, _, _), + PINGROUP(126, _, _, _, _, _, _, _, _, _), + PINGROUP(127, _, _, _, _, _, _, _, _, _), + PINGROUP(128, cam_mclk, _, dac_calib20, _, _, _, _, _, _), + PINGROUP(129, ddr_bist, _, dac_calib21, _, _, _, _, _, _), + PINGROUP(130, ddr_bist, _, dac_calib22, _, _, _, _, _, _), + PINGROUP(131, ddr_bist, _, dac_calib23, _, _, _, _, _, _), + PINGROUP(132, ddr_bist, _, dac_calib24, _, _, _, _, _, _), + PINGROUP(133, _, dac_calib25, _, _, _, _, _, _, _), + PINGROUP(134, _, _, _, _, _, _, _, _, _), + PINGROUP(135, sec_mi2s, blsp_spi7, blsp_i2c7, _, _, _, _, _, _), + PINGROUP(136, sec_mi2s, blsp_spi7, blsp_i2c7, _, _, _, _, _, _), + PINGROUP(137, sec_mi2s, blsp_spi7, _, _, _, _, _, _, _), + PINGROUP(138, sec_mi2s, blsp_spi7, _, _, _, _, _, _, _), + PINGROUP(139, tsens_max, _, _, _, _, _, _, _, _), + PINGROUP(140, _, _, _, _, _, _, _, _, _), + PINGROUP(141, _, _, _, _, _, _, _, _, _), + SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25), + SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data msm8953_pinctrl = { + .pins = msm8953_pins, + .npins = ARRAY_SIZE(msm8953_pins), + .functions = msm8953_functions, + .nfunctions = ARRAY_SIZE(msm8953_functions), + .groups = msm8953_groups, + .ngroups = ARRAY_SIZE(msm8953_groups), + .ngpios = 142, +}; + +static int msm8953_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8953_pinctrl); +} + +static const struct of_device_id msm8953_pinctrl_of_match[] = { + { .compatible = "qcom,msm8953-pinctrl", }, + { }, +}; + +static struct platform_driver msm8953_pinctrl_driver = { + .driver = { + .name = "msm8953-pinctrl", + .of_match_table = msm8953_pinctrl_of_match, + }, + .probe = msm8953_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8953_pinctrl_init(void) +{ + return platform_driver_register(&msm8953_pinctrl_driver); +} +arch_initcall(msm8953_pinctrl_init); + +static void __exit msm8953_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8953_pinctrl_driver); +} +module_exit(msm8953_pinctrl_exit); + +MODULE_DESCRIPTION("QTI msm8953 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match); From 3d417196e2447811f9c73b0efe7ba02f5cb20fff Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Wed, 7 Oct 2020 19:06:12 +0300 Subject: [PATCH 12/80] dt-bindings: pinctrl: qcom: add msm8953 pinctrl bindings Add device tree bindings documentation for Qualcomm MSM8953 pinctrl driver. Signed-off-by: Vladimir Lypak Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201007160611.942754-2-junak.pub@gmail.com Signed-off-by: Linus Walleij --- .../pinctrl/qcom,msm8953-pinctrl.yaml | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml new file mode 100644 index 000000000000..abe9f4c9b1e3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM8953 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + MSM8953 platform. + +properties: + compatible: + const: qcom,msm8953-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, + qdsd_data1, qdsd_data2, qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, + atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens, + atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi, + blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, + blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, + blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo, + cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst, + cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0, + cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11, + dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16, + dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20, + dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25, + dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7, + dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data, + ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a, + gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, + gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx, + gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot, + key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0, + lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, + mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync, + nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1, + pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b, + pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b, + pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a, + sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout, + ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan, + wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8953-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 142>; + + serial_default: serial-pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + }; From 57972641810a97566ffd13e4be3f6a66d61eb3b5 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 16 Oct 2020 22:40:19 +0200 Subject: [PATCH 13/80] pinctrl: mt7622: drop pwm ch7 as mt7622 only has 6 channels mt7622 is reported by mediatek to have only 6 pwm channels so drop pindefines for 7th channel Signed-off-by: Frank Wunderlich Acked-by: Sean Wang Link: https://lore.kernel.org/r/20201016204019.2606-4-linux@fw-web.de Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7622.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index 38c5e166fd0f..68eee881ee3d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -501,12 +501,6 @@ static int mt7622_pwm_ch6_2_pins[] = { 81, }; static int mt7622_pwm_ch6_2_funcs[] = { 4, }; static int mt7622_pwm_ch6_3_pins[] = { 100, }; static int mt7622_pwm_ch6_3_funcs[] = { 0, }; -static int mt7622_pwm_ch7_0_pins[] = { 70, }; -static int mt7622_pwm_ch7_0_funcs[] = { 3, }; -static int mt7622_pwm_ch7_1_pins[] = { 82, }; -static int mt7622_pwm_ch7_1_funcs[] = { 4, }; -static int mt7622_pwm_ch7_2_pins[] = { 101, }; -static int mt7622_pwm_ch7_2_funcs[] = { 0, }; /* SD */ static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; @@ -703,9 +697,6 @@ static const struct group_desc mt7622_groups[] = { PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1), PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2), PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3), - PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0), - PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1), - PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2), PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0), PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1), PINCTRL_PIN_GROUP("snfi", mt7622_snfi), @@ -802,9 +793,7 @@ static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", "pwm_ch4_3", "pwm_ch5_0", "pwm_ch5_1", "pwm_ch5_2", "pwm_ch6_0", "pwm_ch6_1", - "pwm_ch6_2", "pwm_ch6_3", - "pwm_ch7_0", "pwm_ch7_1", - "pwm_ch7_2", }; + "pwm_ch6_2", "pwm_ch6_3", }; static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", }; static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0", "spic1_1", "spic2_0", From bb42b59310ebc33ab73dddd9a075d24003d1adac Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 1 Nov 2020 09:01:03 +0000 Subject: [PATCH 14/80] pinctrl: ingenic: Get rid of repetitive data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Abuse the pin function pointer to store the pin function value directly, when all the pins of a group have the same function value. Now when the pointer value is <= 3 (unsigned), the pointer value is used as the pin function; otherwise it is used as a regular pointer. This drastically reduces the number of pin function tables needed, and drops .data usage by about 2 KiB. Additionally, the few pin function tables that are still around now contain u8 instead of int, since the largest number that will be stored is 3. Signed-off-by: Paul Cercueil Tested-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20201101090104.5088-2-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 1256 ++++++++++------------------- 1 file changed, 446 insertions(+), 810 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index c8e50a58a5e5..01498b6ff83a 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -134,61 +134,42 @@ static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; -static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; -static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; -static int jz4740_uart0_data_funcs[] = { 1, 1, }; -static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; -static int jz4740_uart1_data_funcs[] = { 2, 2, }; -static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; -static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; -static int jz4740_nand_cs1_funcs[] = { 0, }; -static int jz4740_nand_cs2_funcs[] = { 0, }; -static int jz4740_nand_cs3_funcs[] = { 0, }; -static int jz4740_nand_cs4_funcs[] = { 0, }; -static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, }; -static int jz4740_pwm_pwm0_funcs[] = { 0, }; -static int jz4740_pwm_pwm1_funcs[] = { 0, }; -static int jz4740_pwm_pwm2_funcs[] = { 0, }; -static int jz4740_pwm_pwm3_funcs[] = { 0, }; -static int jz4740_pwm_pwm4_funcs[] = { 0, }; -static int jz4740_pwm_pwm5_funcs[] = { 0, }; -static int jz4740_pwm_pwm6_funcs[] = { 0, }; -static int jz4740_pwm_pwm7_funcs[] = { 0, }; -#define INGENIC_PIN_GROUP(name, id) \ +#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ { \ name, \ id##_pins, \ ARRAY_SIZE(id##_pins), \ - id##_funcs, \ + funcs, \ } +#define INGENIC_PIN_GROUP(name, id, func) \ + INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) + static const struct group_desc jz4740_groups[] = { - INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), - INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), - INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), - INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), - INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), - INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), - INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), + INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), + INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), + INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), + INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), + INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), + INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), + INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), - INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), - INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), - INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), - INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe), - INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), - INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), - INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), - INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), + INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), + INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), + INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), + INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), + INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), + INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), + INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), + INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), }; static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; @@ -268,54 +249,33 @@ static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; static int jz4725b_lcd_generic_pins[] = { 0x75, }; -static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, }; -static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; -static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, }; -static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, }; -static int jz4725b_uart_data_funcs[] = { 1, 1, }; -static int jz4725b_nand_cs1_funcs[] = { 0, }; -static int jz4725b_nand_cs2_funcs[] = { 0, }; -static int jz4725b_nand_cs3_funcs[] = { 0, }; -static int jz4725b_nand_cs4_funcs[] = { 0, }; -static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, }; -static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, }; -static int jz4725b_pwm_pwm0_funcs[] = { 0, }; -static int jz4725b_pwm_pwm1_funcs[] = { 0, }; -static int jz4725b_pwm_pwm2_funcs[] = { 0, }; -static int jz4725b_pwm_pwm3_funcs[] = { 0, }; -static int jz4725b_pwm_pwm4_funcs[] = { 0, }; -static int jz4725b_pwm_pwm5_funcs[] = { 0, }; -static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4725b_lcd_18bit_funcs[] = { 0, 0, }; -static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, }; -static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, }; -static int jz4725b_lcd_generic_funcs[] = { 0, }; +static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; static const struct group_desc jz4725b_groups[] = { - INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit), - INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit), - INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit), - INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit), - INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data), - INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1), - INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2), - INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3), - INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4), - INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale), - INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe), - INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4), - INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5), - INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit), - INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit), - INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit), - INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit), - INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special), - INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic), + INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), + INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, + jz4725b_mmc0_4bit_funcs), + INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), + INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), + INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), + INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), + INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), + INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), + INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), + INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), + INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), + INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), + INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), + INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), }; static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; @@ -431,110 +391,61 @@ static int jz4760_pwm_pwm5_pins[] = { 0x85, }; static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; -static int jz4760_uart0_data_funcs[] = { 0, 0, }; -static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; -static int jz4760_uart1_data_funcs[] = { 0, 0, }; -static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; -static int jz4760_uart2_data_funcs[] = { 0, 0, }; -static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; -static int jz4760_uart3_data_funcs[] = { 0, 1, }; -static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; -static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; -static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; -static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; -static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; -static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; -static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; -static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; -static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; -static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; -static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; -static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; -static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; -static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; -static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; -static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; -static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; -static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; -static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; -static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; -static int jz4760_nemc_wait_funcs[] = { 0, }; -static int jz4760_nemc_cs1_funcs[] = { 0, }; -static int jz4760_nemc_cs2_funcs[] = { 0, }; -static int jz4760_nemc_cs3_funcs[] = { 0, }; -static int jz4760_nemc_cs4_funcs[] = { 0, }; -static int jz4760_nemc_cs5_funcs[] = { 0, }; -static int jz4760_nemc_cs6_funcs[] = { 0, }; -static int jz4760_i2c0_funcs[] = { 0, 0, }; -static int jz4760_i2c1_funcs[] = { 0, 0, }; -static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4760_lcd_24bit_funcs[] = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, -}; -static int jz4760_pwm_pwm0_funcs[] = { 0, }; -static int jz4760_pwm_pwm1_funcs[] = { 0, }; -static int jz4760_pwm_pwm2_funcs[] = { 0, }; -static int jz4760_pwm_pwm3_funcs[] = { 0, }; -static int jz4760_pwm_pwm4_funcs[] = { 0, }; -static int jz4760_pwm_pwm5_funcs[] = { 0, }; -static int jz4760_pwm_pwm6_funcs[] = { 0, }; -static int jz4760_pwm_pwm7_funcs[] = { 0, }; +static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; +static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; static const struct group_desc jz4760_groups[] = { - INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), - INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), - INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), - INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), - INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), - INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), - INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), - INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), - INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), - INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), - INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), - INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), - INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), - INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), - INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), - INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), - INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), - INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), - INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), - INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), - INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), - INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), - INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), - INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), - INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), - INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), - INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), - INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), - INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), - INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), - INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), - INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), - INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), - INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), - INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), - INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), - INGENIC_PIN_GROUP("cim-data", jz4760_cim), - INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), + INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), + INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), + INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), + INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), + INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, + jz4760_uart3_data_funcs), + INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), + INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, + jz4760_mmc0_1bit_a_funcs), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), + INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), + INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), + INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), + INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), + INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), + INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), + INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), + INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), + INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), + INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), + INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), + INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), + INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), + INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), + INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), + INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), + INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), + INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), + INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), + INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), + INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), - INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), - INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), - INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), + INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), + INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), + INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), }; static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -735,200 +646,103 @@ static int jz4770_mac_rmii_pins[] = { static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; static int jz4770_otg_pins[] = { 0x8a, }; -static int jz4770_uart0_data_funcs[] = { 0, 0, }; -static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; -static int jz4770_uart1_data_funcs[] = { 0, 0, }; -static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; -static int jz4770_uart2_data_funcs[] = { 0, 0, }; -static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; -static int jz4770_uart3_data_funcs[] = { 0, 1, }; -static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; -static int jz4770_ssi0_dt_a_funcs[] = { 2, }; -static int jz4770_ssi0_dt_b_funcs[] = { 1, }; -static int jz4770_ssi0_dt_d_funcs[] = { 1, }; -static int jz4770_ssi0_dt_e_funcs[] = { 0, }; -static int jz4770_ssi0_dr_a_funcs[] = { 1, }; -static int jz4770_ssi0_dr_b_funcs[] = { 1, }; -static int jz4770_ssi0_dr_d_funcs[] = { 1, }; -static int jz4770_ssi0_dr_e_funcs[] = { 0, }; -static int jz4770_ssi0_clk_a_funcs[] = { 2, }; -static int jz4770_ssi0_clk_b_funcs[] = { 1, }; -static int jz4770_ssi0_clk_d_funcs[] = { 1, }; -static int jz4770_ssi0_clk_e_funcs[] = { 0, }; -static int jz4770_ssi0_gpc_b_funcs[] = { 1, }; -static int jz4770_ssi0_gpc_d_funcs[] = { 1, }; -static int jz4770_ssi0_gpc_e_funcs[] = { 0, }; -static int jz4770_ssi0_ce0_a_funcs[] = { 2, }; -static int jz4770_ssi0_ce0_b_funcs[] = { 1, }; -static int jz4770_ssi0_ce0_d_funcs[] = { 1, }; -static int jz4770_ssi0_ce0_e_funcs[] = { 0, }; -static int jz4770_ssi0_ce1_b_funcs[] = { 1, }; -static int jz4770_ssi0_ce1_d_funcs[] = { 1, }; -static int jz4770_ssi0_ce1_e_funcs[] = { 0, }; -static int jz4770_ssi1_dt_b_funcs[] = { 2, }; -static int jz4770_ssi1_dt_d_funcs[] = { 2, }; -static int jz4770_ssi1_dt_e_funcs[] = { 1, }; -static int jz4770_ssi1_dr_b_funcs[] = { 2, }; -static int jz4770_ssi1_dr_d_funcs[] = { 2, }; -static int jz4770_ssi1_dr_e_funcs[] = { 1, }; -static int jz4770_ssi1_clk_b_funcs[] = { 2, }; -static int jz4770_ssi1_clk_d_funcs[] = { 2, }; -static int jz4770_ssi1_clk_e_funcs[] = { 1, }; -static int jz4770_ssi1_gpc_b_funcs[] = { 2, }; -static int jz4770_ssi1_gpc_d_funcs[] = { 2, }; -static int jz4770_ssi1_gpc_e_funcs[] = { 1, }; -static int jz4770_ssi1_ce0_b_funcs[] = { 2, }; -static int jz4770_ssi1_ce0_d_funcs[] = { 2, }; -static int jz4770_ssi1_ce0_e_funcs[] = { 1, }; -static int jz4770_ssi1_ce1_b_funcs[] = { 2, }; -static int jz4770_ssi1_ce1_d_funcs[] = { 2, }; -static int jz4770_ssi1_ce1_e_funcs[] = { 1, }; -static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; -static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; -static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; -static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; -static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; -static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; -static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; -static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; -static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; -static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; -static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; -static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; -static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; -static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; -static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; -static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; -static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; -static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; -static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; -static int jz4770_nemc_wait_funcs[] = { 0, }; -static int jz4770_nemc_cs1_funcs[] = { 0, }; -static int jz4770_nemc_cs2_funcs[] = { 0, }; -static int jz4770_nemc_cs3_funcs[] = { 0, }; -static int jz4770_nemc_cs4_funcs[] = { 0, }; -static int jz4770_nemc_cs5_funcs[] = { 0, }; -static int jz4770_nemc_cs6_funcs[] = { 0, }; -static int jz4770_i2c0_funcs[] = { 0, 0, }; -static int jz4770_i2c1_funcs[] = { 0, 0, }; -static int jz4770_i2c2_funcs[] = { 2, 2, }; -static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, }; -static int jz4770_lcd_24bit_funcs[] = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, -}; -static int jz4770_pwm_pwm0_funcs[] = { 0, }; -static int jz4770_pwm_pwm1_funcs[] = { 0, }; -static int jz4770_pwm_pwm2_funcs[] = { 0, }; -static int jz4770_pwm_pwm3_funcs[] = { 0, }; -static int jz4770_pwm_pwm4_funcs[] = { 0, }; -static int jz4770_pwm_pwm5_funcs[] = { 0, }; -static int jz4770_pwm_pwm6_funcs[] = { 0, }; -static int jz4770_pwm_pwm7_funcs[] = { 0, }; -static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int jz4770_mac_mii_funcs[] = { 0, 0, }; -static int jz4770_otg_funcs[] = { 0, }; - static const struct group_desc jz4770_groups[] = { - INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), - INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), - INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), - INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), - INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), - INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), - INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a), - INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b), - INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d), - INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e), - INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a), - INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b), - INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d), - INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e), - INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a), - INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b), - INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d), - INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e), - INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b), - INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d), - INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e), - INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a), - INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b), - INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d), - INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e), - INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b), - INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d), - INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e), - INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b), - INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d), - INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e), - INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b), - INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d), - INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e), - INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b), - INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d), - INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e), - INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b), - INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d), - INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e), - INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b), - INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d), - INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e), - INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b), - INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d), - INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e), - INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), - INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), - INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), - INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), - INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e), - INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), - INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), - INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), - INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), - INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e), - INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), - INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), - INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), - INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), - INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e), - INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data), - INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data), - INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), - INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), - INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), - INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), - INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), - INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), - INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), - INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), - INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), - INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), - INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), - INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), - INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), - INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), - INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit), - INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit), - INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), + INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), + INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), + INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), + INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), + INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, + jz4760_uart3_data_funcs), + INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), + INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), + INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), + INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), + INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), + INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), + INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), + INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), + INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), + INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), + INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), + INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), + INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), + INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), + INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), + INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), + INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), + INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), + INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), + INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), + INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), + INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), + INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), + INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), + INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), + INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), + INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), + INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), + INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), + INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), + INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), + INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), + INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), + INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), + INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), + INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), + INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), + INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), + INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), + INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), + INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), + INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, + jz4760_mmc0_1bit_a_funcs), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), + INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), + INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), + INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), + INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), + INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), + INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), + INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), + INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), + INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), + INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), + INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), + INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), + INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), + INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), + INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), + INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), + INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), + INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), + INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), + INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), + INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), + INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), + INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), - INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), - INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), - INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), - INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii), - INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii), - INGENIC_PIN_GROUP("otg-vbus", jz4770_otg), + INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), + INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), + INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), + INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), + INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), + INGENIC_PIN_GROUP("otg-vbus", jz4770_otg, 0), }; static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -1090,156 +904,115 @@ static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; static int jz4780_i2s_sysclk_pins[] = { 0x85, }; static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; -static int jz4780_uart2_data_funcs[] = { 1, 1, }; -static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; -static int jz4780_uart4_data_funcs[] = { 2, 2, }; -static int jz4780_ssi0_dt_a_19_funcs[] = { 2, }; -static int jz4780_ssi0_dt_a_21_funcs[] = { 2, }; -static int jz4780_ssi0_dt_a_28_funcs[] = { 2, }; -static int jz4780_ssi0_dt_b_funcs[] = { 1, }; -static int jz4780_ssi0_dt_d_funcs[] = { 1, }; -static int jz4780_ssi0_dr_a_20_funcs[] = { 2, }; -static int jz4780_ssi0_dr_a_27_funcs[] = { 2, }; -static int jz4780_ssi0_dr_b_funcs[] = { 1, }; -static int jz4780_ssi0_dr_d_funcs[] = { 1, }; -static int jz4780_ssi0_clk_a_funcs[] = { 2, }; -static int jz4780_ssi0_clk_b_5_funcs[] = { 1, }; -static int jz4780_ssi0_clk_b_28_funcs[] = { 1, }; -static int jz4780_ssi0_clk_d_funcs[] = { 1, }; -static int jz4780_ssi0_gpc_b_funcs[] = { 1, }; -static int jz4780_ssi0_gpc_d_funcs[] = { 1, }; -static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, }; -static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, }; -static int jz4780_ssi0_ce0_b_funcs[] = { 1, }; -static int jz4780_ssi0_ce0_d_funcs[] = { 1, }; -static int jz4780_ssi0_ce1_b_funcs[] = { 1, }; -static int jz4780_ssi0_ce1_d_funcs[] = { 1, }; -static int jz4780_ssi1_dt_b_funcs[] = { 2, }; -static int jz4780_ssi1_dt_d_funcs[] = { 2, }; -static int jz4780_ssi1_dr_b_funcs[] = { 2, }; -static int jz4780_ssi1_dr_d_funcs[] = { 2, }; -static int jz4780_ssi1_clk_b_funcs[] = { 2, }; -static int jz4780_ssi1_clk_d_funcs[] = { 2, }; -static int jz4780_ssi1_gpc_b_funcs[] = { 2, }; -static int jz4780_ssi1_gpc_d_funcs[] = { 2, }; -static int jz4780_ssi1_ce0_b_funcs[] = { 2, }; -static int jz4780_ssi1_ce0_d_funcs[] = { 2, }; -static int jz4780_ssi1_ce1_b_funcs[] = { 2, }; -static int jz4780_ssi1_ce1_d_funcs[] = { 2, }; -static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; -static int jz4780_i2c3_funcs[] = { 1, 1, }; -static int jz4780_i2c4_e_funcs[] = { 1, 1, }; -static int jz4780_i2c4_f_funcs[] = { 1, 1, }; -static int jz4780_i2s_data_tx_funcs[] = { 0, }; -static int jz4780_i2s_data_rx_funcs[] = { 0, }; -static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; -static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, }; -static int jz4780_i2s_sysclk_funcs[] = { 2, }; -static int jz4780_hdmi_ddc_funcs[] = { 0, 0, }; +static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; static const struct group_desc jz4780_groups[] = { - INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), - INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), - INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data), - INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow), - INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), - INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), - INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), - INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19), - INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21), - INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28), - INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b), - INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d), - INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e), - INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20), - INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27), - INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b), - INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d), - INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e), - INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a), - INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5), - INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28), - INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d), - INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e), - INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b), - INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d), - INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e), - INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23), - INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25), - INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b), - INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d), - INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e), - INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b), - INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d), - INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e), - INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b), - INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d), - INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e), - INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b), - INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d), - INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e), - INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b), - INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d), - INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e), - INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b), - INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d), - INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e), - INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b), - INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d), - INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e), - INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b), - INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d), - INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e), - INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), - INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), - INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), - INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), - INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), - INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), - INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), - INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), - INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), - INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), - INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), - INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), - INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), - INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data), - INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), - INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), - INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), - INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), - INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), - INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), - INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), - INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), - INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), - INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), - INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), - INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), - INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), - INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), - INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), - INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), - INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), - INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx), - INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx), - INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx), - INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx), - INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk), - INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc), - INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), - INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), + INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), + INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), + INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), + INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), + INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, + jz4760_uart3_data_funcs), + INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), + INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), + INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), + INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), + INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), + INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), + INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), + INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), + INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), + INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), + INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), + INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), + INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), + INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), + INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), + INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), + INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), + INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), + INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), + INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), + INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), + INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), + INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), + INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), + INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), + INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), + INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), + INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), + INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), + INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), + INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), + INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), + INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), + INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), + INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), + INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), + INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), + INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), + INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), + INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), + INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), + INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), + INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), + INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), + INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), + INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), + INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), + INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, + jz4760_mmc0_1bit_a_funcs), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), + INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), + INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), + INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), + INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), + INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), + INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), + INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), + INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), + INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), + INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), + INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), + INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), + INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), + INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), + INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), + INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), + INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), + INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), + INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), + INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), + INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), + INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), + INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), + INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, + jz4780_i2s_clk_txrx_funcs), + INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), + INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), + INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), + INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), + INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), - INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), - INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), - INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), + INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), + INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), + INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), }; static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; @@ -1411,119 +1184,61 @@ static int x1000_mac_pins[] = { 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, }; -static int x1000_uart0_data_funcs[] = { 0, 0, }; -static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; -static int x1000_uart1_data_a_funcs[] = { 2, 2, }; -static int x1000_uart1_data_d_funcs[] = { 1, 1, }; -static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; -static int x1000_uart2_data_a_funcs[] = { 2, 2, }; -static int x1000_uart2_data_d_funcs[] = { 0, 0, }; -static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; -static int x1000_ssi_dt_a_22_funcs[] = { 2, }; -static int x1000_ssi_dt_a_29_funcs[] = { 2, }; -static int x1000_ssi_dt_d_funcs[] = { 0, }; -static int x1000_ssi_dr_a_23_funcs[] = { 2, }; -static int x1000_ssi_dr_a_28_funcs[] = { 2, }; -static int x1000_ssi_dr_d_funcs[] = { 0, }; -static int x1000_ssi_clk_a_24_funcs[] = { 2, }; -static int x1000_ssi_clk_a_26_funcs[] = { 2, }; -static int x1000_ssi_clk_d_funcs[] = { 0, }; -static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; -static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; -static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; -static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; -static int x1000_ssi_ce0_d_funcs[] = { 0, }; -static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; -static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; -static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; -static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; -static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; -static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; -static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; -static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_emc_addr_funcs[] = { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -}; -static int x1000_emc_rd_we_funcs[] = { 0, 0, }; -static int x1000_emc_wait_funcs[] = { 0, }; -static int x1000_emc_cs1_funcs[] = { 0, }; -static int x1000_emc_cs2_funcs[] = { 0, }; -static int x1000_i2c0_funcs[] = { 0, 0, }; -static int x1000_i2c1_a_funcs[] = { 2, 2, }; -static int x1000_i2c1_c_funcs[] = { 0, 0, }; -static int x1000_i2c2_funcs[] = { 1, 1, }; -static int x1000_i2s_data_tx_funcs[] = { 1, }; -static int x1000_i2s_data_rx_funcs[] = { 1, }; -static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, }; -static int x1000_i2s_sysclk_funcs[] = { 1, }; -static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -static int x1000_lcd_8bit_funcs[] = { - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -}; -static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; -static int x1000_pwm_pwm0_funcs[] = { 0, }; -static int x1000_pwm_pwm1_funcs[] = { 1, }; -static int x1000_pwm_pwm2_funcs[] = { 1, }; -static int x1000_pwm_pwm3_funcs[] = { 2, }; -static int x1000_pwm_pwm4_funcs[] = { 0, }; -static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - static const struct group_desc x1000_groups[] = { - INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), - INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), - INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), - INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), - INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), - INGENIC_PIN_GROUP("sfc", x1000_sfc), - INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), - INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), - INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), - INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), - INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), - INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), - INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), - INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), - INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), - INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), - INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), - INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), - INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), - INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), - INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), - INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), - INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), - INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), - INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), - INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), - INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), - INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), - INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), - INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), - INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), - INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), - INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), - INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), - INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), - INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), - INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), - INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), - INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx), - INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx), - INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx), - INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk), - INGENIC_PIN_GROUP("cim-data", x1000_cim), - INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), - INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), + INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), + INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), + INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), + INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), + INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), + INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), + INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), + INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), + INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), + INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), + INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), + INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), + INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), + INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), + INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), + INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), + INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), + INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), + INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), + INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), + INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), + INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), + INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), + INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), + INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), + INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), + INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), + INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), + INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), + INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), + INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), + INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), + INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), + INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), + INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), + INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), + INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), + INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), + INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), + INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), + INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), + INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), + INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), + INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), - INGENIC_PIN_GROUP("mac", x1000_mac), + INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), + INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), + INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), + INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), + INGENIC_PIN_GROUP("mac", x1000_mac, 1), }; static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -1633,56 +1348,32 @@ static int x1500_pwm_pwm2_pins[] = { 0x5b, }; static int x1500_pwm_pwm3_pins[] = { 0x26, }; static int x1500_pwm_pwm4_pins[] = { 0x58, }; -static int x1500_uart0_data_funcs[] = { 0, 0, }; -static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; -static int x1500_uart1_data_a_funcs[] = { 2, 2, }; -static int x1500_uart1_data_d_funcs[] = { 1, 1, }; -static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; -static int x1500_uart2_data_a_funcs[] = { 2, 2, }; -static int x1500_uart2_data_d_funcs[] = { 0, 0, }; -static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; -static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; -static int x1500_i2c0_funcs[] = { 0, 0, }; -static int x1500_i2c1_a_funcs[] = { 2, 2, }; -static int x1500_i2c1_c_funcs[] = { 0, 0, }; -static int x1500_i2c2_funcs[] = { 1, 1, }; -static int x1500_i2s_data_tx_funcs[] = { 1, }; -static int x1500_i2s_data_rx_funcs[] = { 1, }; -static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, }; -static int x1500_i2s_sysclk_funcs[] = { 1, }; -static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -static int x1500_pwm_pwm0_funcs[] = { 0, }; -static int x1500_pwm_pwm1_funcs[] = { 1, }; -static int x1500_pwm_pwm2_funcs[] = { 1, }; -static int x1500_pwm_pwm3_funcs[] = { 2, }; -static int x1500_pwm_pwm4_funcs[] = { 0, }; - static const struct group_desc x1500_groups[] = { - INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), - INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), - INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), - INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), - INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), - INGENIC_PIN_GROUP("sfc", x1000_sfc), - INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), - INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), - INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), - INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), - INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), - INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), - INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx), - INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx), - INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx), - INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk), - INGENIC_PIN_GROUP("cim-data", x1500_cim), + INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), + INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), + INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), + INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), + INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), + INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), + INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), + INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), + INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), + INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), + INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), + INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), + INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), + INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), + INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), + INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), + INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), - INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), - INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), - INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), - INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), + INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), + INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), + INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), + INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), }; static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -1811,124 +1502,62 @@ static int x1830_mac_pins[] = { 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, }; -static int x1830_uart0_data_funcs[] = { 0, 0, }; -static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; -static int x1830_uart1_data_funcs[] = { 0, 0, }; -static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; -static int x1830_ssi0_dt_funcs[] = { 0, }; -static int x1830_ssi0_dr_funcs[] = { 0, }; -static int x1830_ssi0_clk_funcs[] = { 0, }; -static int x1830_ssi0_gpc_funcs[] = { 0, }; -static int x1830_ssi0_ce0_funcs[] = { 0, }; -static int x1830_ssi0_ce1_funcs[] = { 0, }; -static int x1830_ssi1_dt_c_funcs[] = { 1, }; -static int x1830_ssi1_dr_c_funcs[] = { 1, }; -static int x1830_ssi1_clk_c_funcs[] = { 1, }; -static int x1830_ssi1_gpc_c_funcs[] = { 1, }; -static int x1830_ssi1_ce0_c_funcs[] = { 1, }; -static int x1830_ssi1_ce1_c_funcs[] = { 1, }; -static int x1830_ssi1_dt_d_funcs[] = { 2, }; -static int x1830_ssi1_dr_d_funcs[] = { 2, }; -static int x1830_ssi1_clk_d_funcs[] = { 2, }; -static int x1830_ssi1_gpc_d_funcs[] = { 2, }; -static int x1830_ssi1_ce0_d_funcs[] = { 2, }; -static int x1830_ssi1_ce1_d_funcs[] = { 2, }; -static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; -static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; -static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; -static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; -static int x1830_i2c0_funcs[] = { 1, 1, }; -static int x1830_i2c1_funcs[] = { 0, 0, }; -static int x1830_i2c2_funcs[] = { 1, 1, }; -static int x1830_i2s_data_tx_funcs[] = { 0, }; -static int x1830_i2s_data_rx_funcs[] = { 0, }; -static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, }; -static int x1830_i2s_clk_rx_funcs[] = { 0, 0, }; -static int x1830_i2s_sysclk_funcs[] = { 0, }; -static int x1830_lcd_rgb_18bit_funcs[] = { - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, -}; -static int x1830_lcd_slcd_8bit_funcs[] = { - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -}; -static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; -static int x1830_pwm_pwm0_b_funcs[] = { 0, }; -static int x1830_pwm_pwm0_c_funcs[] = { 1, }; -static int x1830_pwm_pwm1_b_funcs[] = { 0, }; -static int x1830_pwm_pwm1_c_funcs[] = { 1, }; -static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; -static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; -static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; -static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; -static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; -static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; -static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; -static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; -static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; -static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; -static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; -static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; -static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; - static const struct group_desc x1830_groups[] = { - INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), - INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), - INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), - INGENIC_PIN_GROUP("sfc", x1830_sfc), - INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), - INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), - INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), - INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), - INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), - INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), - INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), - INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), - INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), - INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), - INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), - INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), - INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), - INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), - INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), - INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), - INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), - INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), - INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), - INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), - INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), - INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), - INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), - INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), - INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), - INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx), - INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx), - INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx), - INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx), - INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk), - INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit), - INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit), - INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit), + INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), + INGENIC_PIN_GROUP("sfc", x1830_sfc, 1), + INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), + INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), + INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), + INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), + INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), + INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), + INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), + INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), + INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), + INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), + INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), + INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), + INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), + INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), + INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), + INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), + INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), + INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), + INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), + INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), + INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), + INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), + INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), + INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), + INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), + INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), + INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), + INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), + INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), + INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit, 0), + INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), + INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), { "lcd-no-pins", }, - INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), - INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), - INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), - INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), - INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), - INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), - INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), - INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), - INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), - INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), - INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), - INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), - INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), - INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), - INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), - INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), - INGENIC_PIN_GROUP("mac", x1830_mac), + INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), + INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), + INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), + INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), + INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), + INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), + INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), + INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), + INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), + INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), + INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), + INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), + INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), + INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), + INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), + INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), + INGENIC_PIN_GROUP("mac", x1830_mac, 0), }; static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -2381,6 +2010,8 @@ static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, struct function_desc *func; struct group_desc *grp; unsigned int i; + uintptr_t mode; + u8 *pin_modes; func = pinmux_generic_get_function(pctldev, selector); if (!func) @@ -2393,10 +2024,15 @@ static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "enable function %s group %s\n", func->name, grp->name); - for (i = 0; i < grp->num_pins; i++) { - int *pin_modes = grp->data; + mode = (uintptr_t)grp->data; + if (mode <= 3) { + for (i = 0; i < grp->num_pins; i++) + ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); + } else { + pin_modes = grp->data; - ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); + for (i = 0; i < grp->num_pins; i++) + ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); } return 0; From 016e054d6926390a583a6422f3193e222be62eb9 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 1 Nov 2020 09:01:04 +0000 Subject: [PATCH 15/80] pinctrl: ingenic: Add lcd-8bit group for JZ4770 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the "lcd-8bit" group to the "lcd" function. As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could be modified to only contain the pins not already included in "lcd-8bit", just like how it's done for the JZ4740 and JZ4725B platforms. However, we can't do that without breaking Device Tree ABI, so in that case we have no choice but to have two groups containing the same pins. Signed-off-by: Paul Cercueil Tested-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20201101090104.5088-3-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 01498b6ff83a..6d3c2c80c8ec 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -626,6 +626,10 @@ static int jz4770_cim_8bit_pins[] = { static int jz4770_cim_12bit_pins[] = { 0x32, 0x33, 0xb0, 0xb1, }; +static int jz4770_lcd_8bit_pins[] = { + 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, + 0x48, 0x49, 0x52, 0x53, +}; static int jz4770_lcd_24bit_pins[] = { 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, @@ -730,6 +734,7 @@ static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), + INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), { "lcd-no-pins", }, INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), @@ -791,7 +796,9 @@ static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; -static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; +static const char *jz4770_lcd_groups[] = { + "lcd-8bit", "lcd-24bit", "lcd-no-pins", +}; static const char *jz4770_pwm0_groups[] = { "pwm0", }; static const char *jz4770_pwm1_groups[] = { "pwm1", }; static const char *jz4770_pwm2_groups[] = { "pwm2", }; From 39cc1d3397053f340776c99e55b733a063fa2c69 Mon Sep 17 00:00:00 2001 From: Coiby Xu Date: Fri, 6 Nov 2020 07:19:11 +0800 Subject: [PATCH 16/80] pinctrl: amd: print debounce filter info in debugfs Print the status of debounce filter as follows, $ cat /sys/kernel/debug/gpio pin129 interrupt is disabled | interrupt is masked | disable wakeup in S0i3 state | disable wakeup in S3 state | disable wakeup in S4/S5 state| input is high | pull-up is disabled | Pull-down is disabled | output is disabled | debouncing filter disabled | 0x50000 pin130 interrupt is disabled | interrupt is masked | disable wakeup in S0i3 state | disable wakeup in S3 state | disable wakeup in S4/S5 state | input is high | pull-up is disabled | Pull-down is disabled | output is disabled | debouncing filter (high) enabled | debouncing timeout is 124800 (us)| 0x503c8 Signed-off-by: Coiby Xu Link: https://lore.kernel.org/r/20201105231912.69527-4-coiby.xu@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 43 +++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9a760f5cd7ed..8aa2e876cb47 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -197,10 +197,16 @@ static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) { u32 pin_reg; + u32 db_cntrl; unsigned long flags; unsigned int bank, i, pin_num; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + bool tmr_out_unit; + unsigned int time; + unsigned int unit; + bool tmr_large; + char *level_trig; char *active_level; char *interrupt_enable; @@ -214,6 +220,8 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) char *pull_down_enable; char *output_value; char *output_enable; + char debounce_value[40]; + char *debounce_enable; for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { seq_printf(s, "GPIO bank%d\t", bank); @@ -327,13 +335,44 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) pin_sts = "input is low|"; } + db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; + if (db_cntrl) { + tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); + tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); + time = pin_reg & DB_TMR_OUT_MASK; + if (tmr_large) { + if (tmr_out_unit) + unit = 62500; + else + unit = 15625; + } else { + if (tmr_out_unit) + unit = 244; + else + unit = 61; + } + if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) + debounce_enable = "debouncing filter (high and low) enabled|"; + else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) + debounce_enable = "debouncing filter (low) enabled|"; + else + debounce_enable = "debouncing filter (high) enabled|"; + + snprintf(debounce_value, sizeof(debounce_value), + "debouncing timeout is %u (us)|", time * unit); + } else { + debounce_enable = "debouncing filter disabled|"; + snprintf(debounce_value, sizeof(debounce_value), " "); + } + seq_printf(s, "%s %s %s %s %s %s\n" - " %s %s %s %s %s %s %s 0x%x\n", + " %s %s %s %s %s %s %s %s %s 0x%x\n", level_trig, active_level, interrupt_enable, interrupt_mask, wake_cntrl0, wake_cntrl1, wake_cntrl2, pin_sts, pull_up_sel, pull_up_enable, pull_down_enable, - output_value, output_enable, pin_reg); + output_value, output_enable, + debounce_enable, debounce_value, pin_reg); } } } From be117ca32261c3331b614f440c737650791a6998 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 6 Nov 2020 04:27:08 +0000 Subject: [PATCH 17/80] pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a selected config This patch reworks PINCTRL_MSM to be a visible option, and instead of having the various SoC specific drivers select PINCTRL_MSM, this switches those configs to depend on PINCTRL_MSM. This is useful, as it will be needed in order to cleanly support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. Without this change, we would eventually have to add dependency lines to every config that selects PINCTRL_MSM, and that would becomes a maintenance headache. We also add PINCTRL_MSM to the arm64 defconfig to avoid surprises as otherwise PINCTRL_MSM/IPQ* options previously enabled, will be off. Signed-off-by: John Stultz Reviewed-by: Bjorn Andersson Cc: Catalin Marinas Cc: Will Deacon Cc: Andy Gross Cc: Bjorn Andersson Cc: Joerg Roedel Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Linus Walleij Cc: Vinod Koul Cc: Kalle Valo Cc: Maulik Shah Cc: Lina Iyer Cc: Saravana Kannan Cc: Todd Kjos Cc: Greg Kroah-Hartman Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-1-john.stultz@linaro.org Signed-off-by: Linus Walleij --- arch/arm64/configs/defconfig | 1 + drivers/pinctrl/qcom/Kconfig | 48 ++++++++++++++++++------------------ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..45768828fdb8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -483,6 +483,7 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 98d075447a32..dc7d93951da7 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -2,7 +2,7 @@ if (ARCH_QCOM || COMPILE_TEST) config PINCTRL_MSM - bool + bool "Qualcomm core pin controller driver" select PINMUX select PINCONF select GENERIC_PINCONF @@ -13,7 +13,7 @@ config PINCTRL_MSM config PINCTRL_APQ8064 tristate "Qualcomm APQ8064 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8064 platform. @@ -21,7 +21,7 @@ config PINCTRL_APQ8064 config PINCTRL_APQ8084 tristate "Qualcomm APQ8084 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8084 platform. @@ -29,7 +29,7 @@ config PINCTRL_APQ8084 config PINCTRL_IPQ4019 tristate "Qualcomm IPQ4019 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ4019 platform. @@ -37,7 +37,7 @@ config PINCTRL_IPQ4019 config PINCTRL_IPQ8064 tristate "Qualcomm IPQ8064 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. @@ -45,7 +45,7 @@ config PINCTRL_IPQ8064 config PINCTRL_IPQ8074 tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -55,7 +55,7 @@ config PINCTRL_IPQ8074 config PINCTRL_IPQ6018 tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -65,7 +65,7 @@ config PINCTRL_IPQ6018 config PINCTRL_MSM8226 tristate "Qualcomm 8226 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -74,7 +74,7 @@ config PINCTRL_MSM8226 config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8660 platform. @@ -82,7 +82,7 @@ config PINCTRL_MSM8660 config PINCTRL_MSM8960 tristate "Qualcomm 8960 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8960 platform. @@ -90,7 +90,7 @@ config PINCTRL_MSM8960 config PINCTRL_MDM9615 tristate "Qualcomm 9615 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 9615 platform. @@ -98,7 +98,7 @@ config PINCTRL_MDM9615 config PINCTRL_MSM8X74 tristate "Qualcomm 8x74 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8974 platform. @@ -106,7 +106,7 @@ config PINCTRL_MSM8X74 config PINCTRL_MSM8916 tristate "Qualcomm 8916 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. @@ -124,7 +124,7 @@ config PINCTRL_MSM8953 config PINCTRL_MSM8976 tristate "Qualcomm 8976 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8976 platform. @@ -134,7 +134,7 @@ config PINCTRL_MSM8976 config PINCTRL_MSM8994 tristate "Qualcomm 8994 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8994 platform. The @@ -143,7 +143,7 @@ config PINCTRL_MSM8994 config PINCTRL_MSM8996 tristate "Qualcomm MSM8996 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. @@ -151,7 +151,7 @@ config PINCTRL_MSM8996 config PINCTRL_MSM8998 tristate "Qualcomm MSM8998 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8998 platform. @@ -159,7 +159,7 @@ config PINCTRL_MSM8998 config PINCTRL_QCS404 tristate "Qualcomm QCS404 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found in the Qualcomm QCS404 platform. @@ -167,7 +167,7 @@ config PINCTRL_QCS404 config PINCTRL_QDF2XXX tristate "Qualcomm Technologies QDF2xxx pin controller driver" depends on GPIOLIB && ACPI - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the GPIO driver for the TLMM block found on the Qualcomm Technologies QDF2xxx SOCs. @@ -204,7 +204,7 @@ config PINCTRL_QCOM_SSBI_PMIC config PINCTRL_SC7180 tristate "Qualcomm Technologies Inc SC7180 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -213,7 +213,7 @@ config PINCTRL_SC7180 config PINCTRL_SDM660 tristate "Qualcomm Technologies Inc SDM660 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -222,7 +222,7 @@ config PINCTRL_SDM660 config PINCTRL_SDM845 tristate "Qualcomm Technologies Inc SDM845 pin controller driver" depends on GPIOLIB && (OF || ACPI) - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -231,7 +231,7 @@ config PINCTRL_SDM845 config PINCTRL_SM8150 tristate "Qualcomm Technologies Inc SM8150 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -240,7 +240,7 @@ config PINCTRL_SM8150 config PINCTRL_SM8250 tristate "Qualcomm Technologies Inc SM8250 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm From 38e86f5c2645f3c16f698fa7e66b4eb23da5369c Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 6 Nov 2020 04:27:09 +0000 Subject: [PATCH 18/80] pinctrl: qcom: Allow pinctrl-msm code to be loadable as a module Tweaks to allow pinctrl-msm code to be loadable as a module. This is needed in order to support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. This requires that we tweak Kconfigs selecting PINCTRL_MSM to also depend on QCOM_SCM || QCOM_SCM=n so that we match the module setting of QCOM_SCM. Signed-off-by: John Stultz Reviewed-by: Bjorn Andersson Cc: Catalin Marinas Cc: Will Deacon Cc: Andy Gross Cc: Bjorn Andersson Cc: Joerg Roedel Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Linus Walleij Cc: Vinod Koul Cc: Kalle Valo Cc: Maulik Shah Cc: Lina Iyer Cc: Saravana Kannan Cc: Todd Kjos Cc: Greg Kroah-Hartman Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-2-john.stultz@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 3 ++- drivers/pinctrl/qcom/pinctrl-msm.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dc7d93951da7..03f1635a4b7e 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -2,7 +2,8 @@ if (ARCH_QCOM || COMPILE_TEST) config PINCTRL_MSM - bool "Qualcomm core pin controller driver" + tristate "Qualcomm core pin controller driver" + depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y select PINMUX select PINCONF select GENERIC_PINCONF diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index c4bcda90aac4..988343ac49b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1443,3 +1443,5 @@ int msm_pinctrl_remove(struct platform_device *pdev) } EXPORT_SYMBOL(msm_pinctrl_remove); +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver"); +MODULE_LICENSE("GPL v2"); From d0511b5496c03cdbcda55a9b57c32cdd751920ed Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 6 Nov 2020 04:27:10 +0000 Subject: [PATCH 19/80] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module Allow the qcom_scm driver to be loadable as a permenent module. This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to ensure that drivers that call into the qcom_scm driver are also built as modules. While not ideal in some cases its the only safe way I can find to avoid build errors without having those drivers select QCOM_SCM and have to force it on (as QCOM_SCM=n can be valid for those drivers). Signed-off-by: John Stultz Reviewed-by: Bjorn Andersson Acked-by: Kalle Valo Acked-by: Greg Kroah-Hartman Cc: Catalin Marinas Cc: Will Deacon Cc: Andy Gross Cc: Bjorn Andersson Cc: Joerg Roedel Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Linus Walleij Cc: Vinod Koul Cc: Kalle Valo Cc: Maulik Shah Cc: Lina Iyer Cc: Saravana Kannan Cc: Todd Kjos Cc: Greg Kroah-Hartman Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-3-john.stultz@linaro.org Signed-off-by: Linus Walleij --- drivers/firmware/Kconfig | 4 ++-- drivers/firmware/Makefile | 3 ++- drivers/firmware/qcom_scm.c | 4 ++++ drivers/iommu/Kconfig | 2 ++ drivers/net/wireless/ath/ath10k/Kconfig | 1 + 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 3315e3c21586..5e369928bc56 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -235,8 +235,8 @@ config INTEL_STRATIX10_RSU Say Y here if you want Intel RSU support. config QCOM_SCM - bool - depends on ARM || ARM64 + tristate "Qcom SCM driver" + depends on (ARM && HAVE_ARM_SMCCC) || ARM64 select RESET_CONTROLLER config QCOM_SCM_DOWNLOAD_MODE_DEFAULT diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 5e013b6a3692..523173cbff33 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -17,7 +17,8 @@ obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o -obj-$(CONFIG_QCOM_SCM) += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o +obj-$(CONFIG_QCOM_SCM) += qcom-scm.o +qcom-scm-objs += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 7be48c1bec96..6f431b73e617 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1280,6 +1280,7 @@ static const struct of_device_id qcom_scm_dt_match[] = { { .compatible = "qcom,scm" }, {} }; +MODULE_DEVICE_TABLE(of, qcom_scm_dt_match); static struct platform_driver qcom_scm_driver = { .driver = { @@ -1295,3 +1296,6 @@ static int __init qcom_scm_init(void) return platform_driver_register(&qcom_scm_driver); } subsys_initcall(qcom_scm_init); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 04878caf6da4..c64d7a2b6513 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -248,6 +248,7 @@ config SPAPR_TCE_IOMMU config ARM_SMMU tristate "ARM Ltd. System MMU (SMMU) Support" depends on ARM64 || ARM || (COMPILE_TEST && !GENERIC_ATOMIC64) + depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select ARM_DMA_USE_IOMMU if ARM @@ -375,6 +376,7 @@ config QCOM_IOMMU # Note: iommu drivers cannot (yet?) be built as modules bool "Qualcomm IOMMU Support" depends on ARCH_QCOM || (COMPILE_TEST && !GENERIC_ATOMIC64) + depends on QCOM_SCM=y select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select ARM_DMA_USE_IOMMU diff --git a/drivers/net/wireless/ath/ath10k/Kconfig b/drivers/net/wireless/ath/ath10k/Kconfig index 40f91bc8514d..741289e385d5 100644 --- a/drivers/net/wireless/ath/ath10k/Kconfig +++ b/drivers/net/wireless/ath/ath10k/Kconfig @@ -44,6 +44,7 @@ config ATH10K_SNOC tristate "Qualcomm ath10k SNOC support" depends on ATH10K depends on ARCH_QCOM || COMPILE_TEST + depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y select QCOM_QMI_HELPERS help This module adds support for integrated WCN3990 chip connected From 54515257ca3acc99e26117727874a7566148e64b Mon Sep 17 00:00:00 2001 From: Kaixu Xia Date: Fri, 6 Nov 2020 16:36:35 +0800 Subject: [PATCH 20/80] pinctrl: ocelot: Remove unnecessary conversion to bool Fix the following coccicheck warning: ./drivers/pinctrl/pinctrl-ocelot.c:732:28-33: WARNING: conversion to bool not needed here Reported-by: Tosk Robot Signed-off-by: Kaixu Xia Link: https://lore.kernel.org/r/1604651795-1220-1-git-send-email-kaixuxia@tencent.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index a4a1b00f7f0d..c2be5c44077f 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -729,7 +729,7 @@ static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, if (err) return err; if (param == PIN_CONFIG_BIAS_DISABLE) - val = (val == 0 ? true : false); + val = (val == 0); else if (param == PIN_CONFIG_BIAS_PULL_DOWN) val = (val & BIAS_PD_BIT ? true : false); else /* PIN_CONFIG_BIAS_PULL_UP */ From ad3b508c90ad20c63ac4fcd076e22b9f0294124d Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 6 Nov 2020 10:31:15 +0100 Subject: [PATCH 21/80] dt-bindings: pinctrl: ocelot: Add Luton SoC support Add the documentation for the Microsemi Luton pinmuxing and gpio controller. Signed-off-by: Gregory CLEMENT Link: https://lore.kernel.org/r/20201106093118.965152-2-gregory.clement@bootlin.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 00912449237b..58ea2ae57713 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -3,7 +3,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" + "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl" + or "mscc,luton-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. From e1822384d6d680a31724872b3134ce03eb6a27bc Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 6 Nov 2020 10:31:16 +0100 Subject: [PATCH 22/80] dt-bindings: pinctrl: ocelot: Add Serval SoC support Add the documentation for the Microsemi Serval pinmuxing and gpio controller. Signed-off-by: Gregory CLEMENT Link: https://lore.kernel.org/r/20201106093118.965152-3-gregory.clement@bootlin.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 58ea2ae57713..db99bd95d423 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -3,8 +3,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl" - or "mscc,luton-pinctrl" + "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", + "mscc,luton-pinctrl" or "mscc,serval-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. From 8f27440decb75cc92ab37ce3140c73198689feaf Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Fri, 6 Nov 2020 10:31:17 +0100 Subject: [PATCH 23/80] pinctrl: ocelot: Add support for Luton platforms This patch adds support for Luton pinctrl, using the ocelot driver as basis. It adds pinconfig support as well, as supported by the platform. gclement: Split from a larger patch adding support all platforms in the same time. Signed-off-by: Lars Povlsen Signed-off-by: Gregory CLEMENT Link: https://lore.kernel.org/r/20201106093118.965152-4-gregory.clement@bootlin.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 92 ++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index c2be5c44077f..9ccecdc30aec 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -158,6 +158,88 @@ struct ocelot_pinctrl { u8 stride; }; +#define LUTON_P(p, f0, f1) \ +static struct ocelot_pin_caps luton_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ + }, \ +} + +LUTON_P(0, SG0, NONE); +LUTON_P(1, SG0, NONE); +LUTON_P(2, SG0, NONE); +LUTON_P(3, SG0, NONE); +LUTON_P(4, TACHO, NONE); +LUTON_P(5, TWI, PHY_LED); +LUTON_P(6, TWI, PHY_LED); +LUTON_P(7, NONE, PHY_LED); +LUTON_P(8, EXT_IRQ, PHY_LED); +LUTON_P(9, EXT_IRQ, PHY_LED); +LUTON_P(10, SFP, PHY_LED); +LUTON_P(11, SFP, PHY_LED); +LUTON_P(12, SFP, PHY_LED); +LUTON_P(13, SFP, PHY_LED); +LUTON_P(14, SI, PHY_LED); +LUTON_P(15, SI, PHY_LED); +LUTON_P(16, SI, PHY_LED); +LUTON_P(17, SFP, PHY_LED); +LUTON_P(18, SFP, PHY_LED); +LUTON_P(19, SFP, PHY_LED); +LUTON_P(20, SFP, PHY_LED); +LUTON_P(21, SFP, PHY_LED); +LUTON_P(22, SFP, PHY_LED); +LUTON_P(23, SFP, PHY_LED); +LUTON_P(24, SFP, PHY_LED); +LUTON_P(25, SFP, PHY_LED); +LUTON_P(26, SFP, PHY_LED); +LUTON_P(27, SFP, PHY_LED); +LUTON_P(28, SFP, PHY_LED); +LUTON_P(29, PWM, NONE); +LUTON_P(30, UART, NONE); +LUTON_P(31, UART, NONE); + +#define LUTON_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &luton_pin_##n \ +} + +static const struct pinctrl_pin_desc luton_pins[] = { + LUTON_PIN(0), + LUTON_PIN(1), + LUTON_PIN(2), + LUTON_PIN(3), + LUTON_PIN(4), + LUTON_PIN(5), + LUTON_PIN(6), + LUTON_PIN(7), + LUTON_PIN(8), + LUTON_PIN(9), + LUTON_PIN(10), + LUTON_PIN(11), + LUTON_PIN(12), + LUTON_PIN(13), + LUTON_PIN(14), + LUTON_PIN(15), + LUTON_PIN(16), + LUTON_PIN(17), + LUTON_PIN(18), + LUTON_PIN(19), + LUTON_PIN(20), + LUTON_PIN(21), + LUTON_PIN(22), + LUTON_PIN(23), + LUTON_PIN(24), + LUTON_PIN(25), + LUTON_PIN(26), + LUTON_PIN(27), + LUTON_PIN(28), + LUTON_PIN(29), + LUTON_PIN(30), + LUTON_PIN(31), +}; + #define OCELOT_P(p, f0, f1, f2) \ static struct ocelot_pin_caps ocelot_pin_##p = { \ .pin = p, \ @@ -868,6 +950,15 @@ static const struct pinctrl_ops ocelot_pctl_ops = { .dt_free_map = pinconf_generic_dt_free_map, }; +static struct pinctrl_desc luton_desc = { + .name = "luton-pinctrl", + .pins = luton_pins, + .npins = ARRAY_SIZE(luton_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + static struct pinctrl_desc ocelot_desc = { .name = "ocelot-pinctrl", .pins = ocelot_pins, @@ -1151,6 +1242,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, } static const struct of_device_id ocelot_pinctrl_of_match[] = { + { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, From 6e6347e2daf52123127a60e92d808f6a3d674b4b Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Fri, 6 Nov 2020 10:31:18 +0100 Subject: [PATCH 24/80] pinctrl: ocelot: Add support for Serval platforms This patch adds support for Serval pinctrl, using the ocelot driver as basis. It adds pinconfig support as well, as supported by the platform. gclement: Split from a larger patch adding support all platforms in the same time. Signed-off-by: Lars Povlsen Signed-off-by: Gregory CLEMENT Link: https://lore.kernel.org/r/20201106093118.965152-5-gregory.clement@bootlin.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 92 ++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 9ccecdc30aec..2fd18e356d0c 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -240,6 +240,88 @@ static const struct pinctrl_pin_desc luton_pins[] = { LUTON_PIN(31), }; +#define SERVAL_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps serval_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + }, \ +} + +SERVAL_P(0, SG0, NONE, NONE); +SERVAL_P(1, SG0, NONE, NONE); +SERVAL_P(2, SG0, NONE, NONE); +SERVAL_P(3, SG0, NONE, NONE); +SERVAL_P(4, TACHO, NONE, NONE); +SERVAL_P(5, PWM, NONE, NONE); +SERVAL_P(6, TWI, NONE, NONE); +SERVAL_P(7, TWI, NONE, NONE); +SERVAL_P(8, SI, NONE, NONE); +SERVAL_P(9, SI, MD, NONE); +SERVAL_P(10, SI, MD, NONE); +SERVAL_P(11, SFP, MD, TWI_SCL_M); +SERVAL_P(12, SFP, MD, TWI_SCL_M); +SERVAL_P(13, SFP, UART2, TWI_SCL_M); +SERVAL_P(14, SFP, UART2, TWI_SCL_M); +SERVAL_P(15, SFP, PTP0, TWI_SCL_M); +SERVAL_P(16, SFP, PTP0, TWI_SCL_M); +SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); +SERVAL_P(18, SFP, NONE, TWI_SCL_M); +SERVAL_P(19, SFP, NONE, TWI_SCL_M); +SERVAL_P(20, SFP, NONE, TWI_SCL_M); +SERVAL_P(21, SFP, NONE, TWI_SCL_M); +SERVAL_P(22, NONE, NONE, NONE); +SERVAL_P(23, NONE, NONE, NONE); +SERVAL_P(24, NONE, NONE, NONE); +SERVAL_P(25, NONE, NONE, NONE); +SERVAL_P(26, UART, NONE, NONE); +SERVAL_P(27, UART, NONE, NONE); +SERVAL_P(28, IRQ0, NONE, NONE); +SERVAL_P(29, IRQ1, NONE, NONE); +SERVAL_P(30, PTP0, NONE, NONE); +SERVAL_P(31, PTP0, NONE, NONE); + +#define SERVAL_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &serval_pin_##n \ +} + +static const struct pinctrl_pin_desc serval_pins[] = { + SERVAL_PIN(0), + SERVAL_PIN(1), + SERVAL_PIN(2), + SERVAL_PIN(3), + SERVAL_PIN(4), + SERVAL_PIN(5), + SERVAL_PIN(6), + SERVAL_PIN(7), + SERVAL_PIN(8), + SERVAL_PIN(9), + SERVAL_PIN(10), + SERVAL_PIN(11), + SERVAL_PIN(12), + SERVAL_PIN(13), + SERVAL_PIN(14), + SERVAL_PIN(15), + SERVAL_PIN(16), + SERVAL_PIN(17), + SERVAL_PIN(18), + SERVAL_PIN(19), + SERVAL_PIN(20), + SERVAL_PIN(21), + SERVAL_PIN(22), + SERVAL_PIN(23), + SERVAL_PIN(24), + SERVAL_PIN(25), + SERVAL_PIN(26), + SERVAL_PIN(27), + SERVAL_PIN(28), + SERVAL_PIN(29), + SERVAL_PIN(30), + SERVAL_PIN(31), +}; + #define OCELOT_P(p, f0, f1, f2) \ static struct ocelot_pin_caps ocelot_pin_##p = { \ .pin = p, \ @@ -959,6 +1041,15 @@ static struct pinctrl_desc luton_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc serval_desc = { + .name = "serval-pinctrl", + .pins = serval_pins, + .npins = ARRAY_SIZE(serval_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + static struct pinctrl_desc ocelot_desc = { .name = "ocelot-pinctrl", .pins = ocelot_pins, @@ -1243,6 +1334,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, + { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, From c82d4776a1ddf8cb16b7683ad1fe6844bf396ac8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 9 Nov 2020 11:56:19 +0530 Subject: [PATCH 25/80] dt-bindings: pinctrl: qcom: Add SDX55 pinctrl bindings Add device tree binding Documentation details for Qualcomm SDX55 pinctrl driver. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201109062620.14566-2-vkoul@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml new file mode 100644 index 000000000000..112dd59ce7ed --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX55 TLMM block + +maintainers: + - Vinod Koul + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SDX55 platform. + +properties: + compatible: + const: qcom,sdx55-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, + blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1, + emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update, + mgpi_clk, m_voc, native_char, native_char0, native_char1, + native_char2, native_char3, native_tsens, native_tsense, + nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref, + pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, + qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2, + qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7, + qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12, + qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17, + qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22, + qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27, + qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en, + qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss, + spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data, + uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, + uim2_reset, usb2phy_ac, vsense_trigger ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@1f00000 { + compatible = "qcom,sdx55-pinctrl"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 108>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + serial-pins { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <8>; + bias-disable; + }; + }; + +... From ac43c44a7a375ae0f0e96e10e227e226f2f2cb70 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Mon, 9 Nov 2020 11:56:20 +0530 Subject: [PATCH 26/80] pinctrl: qcom: Add SDX55 pincontrol driver Add initial Qualcomm SDX55 pinctrl driver to support pin configuration with pinctrl framework for SDX55 SoC. [ported from downstream and tidy up] Signed-off-by: Jeevan Shriram Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20201109062620.14566-3-vkoul@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdx55.c | 1018 ++++++++++++++++++++++++++ 3 files changed, 1028 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sdx55.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 03f1635a4b7e..8bdf878fe970 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -229,6 +229,15 @@ config PINCTRL_SDM845 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM845 platform. +config PINCTRL_SDX55 + tristate "Qualcomm Technologies Inc SDX55 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDX55 platform. + config PINCTRL_SM8150 tristate "Qualcomm Technologies Inc SM8150 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 5072e66fd3ab..891c422672a4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -27,5 +27,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c new file mode 100644 index 000000000000..2b5b0e2b03ad --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -0,0 +1,1018 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdx55_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "SDC1_RCLK"), + PINCTRL_PIN(109, "SDC1_CLK"), + PINCTRL_PIN(110, "SDC1_CMD"), + PINCTRL_PIN(111, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); + +static const unsigned int sdc1_rclk_pins[] = { 108 }; +static const unsigned int sdc1_clk_pins[] = { 109 }; +static const unsigned int sdc1_cmd_pins[] = { 110 }; +static const unsigned int sdc1_data_pins[] = { 111 }; + +enum sdx55_functions { + msm_mux_adsp_ext, + msm_mux_atest, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_char_exec, + msm_mux_coex_uart, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_emac_gcc0, + msm_mux_emac_gcc1, + msm_mux_emac_pps0, + msm_mux_emac_pps1, + msm_mux_ext_dbg, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_plltest, + msm_mux_gpio, + msm_mux_i2s_mclk, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_mgpi_clk, + msm_mux_m_voc, + msm_mux_native_char, + msm_mux_native_char0, + msm_mux_native_char1, + msm_mux_native_char2, + msm_mux_native_char3, + msm_mux_native_tsens, + msm_mux_native_tsense, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pcie_clkreq, + msm_mux_pci_e, + msm_mux_pll_bist, + msm_mux_pll_ref, + msm_mux_pll_test, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qdss_stm, + msm_mux_qlink0_en, + msm_mux_qlink0_req, + msm_mux_qlink0_wmss, + msm_mux_qlink1_en, + msm_mux_qlink1_req, + msm_mux_qlink1_wmss, + msm_mux_spmi_coex, + msm_mux_sec_mi2s, + msm_mux_spmi_vgi, + msm_mux_tgu_ch0, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio52", "gpio53", "gpio53", "gpio54", + "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", + "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", + "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", +}; + +static const char * const qdss_stm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19" "gpio20", "gpio21", "gpio22", + "gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62", + "gpio63", "gpio64", "gpio65", "gpio66", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio45", "gpio46", +}; + +static const char * const m_voc_groups[] = { + "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", +}; + +static const char * const ddr_bist_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const blsp_spi1_groups[] = { + "gpio52", "gpio62", "gpio71", "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char * const pci_e_groups[] = { + "gpio53", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio55", +}; + +static const char * const pcie_clkreq_groups[] = { + "gpio56", +}; + +static const char * const mgpi_clk_groups[] = { + "gpio61", "gpio71", +}; + +static const char * const i2s_mclk_groups[] = { + "gpio62", +}; + +static const char * const audio_ref_groups[] = { + "gpio62", +}; + +static const char * const ldo_update_groups[] = { + "gpio62", +}; + +static const char * const atest_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const uim1_data_groups[] = { + "gpio67", +}; + +static const char * const uim1_present_groups[] = { + "gpio68", +}; + +static const char * const uim1_reset_groups[] = { + "gpio69", +}; + +static const char * const uim1_clk_groups[] = { + "gpio70", +}; + +static const char * const qlink1_en_groups[] = { + "gpio72", +}; + +static const char * const qlink1_req_groups[] = { + "gpio73", +}; + +static const char * const qlink1_wmss_groups[] = { + "gpio74", +}; + +static const char * const coex_uart2_groups[] = { + "gpio75", "gpio76", +}; + +static const char * const spmi_vgi_groups[] = { + "gpio78", "gpio79", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio81", "gpio82", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio93", +}; + +static const char * const emac_pps1_groups[] = { + "gpio95", +}; + +static const char * const emac_pps0_groups[] = { + "gpio106", +}; + +static const char * const uim2_data_groups[] = { + "gpio0", +}; + +static const char * const ebi0_wrcdc_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const uim2_present_groups[] = { + "gpio1", +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio22", + "gpio23", +}; + +static const char * const uim2_reset_groups[] = { + "gpio2", +}; + +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", "gpio82", "gpio83", +}; + +static const char * const uim2_clk_groups[] = { + "gpio3", +}; + +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio52", "gpio62", "gpio71", +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", + "gpio66", +}; + +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", "gpio65", "gpio66", +}; + +static const char * const char_exec_groups[] = { + "gpio6", "gpio7", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", +}; + +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio52", "gpio62", "gpio71", +}; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const ext_dbg_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const ldo_en_groups[] = { + "gpio8", +}; + +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio11", +}; + +static const char * const emac_gcc1_groups[] = { + "gpio14", +}; + +static const char * const bimc_dte0_groups[] = { + "gpio14", "gpio59", +}; + +static const char * const native_tsens_groups[] = { + "gpio14", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio14", +}; + +static const char * const emac_gcc0_groups[] = { + "gpio15", +}; + +static const char * const bimc_dte1_groups[] = { + "gpio15", "gpio61", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", +}; + +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio52", "gpio62", "gpio71", +}; + +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", +}; + +static const char * const qdss_cti_groups[] = { + "gpio16", "gpio16", "gpio17", "gpio17", "gpio22", "gpio22", "gpio23", + "gpio23", "gpio54", "gpio54", "gpio55", "gpio55", "gpio59", "gpio60", + "gpio94", "gpio94", "gpio95", "gpio95", +}; + +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", "gpio78", "gpio79", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio18", +}; + +static const char * const jitter_bist_groups[] = { + "gpio19", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio19", +}; + +static const char * const ebi2_a_groups[] = { + "gpio20", +}; + +static const char * const ebi2_lcd_groups[] = { + "gpio21", "gpio22", "gpio23", +}; + +static const char * const pll_bist_groups[] = { + "gpio22", +}; + +static const char * const adsp_ext_groups[] = { + "gpio24", "gpio25", +}; + +static const char * const native_char_groups[] = { + "gpio26", +}; + +static const char * const qlink0_wmss_groups[] = { + "gpio28", +}; + +static const char * const native_char3_groups[] = { + "gpio28", +}; + +static const char * const native_char2_groups[] = { + "gpio29", +}; + +static const char * const native_tsense_groups[] = { + "gpio29", +}; + +static const char * const nav_gpio_groups[] = { + "gpio31", "gpio32", "gpio76", +}; + +static const char * const pll_ref_groups[] = { + "gpio32", +}; + +static const char * const pa_indicator_groups[] = { + "gpio33", +}; + +static const char * const native_char0_groups[] = { + "gpio33", +}; + +static const char * const qlink0_en_groups[] = { + "gpio34", +}; + +static const char * const qlink0_req_groups[] = { + "gpio35", +}; + +static const char * const pll_test_groups[] = { + "gpio35", +}; + +static const char * const cri_trng_groups[] = { + "gpio36", +}; + +static const char * const dbg_out_groups[] = { + "gpio36", +}; + +static const char * const prng_rosc_groups[] = { + "gpio38", +}; + +static const char * const cri_trng0_groups[] = { + "gpio40", +}; + +static const char * const cri_trng1_groups[] = { + "gpio41", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio42", "gpio61", "gpio63", "gpio64", "gpio65", "gpio66", +}; + +static const char * const native_char1_groups[] = { + "gpio42", +}; + +static const char * const coex_uart_groups[] = { + "gpio44", "gpio45", +}; + +static const char * const spmi_coex_groups[] = { + "gpio44", "gpio45", +}; + +static const struct msm_function sdx55_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(atest), + FUNCTION(audio_ref), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(char_exec), + FUNCTION(coex_uart), + FUNCTION(coex_uart2), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ebi0_wrcdc), + FUNCTION(ebi2_a), + FUNCTION(ebi2_lcd), + FUNCTION(emac_gcc0), + FUNCTION(emac_gcc1), + FUNCTION(emac_pps0), + FUNCTION(emac_pps1), + FUNCTION(ext_dbg), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_plltest), + FUNCTION(gpio), + FUNCTION(i2s_mclk), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(mgpi_clk), + FUNCTION(m_voc), + FUNCTION(native_char), + FUNCTION(native_char0), + FUNCTION(native_char1), + FUNCTION(native_char2), + FUNCTION(native_char3), + FUNCTION(native_tsens), + FUNCTION(native_tsense), + FUNCTION(nav_gpio), + FUNCTION(pa_indicator), + FUNCTION(pcie_clkreq), + FUNCTION(pci_e), + FUNCTION(pll_bist), + FUNCTION(pll_ref), + FUNCTION(pll_test), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qdss_stm), + FUNCTION(qlink0_en), + FUNCTION(qlink0_req), + FUNCTION(qlink0_wmss), + FUNCTION(qlink1_en), + FUNCTION(qlink1_req), + FUNCTION(qlink1_wmss), + FUNCTION(spmi_coex), + FUNCTION(sec_mi2s), + FUNCTION(spmi_vgi), + FUNCTION(tgu_ch0), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(usb2phy_ac), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdx55_groups[] = { + [0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _), + [1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _), + [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _), + [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _), + [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), + [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), + [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), + [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), + [8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _), + [9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _), + [10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _), + [11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _), + [12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), + [13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), + [14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger), + [15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _), + [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio), + [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _), + [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _), + [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio), + [20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _), + [21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _), + [22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm), + [23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _), + [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), + [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _), + [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), + [33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _), + [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _), + [36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _), + [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), + [42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _), + [45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _), + [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _), + [49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _), + [53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _), + [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _), + [57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), + [61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _), + [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _), + [63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _), + [64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _), + [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _), + [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _), + [67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _), + [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), + [72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), + [79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), + [80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _), + [81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _), + [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), + [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), + [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), + [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), + [110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + [111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + [112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sdx55_pinctrl = { + .pins = sdx55_pins, + .npins = ARRAY_SIZE(sdx55_pins), + .functions = sdx55_functions, + .nfunctions = ARRAY_SIZE(sdx55_functions), + .groups = sdx55_groups, + .ngroups = ARRAY_SIZE(sdx55_groups), + .ngpios = 108, +}; + +static int sdx55_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdx55_pinctrl); +} + +static const struct of_device_id sdx55_pinctrl_of_match[] = { + { .compatible = "qcom,sdx55-pinctrl", }, + { }, +}; + +static struct platform_driver sdx55_pinctrl_driver = { + .driver = { + .name = "sdx55-pinctrl", + .of_match_table = sdx55_pinctrl_of_match, + }, + .probe = sdx55_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdx55_pinctrl_init(void) +{ + return platform_driver_register(&sdx55_pinctrl_driver); +} +arch_initcall(sdx55_pinctrl_init); + +static void __exit sdx55_pinctrl_exit(void) +{ + platform_driver_unregister(&sdx55_pinctrl_driver); +} +module_exit(sdx55_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdx55 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); From a4872f905b71e180f2b19bf646b25b732169de61 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 11 Nov 2020 00:23:30 +0100 Subject: [PATCH 27/80] pinctrl: nomadik: db8500: Add more detailed LCD groups We need a more granular distribution among funcion A and function B for the LCD pins for the Samsung GT-I9070. Provide some new pin groups so we can configure this phone properly. Link: https://lore.kernel.org/r/20201110232330.2242167-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c index acad3887cc74..0b9b6cbfd10c 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c @@ -421,6 +421,8 @@ static const unsigned lcd_d0_d7_a_1_pins[] = { /* D8 thru D11 often used as TVOUT lines */ static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 }; +static const unsigned lcd_d12_d15_a_1_pins[] = { + DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; static const unsigned lcd_d12_d23_a_1_pins[] = { DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5, DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6, @@ -535,6 +537,9 @@ static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; +static const unsigned lcd_d16_d23_b_1_pins[] = { + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 }; static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 }; static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13, @@ -689,6 +694,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d12_d15_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A), @@ -741,6 +747,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B), DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B), DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcd_d16_d23_b_1, NMK_GPIO_ALT_B), DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), @@ -846,7 +853,8 @@ DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_a_2", "mc0_dat47_a_1", "mc0dat31dir_a_1" DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", - "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); + "lcd_d8_d11_a_1", "lcd_d12_d15_a_1", "lcd_d12_d23_a_1", "lcd_b_1", + "lcd_d16_d23_b_1"); DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_a_2", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1"); DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); From 80f1803dbc0506c5d192ef4df4e851690ca68114 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 11 Nov 2020 10:06:10 +0530 Subject: [PATCH 28/80] pinctrl: qcom: sdx55: update kconfig dependency Commit be117ca32261 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a dependency rather then a selected config") moved the qcom pinctrl drivers to have PINCTRL_MSM as dependency rather then a selected config, so do this change for SDX55 pinctrl driver as well. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201111043610.177168-1-vkoul@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 8bdf878fe970..dcc046a921cc 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -232,7 +232,7 @@ config PINCTRL_SDM845 config PINCTRL_SDX55 tristate "Qualcomm Technologies Inc SDX55 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm From 3603a537bf791d4047b89fd0fc060f723eded458 Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Sun, 8 Nov 2020 19:01:44 +0100 Subject: [PATCH 29/80] pinctrl: pinctrl-at91-pio4: Set irq handler and data in one go Replace the two separate calls for setting the irq handler and data with a single irq_set_chained_handler_and_data() call. Signed-off-by: Martin Kaiser Link: https://lore.kernel.org/r/20201108180144.28594-1-martin@kaiser.cx Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 578b387100d9..157fea808629 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1127,8 +1127,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) return -EINVAL; } atmel_pioctrl->irqs[i] = res->start; - irq_set_chained_handler(res->start, atmel_gpio_irq_handler); - irq_set_handler_data(res->start, atmel_pioctrl); + irq_set_chained_handler_and_data(res->start, + atmel_gpio_irq_handler, atmel_pioctrl); dev_dbg(dev, "bank %i: irq=%pr\n", i, res); } From d25dd66ae732f7752760d8f9306ba495de9dee8e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 11 Nov 2020 13:34:31 +0200 Subject: [PATCH 30/80] pinctrl: lynxpoint: Use defined constant for disabled bias explicitly We have a specific constant to describe a disabled bias, i.e. GPIWP_NONE. Use it explicitly instead of making an assumption about its value. While at it, move argument assignment to the switch-case in lp_pin_config_get(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 849979d5d646..2e9670fc479a 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -496,7 +496,7 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param = pinconf_to_config_param(*config); unsigned long flags; u32 value, pull; - u16 arg = 0; + u16 arg; raw_spin_lock_irqsave(&lg->lock, flags); value = ioread32(conf2); @@ -506,8 +506,9 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (pull) + if (pull != GPIWP_NONE) return -EINVAL; + arg = 0; break; case PIN_CONFIG_BIAS_PULL_DOWN: if (pull != GPIWP_DOWN) @@ -550,6 +551,7 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: value &= ~GPIWP_MASK; + value |= GPIWP_NONE; break; case PIN_CONFIG_BIAS_PULL_DOWN: value &= ~GPIWP_MASK; From 1d112baae84844f3737193c39ac5069f5980ecd1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 11 Nov 2020 13:34:32 +0200 Subject: [PATCH 31/80] pinctrl: lynxpoint: Enable pin configuration setting for GPIO chip It appears that pin configuration for GPIO chip hasn't been enabled yet due to absence of ->set_config() callback. Enable it here for Intel Lynxpoint PCH. Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 2e9670fc479a..0a48ca46ab59 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -874,6 +874,7 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->direction_output = lp_gpio_direction_output; gc->get = lp_gpio_get; gc->set = lp_gpio_set; + gc->set_config = gpiochip_generic_config; gc->get_direction = lp_gpio_get_direction; gc->base = -1; gc->ngpio = LP_NUM_GPIO; From bf8b7e689de22f862c4b066ff73d8267e04905e2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 10 Nov 2020 21:59:23 +0200 Subject: [PATCH 32/80] pinctrl: jasperlake: Unhide SPI group of pins If the group of pins is hidden in the pin list it affects the register offset calculation despite fixed GPIO base. Hence, the offsets of all pins after the hidden group are broken. Instead we have to unhide the group and use a flag to exclude it from GPIO number space. Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Reported-by: Divagar Mohandass Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-jasperlake.c | 450 +++++++++++---------- 1 file changed, 230 insertions(+), 220 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index 9bd0e8e6310c..c5e204c8da9c 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -65,252 +65,263 @@ static const struct pinctrl_pin_desc jsl_pins[] = { PINCTRL_PIN(17, "EMMC_CLK"), PINCTRL_PIN(18, "EMMC_RESETB"), PINCTRL_PIN(19, "A4WP_PRESENT"), + /* SPI */ + PINCTRL_PIN(20, "SPI0_IO_2"), + PINCTRL_PIN(21, "SPI0_IO_3"), + PINCTRL_PIN(22, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(23, "SPI0_MISO_IO_1"), + PINCTRL_PIN(24, "SPI0_TPM_CSB"), + PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(27, "SPI0_CLK"), + PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"), /* GPP_B */ - PINCTRL_PIN(20, "CORE_VID_0"), - PINCTRL_PIN(21, "CORE_VID_1"), - PINCTRL_PIN(22, "VRALERTB"), - PINCTRL_PIN(23, "CPU_GP_2"), - PINCTRL_PIN(24, "CPU_GP_3"), - PINCTRL_PIN(25, "SRCCLKREQB_0"), - PINCTRL_PIN(26, "SRCCLKREQB_1"), - PINCTRL_PIN(27, "SRCCLKREQB_2"), - PINCTRL_PIN(28, "SRCCLKREQB_3"), - PINCTRL_PIN(29, "SRCCLKREQB_4"), - PINCTRL_PIN(30, "SRCCLKREQB_5"), - PINCTRL_PIN(31, "PMCALERTB"), - PINCTRL_PIN(32, "SLP_S0B"), - PINCTRL_PIN(33, "PLTRSTB"), - PINCTRL_PIN(34, "SPKR"), - PINCTRL_PIN(35, "GSPI0_CS0B"), - PINCTRL_PIN(36, "GSPI0_CLK"), - PINCTRL_PIN(37, "GSPI0_MISO"), - PINCTRL_PIN(38, "GSPI0_MOSI"), - PINCTRL_PIN(39, "GSPI1_CS0B"), - PINCTRL_PIN(40, "GSPI1_CLK"), - PINCTRL_PIN(41, "GSPI1_MISO"), - PINCTRL_PIN(42, "GSPI1_MOSI"), - PINCTRL_PIN(43, "DDSP_HPD_A"), - PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"), - PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"), + PINCTRL_PIN(29, "CORE_VID_0"), + PINCTRL_PIN(30, "CORE_VID_1"), + PINCTRL_PIN(31, "VRALERTB"), + PINCTRL_PIN(32, "CPU_GP_2"), + PINCTRL_PIN(33, "CPU_GP_3"), + PINCTRL_PIN(34, "SRCCLKREQB_0"), + PINCTRL_PIN(35, "SRCCLKREQB_1"), + PINCTRL_PIN(36, "SRCCLKREQB_2"), + PINCTRL_PIN(37, "SRCCLKREQB_3"), + PINCTRL_PIN(38, "SRCCLKREQB_4"), + PINCTRL_PIN(39, "SRCCLKREQB_5"), + PINCTRL_PIN(40, "PMCALERTB"), + PINCTRL_PIN(41, "SLP_S0B"), + PINCTRL_PIN(42, "PLTRSTB"), + PINCTRL_PIN(43, "SPKR"), + PINCTRL_PIN(44, "GSPI0_CS0B"), + PINCTRL_PIN(45, "GSPI0_CLK"), + PINCTRL_PIN(46, "GSPI0_MISO"), + PINCTRL_PIN(47, "GSPI0_MOSI"), + PINCTRL_PIN(48, "GSPI1_CS0B"), + PINCTRL_PIN(49, "GSPI1_CLK"), + PINCTRL_PIN(50, "GSPI1_MISO"), + PINCTRL_PIN(51, "GSPI1_MOSI"), + PINCTRL_PIN(52, "DDSP_HPD_A"), + PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"), /* GPP_A */ - PINCTRL_PIN(46, "ESPI_IO_0"), - PINCTRL_PIN(47, "ESPI_IO_1"), - PINCTRL_PIN(48, "ESPI_IO_2"), - PINCTRL_PIN(49, "ESPI_IO_3"), - PINCTRL_PIN(50, "ESPI_CSB"), - PINCTRL_PIN(51, "ESPI_CLK"), - PINCTRL_PIN(52, "ESPI_RESETB"), - PINCTRL_PIN(53, "SMBCLK"), - PINCTRL_PIN(54, "SMBDATA"), - PINCTRL_PIN(55, "SMBALERTB"), - PINCTRL_PIN(56, "CPU_GP_0"), - PINCTRL_PIN(57, "CPU_GP_1"), - PINCTRL_PIN(58, "USB2_OCB_1"), - PINCTRL_PIN(59, "USB2_OCB_2"), - PINCTRL_PIN(60, "USB2_OCB_3"), - PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"), - PINCTRL_PIN(62, "DDSP_HPD_B"), - PINCTRL_PIN(63, "DDSP_HPD_C"), - PINCTRL_PIN(64, "USB2_OCB_0"), - PINCTRL_PIN(65, "PCHHOTB"), - PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + PINCTRL_PIN(55, "ESPI_IO_0"), + PINCTRL_PIN(56, "ESPI_IO_1"), + PINCTRL_PIN(57, "ESPI_IO_2"), + PINCTRL_PIN(58, "ESPI_IO_3"), + PINCTRL_PIN(59, "ESPI_CSB"), + PINCTRL_PIN(60, "ESPI_CLK"), + PINCTRL_PIN(61, "ESPI_RESETB"), + PINCTRL_PIN(62, "SMBCLK"), + PINCTRL_PIN(63, "SMBDATA"), + PINCTRL_PIN(64, "SMBALERTB"), + PINCTRL_PIN(65, "CPU_GP_0"), + PINCTRL_PIN(66, "CPU_GP_1"), + PINCTRL_PIN(67, "USB2_OCB_1"), + PINCTRL_PIN(68, "USB2_OCB_2"), + PINCTRL_PIN(69, "USB2_OCB_3"), + PINCTRL_PIN(70, "DDSP_HPD_A_TIME_SYNC_0"), + PINCTRL_PIN(71, "DDSP_HPD_B"), + PINCTRL_PIN(72, "DDSP_HPD_C"), + PINCTRL_PIN(73, "USB2_OCB_0"), + PINCTRL_PIN(74, "PCHHOTB"), + PINCTRL_PIN(75, "ESPI_CLK_LOOPBK"), /* GPP_S */ - PINCTRL_PIN(67, "SNDW1_CLK"), - PINCTRL_PIN(68, "SNDW1_DATA"), - PINCTRL_PIN(69, "SNDW2_CLK"), - PINCTRL_PIN(70, "SNDW2_DATA"), - PINCTRL_PIN(71, "SNDW1_CLK"), - PINCTRL_PIN(72, "SNDW1_DATA"), - PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"), - PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"), + PINCTRL_PIN(76, "SNDW1_CLK"), + PINCTRL_PIN(77, "SNDW1_DATA"), + PINCTRL_PIN(78, "SNDW2_CLK"), + PINCTRL_PIN(79, "SNDW2_DATA"), + PINCTRL_PIN(80, "SNDW1_CLK"), + PINCTRL_PIN(81, "SNDW1_DATA"), + PINCTRL_PIN(82, "SNDW4_CLK_DMIC_CLK_0"), + PINCTRL_PIN(83, "SNDW4_DATA_DMIC_DATA_0"), /* GPP_R */ - PINCTRL_PIN(75, "HDA_BCLK"), - PINCTRL_PIN(76, "HDA_SYNC"), - PINCTRL_PIN(77, "HDA_SDO"), - PINCTRL_PIN(78, "HDA_SDI_0"), - PINCTRL_PIN(79, "HDA_RSTB"), - PINCTRL_PIN(80, "HDA_SDI_1"), - PINCTRL_PIN(81, "I2S1_SFRM"), - PINCTRL_PIN(82, "I2S1_TXD"), + PINCTRL_PIN(84, "HDA_BCLK"), + PINCTRL_PIN(85, "HDA_SYNC"), + PINCTRL_PIN(86, "HDA_SDO"), + PINCTRL_PIN(87, "HDA_SDI_0"), + PINCTRL_PIN(88, "HDA_RSTB"), + PINCTRL_PIN(89, "HDA_SDI_1"), + PINCTRL_PIN(90, "I2S1_SFRM"), + PINCTRL_PIN(91, "I2S1_TXD"), /* GPP_H */ - PINCTRL_PIN(83, "GPPC_H_0"), - PINCTRL_PIN(84, "SD_PWR_EN_B"), - PINCTRL_PIN(85, "MODEM_CLKREQ"), - PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"), - PINCTRL_PIN(87, "I2C2_SDA"), - PINCTRL_PIN(88, "I2C2_SCL"), - PINCTRL_PIN(89, "I2C3_SDA"), - PINCTRL_PIN(90, "I2C3_SCL"), - PINCTRL_PIN(91, "I2C4_SDA"), - PINCTRL_PIN(92, "I2C4_SCL"), - PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"), - PINCTRL_PIN(94, "I2S2_SCLK"), - PINCTRL_PIN(95, "I2S2_SFRM"), - PINCTRL_PIN(96, "I2S2_TXD"), - PINCTRL_PIN(97, "I2S2_RXD"), - PINCTRL_PIN(98, "I2S1_SCLK"), - PINCTRL_PIN(99, "GPPC_H_16"), - PINCTRL_PIN(100, "GPPC_H_17"), - PINCTRL_PIN(101, "GPPC_H_18"), - PINCTRL_PIN(102, "GPPC_H_19"), - PINCTRL_PIN(103, "GPPC_H_20"), - PINCTRL_PIN(104, "GPPC_H_21"), - PINCTRL_PIN(105, "GPPC_H_22"), - PINCTRL_PIN(106, "GPPC_H_23"), + PINCTRL_PIN(92, "GPPC_H_0"), + PINCTRL_PIN(93, "SD_PWR_EN_B"), + PINCTRL_PIN(94, "MODEM_CLKREQ"), + PINCTRL_PIN(95, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(96, "I2C2_SDA"), + PINCTRL_PIN(97, "I2C2_SCL"), + PINCTRL_PIN(98, "I2C3_SDA"), + PINCTRL_PIN(99, "I2C3_SCL"), + PINCTRL_PIN(100, "I2C4_SDA"), + PINCTRL_PIN(101, "I2C4_SCL"), + PINCTRL_PIN(102, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(103, "I2S2_SCLK"), + PINCTRL_PIN(104, "I2S2_SFRM"), + PINCTRL_PIN(105, "I2S2_TXD"), + PINCTRL_PIN(106, "I2S2_RXD"), + PINCTRL_PIN(107, "I2S1_SCLK"), + PINCTRL_PIN(108, "GPPC_H_16"), + PINCTRL_PIN(109, "GPPC_H_17"), + PINCTRL_PIN(110, "GPPC_H_18"), + PINCTRL_PIN(111, "GPPC_H_19"), + PINCTRL_PIN(112, "GPPC_H_20"), + PINCTRL_PIN(113, "GPPC_H_21"), + PINCTRL_PIN(114, "GPPC_H_22"), + PINCTRL_PIN(115, "GPPC_H_23"), /* GPP_D */ - PINCTRL_PIN(107, "SPI1_CSB"), - PINCTRL_PIN(108, "SPI1_CLK"), - PINCTRL_PIN(109, "SPI1_MISO_IO_1"), - PINCTRL_PIN(110, "SPI1_MOSI_IO_0"), - PINCTRL_PIN(111, "ISH_I2C0_SDA"), - PINCTRL_PIN(112, "ISH_I2C0_SCL"), - PINCTRL_PIN(113, "ISH_I2C1_SDA"), - PINCTRL_PIN(114, "ISH_I2C1_SCL"), - PINCTRL_PIN(115, "ISH_SPI_CSB"), - PINCTRL_PIN(116, "ISH_SPI_CLK"), - PINCTRL_PIN(117, "ISH_SPI_MISO"), - PINCTRL_PIN(118, "ISH_SPI_MOSI"), - PINCTRL_PIN(119, "ISH_UART0_RXD"), - PINCTRL_PIN(120, "ISH_UART0_TXD"), - PINCTRL_PIN(121, "ISH_UART0_RTSB"), - PINCTRL_PIN(122, "ISH_UART0_CTSB"), - PINCTRL_PIN(123, "SPI1_IO_2"), - PINCTRL_PIN(124, "SPI1_IO_3"), - PINCTRL_PIN(125, "I2S_MCLK"), - PINCTRL_PIN(126, "CNV_MFUART2_RXD"), - PINCTRL_PIN(127, "CNV_MFUART2_TXD"), - PINCTRL_PIN(128, "CNV_PA_BLANKING"), - PINCTRL_PIN(129, "I2C5_SDA"), - PINCTRL_PIN(130, "I2C5_SCL"), - PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"), - PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"), + PINCTRL_PIN(116, "SPI1_CSB"), + PINCTRL_PIN(117, "SPI1_CLK"), + PINCTRL_PIN(118, "SPI1_MISO_IO_1"), + PINCTRL_PIN(119, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(120, "ISH_I2C0_SDA"), + PINCTRL_PIN(121, "ISH_I2C0_SCL"), + PINCTRL_PIN(122, "ISH_I2C1_SDA"), + PINCTRL_PIN(123, "ISH_I2C1_SCL"), + PINCTRL_PIN(124, "ISH_SPI_CSB"), + PINCTRL_PIN(125, "ISH_SPI_CLK"), + PINCTRL_PIN(126, "ISH_SPI_MISO"), + PINCTRL_PIN(127, "ISH_SPI_MOSI"), + PINCTRL_PIN(128, "ISH_UART0_RXD"), + PINCTRL_PIN(129, "ISH_UART0_TXD"), + PINCTRL_PIN(130, "ISH_UART0_RTSB"), + PINCTRL_PIN(131, "ISH_UART0_CTSB"), + PINCTRL_PIN(132, "SPI1_IO_2"), + PINCTRL_PIN(133, "SPI1_IO_3"), + PINCTRL_PIN(134, "I2S_MCLK"), + PINCTRL_PIN(135, "CNV_MFUART2_RXD"), + PINCTRL_PIN(136, "CNV_MFUART2_TXD"), + PINCTRL_PIN(137, "CNV_PA_BLANKING"), + PINCTRL_PIN(138, "I2C5_SDA"), + PINCTRL_PIN(139, "I2C5_SCL"), + PINCTRL_PIN(140, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(141, "SPI1_CLK_LOOPBK"), /* vGPIO */ - PINCTRL_PIN(133, "CNV_BTEN"), - PINCTRL_PIN(134, "CNV_WCEN"), - PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"), - PINCTRL_PIN(136, "CNV_BT_IF_SELECT"), - PINCTRL_PIN(137, "vCNV_BT_UART_TXD"), - PINCTRL_PIN(138, "vCNV_BT_UART_RXD"), - PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"), - PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"), - PINCTRL_PIN(141, "vCNV_MFUART1_TXD"), - PINCTRL_PIN(142, "vCNV_MFUART1_RXD"), - PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"), - PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"), - PINCTRL_PIN(145, "vUART0_TXD"), - PINCTRL_PIN(146, "vUART0_RXD"), - PINCTRL_PIN(147, "vUART0_CTS_B"), - PINCTRL_PIN(148, "vUART0_RTS_B"), - PINCTRL_PIN(149, "vISH_UART0_TXD"), - PINCTRL_PIN(150, "vISH_UART0_RXD"), - PINCTRL_PIN(151, "vISH_UART0_CTS_B"), - PINCTRL_PIN(152, "vISH_UART0_RTS_B"), - PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"), - PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"), - PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"), - PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"), - PINCTRL_PIN(157, "vI2S2_SCLK"), - PINCTRL_PIN(158, "vI2S2_SFRM"), - PINCTRL_PIN(159, "vI2S2_TXD"), - PINCTRL_PIN(160, "vI2S2_RXD"), - PINCTRL_PIN(161, "vSD3_CD_B"), + PINCTRL_PIN(142, "CNV_BTEN"), + PINCTRL_PIN(143, "CNV_WCEN"), + PINCTRL_PIN(144, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(145, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(146, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(147, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(148, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(149, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(150, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(151, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(152, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(153, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(154, "vUART0_TXD"), + PINCTRL_PIN(155, "vUART0_RXD"), + PINCTRL_PIN(156, "vUART0_CTS_B"), + PINCTRL_PIN(157, "vUART0_RTS_B"), + PINCTRL_PIN(158, "vISH_UART0_TXD"), + PINCTRL_PIN(159, "vISH_UART0_RXD"), + PINCTRL_PIN(160, "vISH_UART0_CTS_B"), + PINCTRL_PIN(161, "vISH_UART0_RTS_B"), + PINCTRL_PIN(162, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(163, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(164, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(165, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(166, "vI2S2_SCLK"), + PINCTRL_PIN(167, "vI2S2_SFRM"), + PINCTRL_PIN(168, "vI2S2_TXD"), + PINCTRL_PIN(169, "vI2S2_RXD"), + PINCTRL_PIN(170, "vSD3_CD_B"), /* GPP_C */ - PINCTRL_PIN(162, "GPPC_C_0"), - PINCTRL_PIN(163, "GPPC_C_1"), - PINCTRL_PIN(164, "GPPC_C_2"), - PINCTRL_PIN(165, "GPPC_C_3"), - PINCTRL_PIN(166, "GPPC_C_4"), - PINCTRL_PIN(167, "GPPC_C_5"), - PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"), - PINCTRL_PIN(169, "SUSACKB"), - PINCTRL_PIN(170, "UART0_RXD"), - PINCTRL_PIN(171, "UART0_TXD"), - PINCTRL_PIN(172, "UART0_RTSB"), - PINCTRL_PIN(173, "UART0_CTSB"), - PINCTRL_PIN(174, "UART1_RXD"), - PINCTRL_PIN(175, "UART1_TXD"), - PINCTRL_PIN(176, "UART1_RTSB"), - PINCTRL_PIN(177, "UART1_CTSB"), - PINCTRL_PIN(178, "I2C0_SDA"), - PINCTRL_PIN(179, "I2C0_SCL"), - PINCTRL_PIN(180, "I2C1_SDA"), - PINCTRL_PIN(181, "I2C1_SCL"), - PINCTRL_PIN(182, "UART2_RXD"), - PINCTRL_PIN(183, "UART2_TXD"), - PINCTRL_PIN(184, "UART2_RTSB"), - PINCTRL_PIN(185, "UART2_CTSB"), + PINCTRL_PIN(171, "GPPC_C_0"), + PINCTRL_PIN(172, "GPPC_C_1"), + PINCTRL_PIN(173, "GPPC_C_2"), + PINCTRL_PIN(174, "GPPC_C_3"), + PINCTRL_PIN(175, "GPPC_C_4"), + PINCTRL_PIN(176, "GPPC_C_5"), + PINCTRL_PIN(177, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(178, "SUSACKB"), + PINCTRL_PIN(179, "UART0_RXD"), + PINCTRL_PIN(180, "UART0_TXD"), + PINCTRL_PIN(181, "UART0_RTSB"), + PINCTRL_PIN(182, "UART0_CTSB"), + PINCTRL_PIN(183, "UART1_RXD"), + PINCTRL_PIN(184, "UART1_TXD"), + PINCTRL_PIN(185, "UART1_RTSB"), + PINCTRL_PIN(186, "UART1_CTSB"), + PINCTRL_PIN(187, "I2C0_SDA"), + PINCTRL_PIN(188, "I2C0_SCL"), + PINCTRL_PIN(189, "I2C1_SDA"), + PINCTRL_PIN(190, "I2C1_SCL"), + PINCTRL_PIN(191, "UART2_RXD"), + PINCTRL_PIN(192, "UART2_TXD"), + PINCTRL_PIN(193, "UART2_RTSB"), + PINCTRL_PIN(194, "UART2_CTSB"), /* HVCMOS */ - PINCTRL_PIN(186, "L_BKLTEN"), - PINCTRL_PIN(187, "L_BKLTCTL"), - PINCTRL_PIN(188, "L_VDDEN"), - PINCTRL_PIN(189, "SYS_PWROK"), - PINCTRL_PIN(190, "SYS_RESETB"), - PINCTRL_PIN(191, "MLK_RSTB"), + PINCTRL_PIN(195, "L_BKLTEN"), + PINCTRL_PIN(196, "L_BKLTCTL"), + PINCTRL_PIN(197, "L_VDDEN"), + PINCTRL_PIN(198, "SYS_PWROK"), + PINCTRL_PIN(199, "SYS_RESETB"), + PINCTRL_PIN(200, "MLK_RSTB"), /* GPP_E */ - PINCTRL_PIN(192, "ISH_GP_0"), - PINCTRL_PIN(193, "ISH_GP_1"), - PINCTRL_PIN(194, "IMGCLKOUT_1"), - PINCTRL_PIN(195, "ISH_GP_2"), - PINCTRL_PIN(196, "IMGCLKOUT_2"), - PINCTRL_PIN(197, "SATA_LEDB"), - PINCTRL_PIN(198, "IMGCLKOUT_3"), - PINCTRL_PIN(199, "ISH_GP_3"), - PINCTRL_PIN(200, "ISH_GP_4"), - PINCTRL_PIN(201, "ISH_GP_5"), - PINCTRL_PIN(202, "ISH_GP_6"), - PINCTRL_PIN(203, "ISH_GP_7"), - PINCTRL_PIN(204, "IMGCLKOUT_4"), - PINCTRL_PIN(205, "DDPA_CTRLCLK"), - PINCTRL_PIN(206, "DDPA_CTRLDATA"), - PINCTRL_PIN(207, "DDPB_CTRLCLK"), - PINCTRL_PIN(208, "DDPB_CTRLDATA"), - PINCTRL_PIN(209, "DDPC_CTRLCLK"), - PINCTRL_PIN(210, "DDPC_CTRLDATA"), - PINCTRL_PIN(211, "IMGCLKOUT_5"), - PINCTRL_PIN(212, "CNV_BRI_DT"), - PINCTRL_PIN(213, "CNV_BRI_RSP"), - PINCTRL_PIN(214, "CNV_RGI_DT"), - PINCTRL_PIN(215, "CNV_RGI_RSP"), + PINCTRL_PIN(201, "ISH_GP_0"), + PINCTRL_PIN(202, "ISH_GP_1"), + PINCTRL_PIN(203, "IMGCLKOUT_1"), + PINCTRL_PIN(204, "ISH_GP_2"), + PINCTRL_PIN(205, "IMGCLKOUT_2"), + PINCTRL_PIN(206, "SATA_LEDB"), + PINCTRL_PIN(207, "IMGCLKOUT_3"), + PINCTRL_PIN(208, "ISH_GP_3"), + PINCTRL_PIN(209, "ISH_GP_4"), + PINCTRL_PIN(210, "ISH_GP_5"), + PINCTRL_PIN(211, "ISH_GP_6"), + PINCTRL_PIN(212, "ISH_GP_7"), + PINCTRL_PIN(213, "IMGCLKOUT_4"), + PINCTRL_PIN(214, "DDPA_CTRLCLK"), + PINCTRL_PIN(215, "DDPA_CTRLDATA"), + PINCTRL_PIN(216, "DDPB_CTRLCLK"), + PINCTRL_PIN(217, "DDPB_CTRLDATA"), + PINCTRL_PIN(218, "DDPC_CTRLCLK"), + PINCTRL_PIN(219, "DDPC_CTRLDATA"), + PINCTRL_PIN(220, "IMGCLKOUT_5"), + PINCTRL_PIN(221, "CNV_BRI_DT"), + PINCTRL_PIN(222, "CNV_BRI_RSP"), + PINCTRL_PIN(223, "CNV_RGI_DT"), + PINCTRL_PIN(224, "CNV_RGI_RSP"), /* GPP_G */ - PINCTRL_PIN(216, "SD3_CMD"), - PINCTRL_PIN(217, "SD3_D0"), - PINCTRL_PIN(218, "SD3_D1"), - PINCTRL_PIN(219, "SD3_D2"), - PINCTRL_PIN(220, "SD3_D3"), - PINCTRL_PIN(221, "SD3_CDB"), - PINCTRL_PIN(222, "SD3_CLK"), - PINCTRL_PIN(223, "SD3_WP"), + PINCTRL_PIN(225, "SD3_CMD"), + PINCTRL_PIN(226, "SD3_D0"), + PINCTRL_PIN(227, "SD3_D1"), + PINCTRL_PIN(228, "SD3_D2"), + PINCTRL_PIN(229, "SD3_D3"), + PINCTRL_PIN(230, "SD3_CDB"), + PINCTRL_PIN(231, "SD3_CLK"), + PINCTRL_PIN(232, "SD3_WP"), }; static const struct intel_padgroup jsl_community0_gpps[] = { JSL_GPP(0, 0, 19, 320), /* GPP_F */ - JSL_GPP(1, 20, 45, 32), /* GPP_B */ - JSL_GPP(2, 46, 66, 64), /* GPP_A */ - JSL_GPP(3, 67, 74, 96), /* GPP_S */ - JSL_GPP(4, 75, 82, 128), /* GPP_R */ + JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */ + JSL_GPP(2, 29, 54, 32), /* GPP_B */ + JSL_GPP(3, 55, 75, 64), /* GPP_A */ + JSL_GPP(4, 76, 83, 96), /* GPP_S */ + JSL_GPP(5, 84, 91, 128), /* GPP_R */ }; static const struct intel_padgroup jsl_community1_gpps[] = { - JSL_GPP(0, 83, 106, 160), /* GPP_H */ - JSL_GPP(1, 107, 132, 192), /* GPP_D */ - JSL_GPP(2, 133, 161, 224), /* vGPIO */ - JSL_GPP(3, 162, 185, 256), /* GPP_C */ + JSL_GPP(0, 92, 115, 160), /* GPP_H */ + JSL_GPP(1, 116, 141, 192), /* GPP_D */ + JSL_GPP(2, 142, 170, 224), /* vGPIO */ + JSL_GPP(3, 171, 194, 256), /* GPP_C */ }; static const struct intel_padgroup jsl_community4_gpps[] = { - JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ - JSL_GPP(1, 192, 215, 288), /* GPP_E */ + JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + JSL_GPP(1, 201, 224, 288), /* GPP_E */ }; static const struct intel_padgroup jsl_community5_gpps[] = { - JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */ + JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */ }; static const struct intel_community jsl_communities[] = { - JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps), - JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps), - JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps), - JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps), + JSL_COMMUNITY(0, 0, 91, jsl_community0_gpps), + JSL_COMMUNITY(1, 92, 194, jsl_community1_gpps), + JSL_COMMUNITY(2, 195, 224, jsl_community4_gpps), + JSL_COMMUNITY(3, 225, 232, jsl_community5_gpps), }; static const struct intel_pinctrl_soc_data jsl_soc_data = { @@ -336,7 +347,6 @@ static struct platform_driver jsl_pinctrl_driver = { .pm = &jsl_pinctrl_pm_ops, }, }; - module_platform_driver(jsl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); From 5aa5541eca04a1c69a05bbb747164926bbf20de4 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Wed, 11 Nov 2020 15:17:28 -0800 Subject: [PATCH 33/80] pinctrl: jasperlake: Fix HOSTSW_OWN offset GPIOs that attempt to use interrupts get thwarted with a message like: "pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's owned by ACPI. Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Cc: stable@vger.kernel.org Signed-off-by: Evan Green Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-jasperlake.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index c5e204c8da9c..ec435b7ab392 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -16,7 +16,7 @@ #define JSL_PAD_OWN 0x020 #define JSL_PADCFGLOCK 0x080 -#define JSL_HOSTSW_OWN 0x0b0 +#define JSL_HOSTSW_OWN 0x0c0 #define JSL_GPI_IS 0x100 #define JSL_GPI_IE 0x120 From 0fa86fc2e28227f1e64f13867e73cf864c6d25ad Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 11 Nov 2020 14:06:05 +0200 Subject: [PATCH 34/80] pinctrl: merrifield: Set default bias in case no particular value given When GPIO library asks pin control to set the bias, it doesn't pass any value of it and argument is considered boolean (and this is true for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual drivers must behave well, when they got the resistance value of 1 Ohm, i.e. transforming it to sane default. In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible because it gives a good trade off between weakness and minimization of leakage current (will be only 50 uA with the above choice). Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-merrifield.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index e4ff8da1b894..3ae141e0b421 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -745,6 +745,10 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; bits |= BUFCFG_PU_EN; + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 20000; + switch (arg) { case 50000: bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; @@ -765,6 +769,10 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; bits |= BUFCFG_PD_EN; + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 20000; + switch (arg) { case 50000: bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; From b8029394efccf48687d9a7fae6c4747b81e35261 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Oct 2020 13:42:53 +0100 Subject: [PATCH 35/80] pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1 This driver supports both RZ/G2H and R-Car H3 ES2 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2 (R8A77951) is not enabled. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20201019124258.4574-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77951.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index a94ebe0bf5d0..8d1262c170af 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -1827,6 +1827,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2041,6 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4159,7 +4161,9 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[320]; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_pin_group automotive[30]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4483,6 +4487,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4515,7 +4520,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } - +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; static const char * const audio_clk_groups[] = { @@ -4574,6 +4579,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4615,6 +4621,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ static const char * const du_groups[] = { "du_rgb666", @@ -5041,7 +5048,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[53]; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5098,13 +5107,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } - +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 74ce7a8044b07268817828af2d6268801ddc012b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Oct 2020 14:28:05 +0100 Subject: [PATCH 36/80] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1 This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20201019132805.5996-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7796.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 55f0344a3d3e..88e9c46003d9 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1831,6 +1831,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2045,6 +2046,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4133,7 +4135,9 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[316]; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_pin_group automotive[30]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4453,6 +4457,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4485,6 +4490,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; static const char * const audio_clk_groups[] = { @@ -4543,6 +4549,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4584,6 +4591,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ static const char * const du_groups[] = { "du_rgb666", @@ -4997,7 +5005,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[50]; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5051,12 +5061,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 74c5fdc5b87a9435d6afbdd7d22c874c160bafc6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Oct 2020 13:42:55 +0100 Subject: [PATCH 37/80] pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1 This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N (R8A77965) is not enabled. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20201019124258.4574-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77965.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 7a50b9b69a7d..38b7b844abe9 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -1847,6 +1847,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2120,6 +2121,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4380,7 +4382,9 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[318]; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_pin_group automotive[30]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4702,6 +4706,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77965 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4734,6 +4739,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; static const char * const audio_clk_groups[] = { @@ -4792,6 +4798,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4833,6 +4840,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ static const char * const du_groups[] = { "du_rgb666", @@ -5250,7 +5258,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[51]; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5305,12 +5315,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77965 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 03522a59a9e7e5f464735e907891cd235aa68b1d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Oct 2020 13:42:56 +0100 Subject: [PATCH 38/80] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0 This driver supports both RZ/G2E and R-Car E3 SoCs. Optimize pinctrl image size for RZ/G2E, when support for R-Car E3 (R8A77990) is not enabled. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77990.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index aed04a4c6116..6f9f7638703d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1593,6 +1593,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -1785,6 +1786,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -3761,7 +3763,9 @@ static const unsigned int vin5_clk_b_mux[] = { static const struct { struct sh_pfc_pin_group common[247]; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[21]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4012,6 +4016,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk_a), SH_PFC_PIN_GROUP(vin5_clk_b), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4035,6 +4040,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; static const char * const audio_clk_groups[] = { @@ -4088,6 +4094,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4120,6 +4127,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ static const char * const du_groups[] = { "du_rgb666", @@ -4460,7 +4468,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[47]; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4511,12 +4521,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 529b8eecb5c3b61cc53a21b72a12304a03e83c9f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Oct 2020 13:42:57 +0100 Subject: [PATCH 39/80] pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742 This driver supports both RZ/G1H and R-Car H2 SoCs. Optimize pinctrl image size for RZ/G1H, when support for R-Car H2 (R8A7790) is not enabled. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20201019124258.4574-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7790.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 3f48d3d879f7..e9a64e0e2734 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -2393,6 +2393,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_R8A7790 /* - MLB+ ------------------------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), @@ -2400,6 +2402,8 @@ static const unsigned int mlb_3pin_pins[] = { static const unsigned int mlb_3pin_mux[] = { MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ + /* - MMCIF0 ----------------------------------------------------------------- */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ @@ -4131,7 +4135,9 @@ static const unsigned int vin3_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[311]; +#ifdef CONFIG_PINCTRL_PFC_R8A7790 struct sh_pfc_pin_group automotive[1]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4446,9 +4452,11 @@ static const struct { SH_PFC_PIN_GROUP(vin3_clkenb), SH_PFC_PIN_GROUP(vin3_clk), }, +#ifdef CONFIG_PINCTRL_PFC_R8A7790 .automotive = { SH_PFC_PIN_GROUP(mlb_3pin), } +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ }; static const char * const audio_clk_groups[] = { @@ -4592,9 +4600,11 @@ static const char * const intc_groups[] = { "intc_irq3", }; +#ifdef CONFIG_PINCTRL_PFC_R8A7790 static const char * const mlb_groups[] = { "mlb_3pin", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ static const char * const mmc0_groups[] = { "mmc0_data1", @@ -4942,7 +4952,9 @@ static const char * const vin3_groups[] = { static const struct { struct sh_pfc_function common[58]; +#ifdef CONFIG_PINCTRL_PFC_R8A7790 struct sh_pfc_function automotive[1]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5004,9 +5016,11 @@ static const struct { SH_PFC_FUNCTION(vin2), SH_PFC_FUNCTION(vin3), }, +#ifdef CONFIG_PINCTRL_PFC_R8A7790 .automotive = { SH_PFC_FUNCTION(mlb), } +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 8d3b2e3d5b1b27054c62a61bc1191131533166e5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Oct 2020 13:42:58 +0100 Subject: [PATCH 40/80] pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[34] This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs. Optimize pinctrl image size for RZ/G1[MN], when support for R-Car M2-W/M2-N (R8A779[13]) is not enabled. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20201019124258.4574-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7791.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index bc9caf812fc1..6fce9fe2e98f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -1700,6 +1700,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - ADI -------------------------------------------------------------------- */ static const unsigned int adi_common_pins[] = { /* ADIDATA, ADICS/SAMP, ADICLK */ @@ -1765,6 +1766,7 @@ static const unsigned int adi_chsel2_b_mux[] = { /* ADICHS B 2 */ ADICHS2_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ /* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { @@ -2553,6 +2555,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; + +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - MLB+ ------------------------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), @@ -2560,6 +2564,8 @@ static const unsigned int mlb_3pin_pins[] = { static const unsigned int mlb_3pin_mux[] = { MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ + /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc_data1_pins[] = { /* D[0] */ @@ -4452,7 +4458,9 @@ static const unsigned int vin2_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[346]; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) struct sh_pfc_pin_group automotive[9]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4802,6 +4810,7 @@ static const struct { SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { SH_PFC_PIN_GROUP(adi_common), SH_PFC_PIN_GROUP(adi_chsel0), @@ -4813,8 +4822,10 @@ static const struct { SH_PFC_PIN_GROUP(adi_chsel2_b), SH_PFC_PIN_GROUP(mlb_3pin), } +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ }; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const adi_groups[] = { "adi_common", "adi_chsel0", @@ -4825,6 +4836,7 @@ static const char * const adi_groups[] = { "adi_chsel1_b", "adi_chsel2_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ static const char * const audio_clk_groups[] = { "audio_clk_a", @@ -5002,9 +5014,11 @@ static const char * const intc_groups[] = { "intc_irq3", }; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const mlb_groups[] = { "mlb_3pin", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ static const char * const mmc_groups[] = { "mmc_data1", @@ -5359,7 +5373,9 @@ static const char * const vin2_groups[] = { static const struct { struct sh_pfc_function common[58]; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) struct sh_pfc_function automotive[2]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5421,10 +5437,12 @@ static const struct { SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { SH_PFC_FUNCTION(adi), SH_PFC_FUNCTION(mlb), } +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From b5bd0becfd42e6d007ad559c9068b80ef3ff84b8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:30 +0100 Subject: [PATCH 41/80] pinctrl: renesas: Remove superfluous goto in sh_pfc_gpio_set_direction() Commit b13431ed6eab808a ("pinctrl: sh-pfc: Remove incomplete flag "cfg->type"") removed the last statement in between the goto and the label. Hence remove both. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-2-geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 212a4a9c3a8f..f8d5fae66e86 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -460,12 +460,7 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, } spin_lock_irqsave(&pfc->lock, flags); - ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); - if (ret < 0) - goto done; - -done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; } From b589f241d8715803c11b6975b6322731b664b5ef Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:31 +0100 Subject: [PATCH 42/80] pinctrl: renesas: Singular/plural grammar fixes Fix a few singular vs. plural grammar issues in comments. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-3-geert+renesas@glider.be --- drivers/pinctrl/renesas/gpio.c | 2 +- drivers/pinctrl/renesas/pinctrl.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index 9c6e931ae766..ad06f5355d1e 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -328,7 +328,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (pfc->info->data_regs == NULL) return 0; - /* Find the memory window that contain the GPIO registers. Boards that + /* Find the memory window that contains the GPIO registers. Boards that * register a separate GPIO device will not supply a memory resource * that covers the data registers. In that case don't try to handle * GPIOs. diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index f8d5fae66e86..8e54f9b662f3 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -399,7 +399,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); if (!pfc->gpio) { - /* If GPIOs are handled externally the pin mux type need to be + /* If GPIOs are handled externally the pin mux type needs to be * set to GPIO here. */ const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; @@ -450,8 +450,8 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, unsigned int dir; int ret; - /* Check if the requested direction is supported by the pin. Not all SoC - * provide pin config data, so perform the check conditionally. + /* Check if the requested direction is supported by the pin. Not all + * SoCs provide pin config data, so perform the check conditionally. */ if (pin->configs) { dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; From eb9d673f94fb186702c4933ef72d190232c26ce9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:32 +0100 Subject: [PATCH 43/80] pinctrl: renesas: Reorder struct sh_pfc_pin to remove hole On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is present in between the enum_id and name members of the sh_pfc_pin structure. Get rid of this hole by sorting the structure's members by decreasing size. This saves up to 1.5 KiB per enabled SoC, and reduces the size of a kernel including support for all R-Car Gen3 SoCs by more than 10 KiB. This has no size impact on SH and arm32. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-4-geert+renesas@glider.be --- drivers/pinctrl/renesas/sh_pfc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index eff1bb872325..3b390dffacb4 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -34,10 +34,10 @@ enum { #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) struct sh_pfc_pin { - u16 pin; - u16 enum_id; const char *name; unsigned int configs; + u16 pin; + u16 enum_id; }; #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ From 8019938a85d0f7e5ed06cd9bf0824e5edae9be2b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:33 +0100 Subject: [PATCH 44/80] pinctrl: renesas: Optimize sh_pfc_pin_config Shrink sh_pfc_pin_config from 8 to 2 bytes: - The mux_set flag can be removed, as a non-zero mark value means the same (zero = PINMUX_RESERVED is an invalid mark value), - The gpio_enabled flag needs only a single bit, - Mark values are small integers, and can easily fit in a 15-bit bitfield. This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 8e54f9b662f3..d34079726039 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -26,9 +26,8 @@ #include "../pinconf.h" struct sh_pfc_pin_config { - unsigned int mux_mark; - bool mux_set; - bool gpio_enabled; + u16 gpio_enabled:1; + u16 mux_mark:15; }; struct sh_pfc_pinctrl { @@ -371,12 +370,11 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, goto done; } - /* All group pins are configured, mark the pins as mux_set */ + /* All group pins are configured, mark the pins as muxed */ for (i = 0; i < grp->nr_pins; ++i) { int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - cfg->mux_set = true; cfg->mux_mark = grp->mux[i]; } @@ -432,7 +430,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); cfg->gpio_enabled = false; /* If mux is already set, this configures it here */ - if (cfg->mux_set) + if (cfg->mux_mark) sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); spin_unlock_irqrestore(&pfc->lock, flags); } From 27e768a4e7fa8b2b727a05e2eabf000ac7119f5d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:34 +0100 Subject: [PATCH 45/80] pinctrl: renesas: Factor out common R-Car Gen3 bias handling All pin control drivers for R-Car Gen3 SoCs contain identical bias handling. Reduce code duplication by moving it to the common pinctrl.c code. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-6-geert+renesas@glider.be --- drivers/pinctrl/renesas/core.h | 4 +++ drivers/pinctrl/renesas/pfc-r8a77950.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a77951.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a7796.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a77965.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a77990.c | 45 ++------------------------ drivers/pinctrl/renesas/pinctrl.c | 40 +++++++++++++++++++++++ 7 files changed, 54 insertions(+), 215 deletions(-) diff --git a/drivers/pinctrl/renesas/core.h b/drivers/pinctrl/renesas/core.h index b5b1d163e98a..5ca7e0830ae9 100644 --- a/drivers/pinctrl/renesas/core.h +++ b/drivers/pinctrl/renesas/core.h @@ -33,4 +33,8 @@ const struct pinmux_bias_reg * sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, unsigned int *bit); +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); + #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index 04812e62f3a4..32b66b9999b8 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -5820,51 +5820,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { .pin_to_pocctrl = r8a77950_pin_to_pocctrl, - .get_bias = r8a77950_pinmux_get_bias, - .set_bias = r8a77950_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77950_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 8d1262c170af..72252fdcbc21 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -6201,51 +6201,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { .pin_to_pocctrl = r8a77951_pin_to_pocctrl, - .get_bias = r8a77951_pinmux_get_bias, - .set_bias = r8a77951_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774E1 diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 88e9c46003d9..6e8e023410c4 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -6150,51 +6150,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { .pin_to_pocctrl = r8a7796_pin_to_pocctrl, - .get_bias = r8a7796_pinmux_get_bias, - .set_bias = r8a7796_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774A1 diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 38b7b844abe9..590e5f8006d4 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -6404,51 +6404,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { .pin_to_pocctrl = r8a77965_pin_to_pocctrl, - .get_bias = r8a77965_pinmux_get_bias, - .set_bias = r8a77965_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774B1 diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 6f9f7638703d..a51c1e684439 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -5237,51 +5237,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { .pin_to_pocctrl = r8a77990_pin_to_pocctrl, - .get_bias = r8a77990_pinmux_get_bias, - .set_bias = r8a77990_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774C0 diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index d34079726039..4a030600f4fd 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -823,3 +823,43 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) return pinctrl_enable(pmx->pctl); } + +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + u32 enable, updown; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= BIT(bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); +} From 2d341cc3da8a0aef8b505ea7d2de39075e181088 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:35 +0100 Subject: [PATCH 46/80] pinctrl: renesas: r8a7778: Use physical addresses for PUPR regs The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car M1A uses register offsets instead of register physical addresses. This is different from the handling on other R-Car parts. Convert the bias handling from register offsets to physical addresses. This increases uniformity, and prepares for consolidation of the bias handling. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-7-geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7778.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index a9875038ed9b..debf0c9a281c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -2909,7 +2909,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }; static const struct pinmux_bias_reg pinmux_bias_regs[] = { - { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 6), /* A0 */ [ 1] = RCAR_GP_PIN(0, 7), /* A1 */ [ 2] = RCAR_GP_PIN(0, 8), /* A2 */ @@ -2943,7 +2943,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */ [31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */ } }, - { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */ [ 1] = RCAR_GP_PIN(0, 5), /* /BS */ [ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */ @@ -2977,7 +2977,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) { [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */ [ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */ [ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */ @@ -3011,7 +3011,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */ [31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */ } }, - { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) { [ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */ [ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */ [ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */ @@ -3045,7 +3045,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */ [31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */ } }, - { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) { [ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */ [ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */ [ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */ @@ -3079,7 +3079,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(1, 14), /* IRQ2 */ [31] = RCAR_GP_PIN(1, 15), /* IRQ3 */ } }, - { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */ [ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */ [ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */ @@ -3120,16 +3120,13 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { const struct pinmux_bias_reg *reg; - void __iomem *addr; unsigned int bit; reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); if (!reg) return PIN_CONFIG_BIAS_DISABLE; - addr = pfc->windows->virt + reg->puen; - - if (ioread32(addr) & BIT(bit)) + if (sh_pfc_read(pfc, reg->puen) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_DISABLE; @@ -3139,7 +3136,6 @@ static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { const struct pinmux_bias_reg *reg; - void __iomem *addr; unsigned int bit; u32 value; @@ -3147,12 +3143,10 @@ static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, if (!reg) return; - addr = pfc->windows->virt + reg->puen; - - value = ioread32(addr) & ~BIT(bit); + value = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) value |= BIT(bit); - iowrite32(value, addr); + sh_pfc_write(pfc, reg->puen, value); } static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { From a3ee0a246df1755af04d79cd6cd53939aeb6a0db Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:36 +0100 Subject: [PATCH 47/80] pinctrl: renesas: r8a7778: Use common R-Car bias handling Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD) registers, like R-Car Gen3 and RZ/G2. Update the function to handle SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car Gen1/Gen2 and RZ/G1. Reduce code duplication by converting the R-Car M1A pin control driver to use the common handler. Note that this changes behavior in case the (invalid!) option "bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored silently; after this change, it is considered the same as "bias-pull-up". Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7778.c | 37 ++------------------------- drivers/pinctrl/renesas/pinctrl.c | 13 ++++++---- 2 files changed, 10 insertions(+), 40 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index debf0c9a281c..75f52b1798c3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -3116,42 +3116,9 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (sh_pfc_read(pfc, reg->puen) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_DISABLE; -} - -static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - u32 value; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - value = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - value |= BIT(bit); - sh_pfc_write(pfc, reg->puen, value); -} - static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { - .get_bias = r8a7778_pinmux_get_bias, - .set_bias = r8a7778_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7778_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 4a030600f4fd..d5c798e98c18 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -835,7 +835,7 @@ unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -856,10 +856,13 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, if (bias != PIN_CONFIG_BIAS_DISABLE) enable |= BIT(bit); - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); + if (reg->pud) { + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + } - sh_pfc_write(pfc, reg->pud, updown); sh_pfc_write(pfc, reg->puen, enable); } From 7b1425f08f5620bde28aced29820004bc8c28962 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2020 16:16:37 +0100 Subject: [PATCH 48/80] pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIO On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 2 ++ drivers/pinctrl/renesas/pinctrl.c | 4 ++++ drivers/pinctrl/renesas/sh_pfc.h | 8 +++++--- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index c528c124fb0e..2cc457279345 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -315,6 +315,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) range = NULL; break; +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO case PINMUX_TYPE_OUTPUT: range = &pfc->info->output; break; @@ -322,6 +323,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) case PINMUX_TYPE_INPUT: range = &pfc->info->input; break; +#endif /* CONFIG_PINCTRL_SH_PFC_GPIO */ default: return -EINVAL; diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index d5c798e98c18..ac542d278a38 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -435,6 +435,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_unlock_irqrestore(&pfc->lock, flags); } +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool input) @@ -462,6 +463,9 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, spin_unlock_irqrestore(&pfc->lock, flags); return ret; } +#else +#define sh_pfc_gpio_set_direction NULL +#endif static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 3b390dffacb4..dc484c13f59c 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -270,8 +270,13 @@ struct sh_pfc_soc_info { const char *name; const struct sh_pfc_soc_operations *ops; +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO struct pinmux_range input; struct pinmux_range output; + const struct pinmux_irq *gpio_irq; + unsigned int gpio_irq_size; +#endif + struct pinmux_range function; const struct sh_pfc_pin *pins; @@ -295,9 +300,6 @@ struct sh_pfc_soc_info { const u16 *pinmux_data; unsigned int pinmux_data_size; - const struct pinmux_irq *gpio_irq; - unsigned int gpio_irq_size; - u32 unlock_reg; }; From d4aac7d439c2d9307cb5137fc285464a36978107 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Mon, 9 Nov 2020 23:10:12 +0100 Subject: [PATCH 49/80] pinctrl: renesas: Constify sh73a0_vccq_mc0_ops The only usage of sh73a0_vccq_mc0_ops is to assign its address to the ops field in the regulator_desc struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-sh73a0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c index afabd95105d5..96b91e95b1e1 100644 --- a/drivers/pinctrl/renesas/pfc-sh73a0.c +++ b/drivers/pinctrl/renesas/pfc-sh73a0.c @@ -4279,7 +4279,7 @@ static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) return 3300000; } -static struct regulator_ops sh73a0_vccq_mc0_ops = { +static const struct regulator_ops sh73a0_vccq_mc0_ops = { .enable = sh73a0_vccq_mc0_enable, .disable = sh73a0_vccq_mc0_disable, .is_enabled = sh73a0_vccq_mc0_is_enabled, From 0b74e40a4e41f3cbad76dff4c50850d47b525b26 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 12 Nov 2020 21:03:01 +0200 Subject: [PATCH 50/80] pinctrl: baytrail: Avoid clearing debounce value when turning it off Baytrail pin control has a common register to set up debounce timeout. When a pin configuration requested debounce to be disabled, the rest of the pins may still want to have debounce enabled and thus rely on the common timeout value. Avoid clearing debounce value when turning it off for one pin while others may still use it. Fixes: 658b476c742f ("pinctrl: baytrail: Add debounce configuration") Depends-on: 04ff5a095d66 ("pinctrl: baytrail: Rectify debounce support") Depends-on: 827e1579e1d5 ("pinctrl: baytrail: Rectify debounce support (part 2)") Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-baytrail.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index d49aab3cfbaa..394a421a19d5 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1049,7 +1049,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, break; case PIN_CONFIG_INPUT_DEBOUNCE: debounce = readl(db_reg); - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; if (arg) conf |= BYT_DEBOUNCE_EN; @@ -1058,24 +1057,31 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, switch (arg) { case 375: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_375US; break; case 750: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_750US; break; case 1500: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_1500US; break; case 3000: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_3MS; break; case 6000: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_6MS; break; case 12000: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_12MS; break; case 24000: + debounce &= ~BYT_DEBOUNCE_PULSE_MASK; debounce |= BYT_DEBOUNCE_PULSE_24MS; break; default: From 8d1e4f90ce445248d9e87ce5276b31cb675ec84f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Nov 2020 16:02:10 -0300 Subject: [PATCH 51/80] pinctrl: imx21: Remove the driver Since commit 4b563a066611 ("ARM: imx: Remove imx21 support") the imx21 SoC is no longer supported. Get rid of its pinctrl driver too, which is now unused. Signed-off-by: Fabio Estevam Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201110190210.29376-1-festevam@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 7 - drivers/pinctrl/freescale/Makefile | 1 - drivers/pinctrl/freescale/pinctrl-imx21.c | 330 ---------------------- 3 files changed, 338 deletions(-) delete mode 100644 drivers/pinctrl/freescale/pinctrl-imx21.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index a1fbb3b9ae34..f294336430cc 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -24,13 +24,6 @@ config PINCTRL_IMX1 help Say Y here to enable the imx1 pinctrl driver -config PINCTRL_IMX21 - bool "i.MX21 pinctrl driver" - depends on SOC_IMX21 - select PINCTRL_IMX1_CORE - help - Say Y here to enable the i.MX21 pinctrl driver - config PINCTRL_IMX27 bool "IMX27 pinctrl driver" depends on SOC_IMX27 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index c61722565289..e476cb671037 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -4,7 +4,6 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o -obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c deleted file mode 100644 index 8a102275a053..000000000000 --- a/drivers/pinctrl/freescale/pinctrl-imx21.c +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// i.MX21 pinctrl driver based on imx pinmux core -// -// Copyright (C) 2014 Alexander Shiyan - -#include -#include -#include -#include - -#include "pinctrl-imx1.h" - -#define PAD_ID(port, pin) ((port) * 32 + (pin)) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 -#define PE 4 -#define PF 5 - -enum imx21_pads { - MX21_PAD_LSCLK = PAD_ID(PA, 5), - MX21_PAD_LD0 = PAD_ID(PA, 6), - MX21_PAD_LD1 = PAD_ID(PA, 7), - MX21_PAD_LD2 = PAD_ID(PA, 8), - MX21_PAD_LD3 = PAD_ID(PA, 9), - MX21_PAD_LD4 = PAD_ID(PA, 10), - MX21_PAD_LD5 = PAD_ID(PA, 11), - MX21_PAD_LD6 = PAD_ID(PA, 12), - MX21_PAD_LD7 = PAD_ID(PA, 13), - MX21_PAD_LD8 = PAD_ID(PA, 14), - MX21_PAD_LD9 = PAD_ID(PA, 15), - MX21_PAD_LD10 = PAD_ID(PA, 16), - MX21_PAD_LD11 = PAD_ID(PA, 17), - MX21_PAD_LD12 = PAD_ID(PA, 18), - MX21_PAD_LD13 = PAD_ID(PA, 19), - MX21_PAD_LD14 = PAD_ID(PA, 20), - MX21_PAD_LD15 = PAD_ID(PA, 21), - MX21_PAD_LD16 = PAD_ID(PA, 22), - MX21_PAD_LD17 = PAD_ID(PA, 23), - MX21_PAD_REV = PAD_ID(PA, 24), - MX21_PAD_CLS = PAD_ID(PA, 25), - MX21_PAD_PS = PAD_ID(PA, 26), - MX21_PAD_SPL_SPR = PAD_ID(PA, 27), - MX21_PAD_HSYNC = PAD_ID(PA, 28), - MX21_PAD_VSYNC = PAD_ID(PA, 29), - MX21_PAD_CONTRAST = PAD_ID(PA, 30), - MX21_PAD_OE_ACD = PAD_ID(PA, 31), - MX21_PAD_SD2_D0 = PAD_ID(PB, 4), - MX21_PAD_SD2_D1 = PAD_ID(PB, 5), - MX21_PAD_SD2_D2 = PAD_ID(PB, 6), - MX21_PAD_SD2_D3 = PAD_ID(PB, 7), - MX21_PAD_SD2_CMD = PAD_ID(PB, 8), - MX21_PAD_SD2_CLK = PAD_ID(PB, 9), - MX21_PAD_CSI_D0 = PAD_ID(PB, 10), - MX21_PAD_CSI_D1 = PAD_ID(PB, 11), - MX21_PAD_CSI_D2 = PAD_ID(PB, 12), - MX21_PAD_CSI_D3 = PAD_ID(PB, 13), - MX21_PAD_CSI_D4 = PAD_ID(PB, 14), - MX21_PAD_CSI_MCLK = PAD_ID(PB, 15), - MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16), - MX21_PAD_CSI_D5 = PAD_ID(PB, 17), - MX21_PAD_CSI_D6 = PAD_ID(PB, 18), - MX21_PAD_CSI_D7 = PAD_ID(PB, 19), - MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20), - MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21), - MX21_PAD_USB_BYP = PAD_ID(PB, 22), - MX21_PAD_USB_PWR = PAD_ID(PB, 23), - MX21_PAD_USB_OC = PAD_ID(PB, 24), - MX21_PAD_USBH_ON = PAD_ID(PB, 25), - MX21_PAD_USBH1_FS = PAD_ID(PB, 26), - MX21_PAD_USBH1_OE = PAD_ID(PB, 27), - MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28), - MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29), - MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30), - MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31), - MX21_PAD_USBG_SDA = PAD_ID(PC, 5), - MX21_PAD_USBG_SCL = PAD_ID(PC, 6), - MX21_PAD_USBG_ON = PAD_ID(PC, 7), - MX21_PAD_USBG_FS = PAD_ID(PC, 8), - MX21_PAD_USBG_OE = PAD_ID(PC, 9), - MX21_PAD_USBG_TXDM = PAD_ID(PC, 10), - MX21_PAD_USBG_TXDP = PAD_ID(PC, 11), - MX21_PAD_USBG_RXDM = PAD_ID(PC, 12), - MX21_PAD_USBG_RXDP = PAD_ID(PC, 13), - MX21_PAD_TOUT = PAD_ID(PC, 14), - MX21_PAD_TIN = PAD_ID(PC, 15), - MX21_PAD_SAP_FS = PAD_ID(PC, 16), - MX21_PAD_SAP_RXD = PAD_ID(PC, 17), - MX21_PAD_SAP_TXD = PAD_ID(PC, 18), - MX21_PAD_SAP_CLK = PAD_ID(PC, 19), - MX21_PAD_SSI1_FS = PAD_ID(PC, 20), - MX21_PAD_SSI1_RXD = PAD_ID(PC, 21), - MX21_PAD_SSI1_TXD = PAD_ID(PC, 22), - MX21_PAD_SSI1_CLK = PAD_ID(PC, 23), - MX21_PAD_SSI2_FS = PAD_ID(PC, 24), - MX21_PAD_SSI2_RXD = PAD_ID(PC, 25), - MX21_PAD_SSI2_TXD = PAD_ID(PC, 26), - MX21_PAD_SSI2_CLK = PAD_ID(PC, 27), - MX21_PAD_SSI3_FS = PAD_ID(PC, 28), - MX21_PAD_SSI3_RXD = PAD_ID(PC, 29), - MX21_PAD_SSI3_TXD = PAD_ID(PC, 30), - MX21_PAD_SSI3_CLK = PAD_ID(PC, 31), - MX21_PAD_I2C_DATA = PAD_ID(PD, 17), - MX21_PAD_I2C_CLK = PAD_ID(PD, 18), - MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19), - MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20), - MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21), - MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22), - MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23), - MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24), - MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25), - MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26), - MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27), - MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28), - MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29), - MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30), - MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31), - MX21_PAD_TEST_WB2 = PAD_ID(PE, 0), - MX21_PAD_TEST_WB1 = PAD_ID(PE, 1), - MX21_PAD_TEST_WB0 = PAD_ID(PE, 2), - MX21_PAD_UART2_CTS = PAD_ID(PE, 3), - MX21_PAD_UART2_RTS = PAD_ID(PE, 4), - MX21_PAD_PWMO = PAD_ID(PE, 5), - MX21_PAD_UART2_TXD = PAD_ID(PE, 6), - MX21_PAD_UART2_RXD = PAD_ID(PE, 7), - MX21_PAD_UART3_TXD = PAD_ID(PE, 8), - MX21_PAD_UART3_RXD = PAD_ID(PE, 9), - MX21_PAD_UART3_CTS = PAD_ID(PE, 10), - MX21_PAD_UART3_RTS = PAD_ID(PE, 11), - MX21_PAD_UART1_TXD = PAD_ID(PE, 12), - MX21_PAD_UART1_RXD = PAD_ID(PE, 13), - MX21_PAD_UART1_CTS = PAD_ID(PE, 14), - MX21_PAD_UART1_RTS = PAD_ID(PE, 15), - MX21_PAD_RTCK = PAD_ID(PE, 16), - MX21_PAD_RESET_OUT = PAD_ID(PE, 17), - MX21_PAD_SD1_D0 = PAD_ID(PE, 18), - MX21_PAD_SD1_D1 = PAD_ID(PE, 19), - MX21_PAD_SD1_D2 = PAD_ID(PE, 20), - MX21_PAD_SD1_D3 = PAD_ID(PE, 21), - MX21_PAD_SD1_CMD = PAD_ID(PE, 22), - MX21_PAD_SD1_CLK = PAD_ID(PE, 23), - MX21_PAD_NFRB = PAD_ID(PF, 0), - MX21_PAD_NFCE = PAD_ID(PF, 1), - MX21_PAD_NFWP = PAD_ID(PF, 2), - MX21_PAD_NFCLE = PAD_ID(PF, 3), - MX21_PAD_NFALE = PAD_ID(PF, 4), - MX21_PAD_NFRE = PAD_ID(PF, 5), - MX21_PAD_NFWE = PAD_ID(PF, 6), - MX21_PAD_NFIO0 = PAD_ID(PF, 7), - MX21_PAD_NFIO1 = PAD_ID(PF, 8), - MX21_PAD_NFIO2 = PAD_ID(PF, 9), - MX21_PAD_NFIO3 = PAD_ID(PF, 10), - MX21_PAD_NFIO4 = PAD_ID(PF, 11), - MX21_PAD_NFIO5 = PAD_ID(PF, 12), - MX21_PAD_NFIO6 = PAD_ID(PF, 13), - MX21_PAD_NFIO7 = PAD_ID(PF, 14), - MX21_PAD_CLKO = PAD_ID(PF, 15), - MX21_PAD_RESERVED = PAD_ID(PF, 16), - MX21_PAD_CS4 = PAD_ID(PF, 21), - MX21_PAD_CS5 = PAD_ID(PF, 22), -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX21_PAD_LSCLK), - IMX_PINCTRL_PIN(MX21_PAD_LD0), - IMX_PINCTRL_PIN(MX21_PAD_LD1), - IMX_PINCTRL_PIN(MX21_PAD_LD2), - IMX_PINCTRL_PIN(MX21_PAD_LD3), - IMX_PINCTRL_PIN(MX21_PAD_LD4), - IMX_PINCTRL_PIN(MX21_PAD_LD5), - IMX_PINCTRL_PIN(MX21_PAD_LD6), - IMX_PINCTRL_PIN(MX21_PAD_LD7), - IMX_PINCTRL_PIN(MX21_PAD_LD8), - IMX_PINCTRL_PIN(MX21_PAD_LD9), - IMX_PINCTRL_PIN(MX21_PAD_LD10), - IMX_PINCTRL_PIN(MX21_PAD_LD11), - IMX_PINCTRL_PIN(MX21_PAD_LD12), - IMX_PINCTRL_PIN(MX21_PAD_LD13), - IMX_PINCTRL_PIN(MX21_PAD_LD14), - IMX_PINCTRL_PIN(MX21_PAD_LD15), - IMX_PINCTRL_PIN(MX21_PAD_LD16), - IMX_PINCTRL_PIN(MX21_PAD_LD17), - IMX_PINCTRL_PIN(MX21_PAD_REV), - IMX_PINCTRL_PIN(MX21_PAD_CLS), - IMX_PINCTRL_PIN(MX21_PAD_PS), - IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR), - IMX_PINCTRL_PIN(MX21_PAD_HSYNC), - IMX_PINCTRL_PIN(MX21_PAD_VSYNC), - IMX_PINCTRL_PIN(MX21_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX21_PAD_OE_ACD), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D0), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D1), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D2), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D3), - IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D0), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D1), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D2), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D3), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D4), - IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D5), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D6), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D7), - IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX21_PAD_USB_BYP), - IMX_PINCTRL_PIN(MX21_PAD_USB_PWR), - IMX_PINCTRL_PIN(MX21_PAD_USB_OC), - IMX_PINCTRL_PIN(MX21_PAD_USBH_ON), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA), - IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL), - IMX_PINCTRL_PIN(MX21_PAD_USBG_ON), - IMX_PINCTRL_PIN(MX21_PAD_USBG_FS), - IMX_PINCTRL_PIN(MX21_PAD_USBG_OE), - IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP), - IMX_PINCTRL_PIN(MX21_PAD_TOUT), - IMX_PINCTRL_PIN(MX21_PAD_TIN), - IMX_PINCTRL_PIN(MX21_PAD_SAP_FS), - IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK), - IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA), - IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI), - IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2), - IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1), - IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0), - IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS), - IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS), - IMX_PINCTRL_PIN(MX21_PAD_PWMO), - IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD), - IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD), - IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS), - IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS), - IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX21_PAD_RTCK), - IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D0), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D1), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D2), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D3), - IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX21_PAD_NFRB), - IMX_PINCTRL_PIN(MX21_PAD_NFCE), - IMX_PINCTRL_PIN(MX21_PAD_NFWP), - IMX_PINCTRL_PIN(MX21_PAD_NFCLE), - IMX_PINCTRL_PIN(MX21_PAD_NFALE), - IMX_PINCTRL_PIN(MX21_PAD_NFRE), - IMX_PINCTRL_PIN(MX21_PAD_NFWE), - IMX_PINCTRL_PIN(MX21_PAD_NFIO0), - IMX_PINCTRL_PIN(MX21_PAD_NFIO1), - IMX_PINCTRL_PIN(MX21_PAD_NFIO2), - IMX_PINCTRL_PIN(MX21_PAD_NFIO3), - IMX_PINCTRL_PIN(MX21_PAD_NFIO4), - IMX_PINCTRL_PIN(MX21_PAD_NFIO5), - IMX_PINCTRL_PIN(MX21_PAD_NFIO6), - IMX_PINCTRL_PIN(MX21_PAD_NFIO7), - IMX_PINCTRL_PIN(MX21_PAD_CLKO), - IMX_PINCTRL_PIN(MX21_PAD_RESERVED), - IMX_PINCTRL_PIN(MX21_PAD_CS4), - IMX_PINCTRL_PIN(MX21_PAD_CS5), -}; - -static struct imx1_pinctrl_soc_info imx21_pinctrl_info = { - .pins = imx21_pinctrl_pads, - .npins = ARRAY_SIZE(imx21_pinctrl_pads), -}; - -static int __init imx21_pinctrl_probe(struct platform_device *pdev) -{ - return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info); -} - -static const struct of_device_id imx21_pinctrl_of_match[] = { - { .compatible = "fsl,imx21-iomuxc", }, - { } -}; - -static struct platform_driver imx21_pinctrl_driver = { - .driver = { - .name = "imx21-pinctrl", - .of_match_table = imx21_pinctrl_of_match, - }, -}; -builtin_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe); From 89ad953e1e727640e85beb82db3c71d45a59b177 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 19 Nov 2020 13:09:23 +0000 Subject: [PATCH 52/80] pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201119130926.25692-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77990.c | 75 +++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index a51c1e684439..0a32e3c317c1 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2810,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + /* QSPI0_IO2, QSPI0_IO3 */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* QSPI1_IO2, QSPI1_IO3 */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -3762,7 +3813,7 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[247]; + struct sh_pfc_pin_group common[253]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[21]; #endif @@ -3910,6 +3961,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_ctrl_a), @@ -4313,6 +4370,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -4467,7 +4536,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[47]; + struct sh_pfc_function common[49]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_function automotive[4]; #endif @@ -4504,6 +4573,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From 590567bf6f6d989ba9d0fc406282d7a18cf5fa96 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 19 Nov 2020 13:09:24 +0000 Subject: [PATCH 53/80] pinctrl: renesas: r8a77951: Add QSPI[01] pins, groups and functions Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201119130926.25692-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77951.c | 75 +++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 72252fdcbc21..cf14420794c7 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -3252,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4160,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[320]; + struct sh_pfc_pin_group common[326]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_pin_group automotive[30]; #endif @@ -4365,6 +4416,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4859,6 +4916,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5047,7 +5116,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[53]; + struct sh_pfc_function common[55]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_function automotive[4]; #endif @@ -5084,6 +5153,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), From 4356497e9eda8ec7dcd095b1ecd947ffe12917aa Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 19 Nov 2020 13:09:25 +0000 Subject: [PATCH 54/80] pinctrl: renesas: r8a7796: Add QSPI[01] pins, groups and functions Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201119130926.25692-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7796.c | 75 ++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 6e8e023410c4..38d963561b5f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -3257,6 +3257,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -4134,7 +4185,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[316]; + struct sh_pfc_pin_group common[322]; #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_pin_group automotive[30]; #endif @@ -4339,6 +4390,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4829,6 +4886,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -5004,7 +5073,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[50]; + struct sh_pfc_function common[52]; #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_function automotive[4]; #endif @@ -5041,6 +5110,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From ffcd7f812dec2f1f27fe73b89c17a04ef6586325 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 19 Nov 2020 13:09:26 +0000 Subject: [PATCH 55/80] pinctrl: renesas: r8a77965: Add QSPI[01] pins, groups and functions Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201119130926.25692-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77965.c | 75 +++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 590e5f8006d4..92f231baff7d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -3408,6 +3408,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4381,7 +4432,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[318]; + struct sh_pfc_pin_group common[324]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_pin_group automotive[30]; #endif @@ -4586,6 +4637,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -5078,6 +5135,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5257,7 +5326,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[51]; + struct sh_pfc_function common[53]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_function automotive[4]; #endif @@ -5294,6 +5363,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), From 7ba4a9591a8ac058bf976485975f78128c273800 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 20 Nov 2020 12:31:44 -0600 Subject: [PATCH 56/80] pinctrl: renesas: Fix fall-through warnings for Clang In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva Link: https://lore.kernel.org/r/da20103af0c22424c5d08a12f7107771bf4c01c5.1605896059.git.gustavoars@kernel.org Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rza1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 15dd007700c2..10020fe302b8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -931,6 +931,7 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */ case PIN_CONFIG_OUTPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; + break; default: break; From 8dc248665f3a4261907ac35200687c4cb6e16cc0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 23 Nov 2020 13:33:20 +0100 Subject: [PATCH 57/80] Revert "firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module" This reverts commit d0511b5496c03cdbcda55a9b57c32cdd751920ed. After some time it was noticed that the Tegra186 among others were experiencing problems when making this into a module. Signed-off-by: Linus Walleij --- drivers/firmware/Kconfig | 4 ++-- drivers/firmware/Makefile | 3 +-- drivers/firmware/qcom_scm.c | 4 ---- drivers/iommu/Kconfig | 2 -- drivers/net/wireless/ath/ath10k/Kconfig | 1 - 5 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 5e369928bc56..3315e3c21586 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -235,8 +235,8 @@ config INTEL_STRATIX10_RSU Say Y here if you want Intel RSU support. config QCOM_SCM - tristate "Qcom SCM driver" - depends on (ARM && HAVE_ARM_SMCCC) || ARM64 + bool + depends on ARM || ARM64 select RESET_CONTROLLER config QCOM_SCM_DOWNLOAD_MODE_DEFAULT diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 523173cbff33..5e013b6a3692 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -17,8 +17,7 @@ obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o -obj-$(CONFIG_QCOM_SCM) += qcom-scm.o -qcom-scm-objs += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o +obj-$(CONFIG_QCOM_SCM) += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 6f431b73e617..7be48c1bec96 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1280,7 +1280,6 @@ static const struct of_device_id qcom_scm_dt_match[] = { { .compatible = "qcom,scm" }, {} }; -MODULE_DEVICE_TABLE(of, qcom_scm_dt_match); static struct platform_driver qcom_scm_driver = { .driver = { @@ -1296,6 +1295,3 @@ static int __init qcom_scm_init(void) return platform_driver_register(&qcom_scm_driver); } subsys_initcall(qcom_scm_init); - -MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index c64d7a2b6513..04878caf6da4 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -248,7 +248,6 @@ config SPAPR_TCE_IOMMU config ARM_SMMU tristate "ARM Ltd. System MMU (SMMU) Support" depends on ARM64 || ARM || (COMPILE_TEST && !GENERIC_ATOMIC64) - depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select ARM_DMA_USE_IOMMU if ARM @@ -376,7 +375,6 @@ config QCOM_IOMMU # Note: iommu drivers cannot (yet?) be built as modules bool "Qualcomm IOMMU Support" depends on ARCH_QCOM || (COMPILE_TEST && !GENERIC_ATOMIC64) - depends on QCOM_SCM=y select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select ARM_DMA_USE_IOMMU diff --git a/drivers/net/wireless/ath/ath10k/Kconfig b/drivers/net/wireless/ath/ath10k/Kconfig index 741289e385d5..40f91bc8514d 100644 --- a/drivers/net/wireless/ath/ath10k/Kconfig +++ b/drivers/net/wireless/ath/ath10k/Kconfig @@ -44,7 +44,6 @@ config ATH10K_SNOC tristate "Qualcomm ath10k SNOC support" depends on ATH10K depends on ARCH_QCOM || COMPILE_TEST - depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y select QCOM_QMI_HELPERS help This module adds support for integrated WCN3990 chip connected From 2a984219b53422261cd90feb8a1bb5c1583be3fb Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 10 Nov 2020 21:56:19 +0000 Subject: [PATCH 58/80] pinctrl: qcom: Fix msm8953 Kconfig entry to depend on, not select PINCTRL_MSM One fixup following my patch commit be117ca32261 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a selected config") being queued in LinusW's tree, as a new config entry was added for the msm8953 that also needs the change. Applies to LinusW's pinctrl devel tree. Signed-off-by: John Stultz Reviewed-by: Bjorn Andersson Cc: Andy Gross Cc: Prasad Sodagudi Cc: Vladimir Lypak Cc: Bjorn Andersson Cc: Linus Walleij Cc: linux-arm-msm@vger.kernel.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201110215619.86076-1-john.stultz@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dcc046a921cc..87529e15e634 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -115,7 +115,7 @@ config PINCTRL_MSM8916 config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" depends on GPIOLIB && OF - select PINCTRL_MSM + depends on PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8953 platform. From 5913f635a28df654632965db7fe9ff90116f31b5 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 5 Nov 2020 15:26:31 +0530 Subject: [PATCH 59/80] dt-bindings: pinctrl: qcom: Add sc7280 pinctrl bindings Add device tree binding Documentation details for Qualcomm SC7280 TLMM block. Signed-off-by: Rajendra Nayak Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1604570192-15057-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml new file mode 100644 index 000000000000..7d6a2ab10eec --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC7280 TLMM block + +maintainers: + - Rajendra Nayak + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC7280 platform. + +properties: + compatible: + const: qcom,sc7280-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_usb0, atest_usb00, atest_usb01, + atest_usb02, atest_usb03, atest_usb1, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, audio_ref, + cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1, + cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0, + cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot, + dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus, + mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, + mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck, + mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0, + mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2, + mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, + mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2, + pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag, + pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc, + qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs, + qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07, + qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write, + sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1, + tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, + usb_phy, vfr_0, vfr_1, vsense_trigger ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@f000000 { + compatible = "qcom,sc7280-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 175>; + wakeup-parent = <&pdc>; + + qup_uart5_default: qup-uart5-pins { + pins = "gpio46", "gpio47"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + }; From ecb454594c43456bdeb1bd5cd68ac454db51b2c6 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 5 Nov 2020 15:26:32 +0530 Subject: [PATCH 60/80] pinctrl: qcom: Add sc7280 pinctrl driver Add initial pinctrl driver to support pin configuration with pinctrl framework for SC7280 SoC Signed-off-by: Rajendra Nayak Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1604570192-15057-2-git-send-email-rnayak@codeaurora.org [Change select PINCTRL_MSM to depends on PINCTRL_MSM] Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sc7280.c | 1495 +++++++++++++++++++++++++ 3 files changed, 1505 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 87529e15e634..54412f270738 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -211,6 +211,15 @@ config PINCTRL_SC7180 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC7180 platform. +config PINCTRL_SC7280 + tristate "Qualcomm Technologies Inc SC7280 pin controller driver" + depends on GPIOLIB && OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC7280 platform. + config PINCTRL_SDM660 tristate "Qualcomm Technologies Inc SDM660 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 891c422672a4..c28a33c48aa5 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o +obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c new file mode 100644 index 000000000000..8daccd530285 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -0,0 +1,1495 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sc7280_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "UFS_RESET"), + PINCTRL_PIN(176, "SDC1_RCLK"), + PINCTRL_PIN(177, "SDC1_CLK"), + PINCTRL_PIN(178, "SDC1_CMD"), + PINCTRL_PIN(179, "SDC1_DATA"), + PINCTRL_PIN(180, "SDC2_CLK"), + PINCTRL_PIN(181, "SDC2_CMD"), + PINCTRL_PIN(182, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); + +static const unsigned int ufs_reset_pins[] = { 175 }; +static const unsigned int sdc1_rclk_pins[] = { 176 }; +static const unsigned int sdc1_clk_pins[] = { 177 }; +static const unsigned int sdc1_cmd_pins[] = { 178 }; +static const unsigned int sdc1_data_pins[] = { 179 }; +static const unsigned int sdc2_clk_pins[] = { 180 }; +static const unsigned int sdc2_cmd_pins[] = { 181 }; +static const unsigned int sdc2_data_pins[] = { 182 }; + +enum sc7280_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_usb0, + msm_mux_atest_usb00, + msm_mux_atest_usb01, + msm_mux_atest_usb02, + msm_mux_atest_usb03, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cmu_rng0, + msm_mux_cmu_rng1, + msm_mux_cmu_rng2, + msm_mux_cmu_rng3, + msm_mux_coex_uart1, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_host2wlan_sol, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync4, + msm_mux_mdp_vsync5, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mss_grfc0, + msm_mux_mss_grfc1, + msm_mux_mss_grfc10, + msm_mux_mss_grfc11, + msm_mux_mss_grfc12, + msm_mux_mss_grfc2, + msm_mux_mss_grfc3, + msm_mux_mss_grfc4, + msm_mux_mss_grfc5, + msm_mux_mss_grfc6, + msm_mux_mss_grfc7, + msm_mux_mss_grfc8, + msm_mux_mss_grfc9, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_pa_indicator, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup03, + msm_mux_qup04, + msm_mux_qup05, + msm_mux_qup06, + msm_mux_qup07, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", +}; +static const char * const atest_char_groups[] = { + "gpio81", +}; +static const char * const atest_char0_groups[] = { + "gpio77", +}; +static const char * const atest_char1_groups[] = { + "gpio78", +}; +static const char * const atest_char2_groups[] = { + "gpio79", +}; +static const char * const atest_char3_groups[] = { + "gpio80", +}; +static const char * const atest_usb0_groups[] = { + "gpio107", +}; +static const char * const atest_usb00_groups[] = { + "gpio106", +}; +static const char * const atest_usb01_groups[] = { + "gpio105", +}; +static const char * const atest_usb02_groups[] = { + "gpio104", +}; +static const char * const atest_usb03_groups[] = { + "gpio103", +}; +static const char * const atest_usb1_groups[] = { + "gpio81", +}; +static const char * const atest_usb10_groups[] = { + "gpio80", +}; +static const char * const atest_usb11_groups[] = { + "gpio79", +}; +static const char * const atest_usb12_groups[] = { + "gpio78", +}; +static const char * const atest_usb13_groups[] = { + "gpio77", +}; +static const char * const audio_ref_groups[] = { + "gpio105", +}; +static const char * const cam_mclk_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio93", +}; +static const char * const cci_async_groups[] = { + "gpio78", "gpio79", "gpio93", +}; +static const char * const cci_i2c_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", + "gpio76", +}; +static const char * const cci_timer0_groups[] = { + "gpio20", +}; +static const char * const cci_timer1_groups[] = { + "gpio21", +}; +static const char * const cci_timer2_groups[] = { + "gpio77", +}; +static const char * const cci_timer3_groups[] = { + "gpio78", +}; +static const char * const cci_timer4_groups[] = { + "gpio79", +}; +static const char * const cmu_rng0_groups[] = { + "gpio120", +}; +static const char * const cmu_rng1_groups[] = { + "gpio119", +}; +static const char * const cmu_rng2_groups[] = { + "gpio118", +}; +static const char * const cmu_rng3_groups[] = { + "gpio117", +}; +static const char * const coex_uart1_groups[] = { + "gpio127", "gpio128", +}; +static const char * const cri_trng_groups[] = { + "gpio124", +}; +static const char * const cri_trng0_groups[] = { + "gpio121", +}; +static const char * const cri_trng1_groups[] = { + "gpio122", +}; +static const char * const dbg_out_groups[] = { + "gpio38", +}; +static const char * const ddr_bist_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio14", "gpio15", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio12", "gpio13", +}; +static const char * const dp_hot_groups[] = { + "gpio47", +}; +static const char * const dp_lcd_groups[] = { + "gpio81", +}; +static const char * const edp_hot_groups[] = { + "gpio60", +}; +static const char * const edp_lcd_groups[] = { + "gpio46", +}; +static const char * const gcc_gp1_groups[] = { + "gpio76", "gpio105", +}; +static const char * const gcc_gp2_groups[] = { + "gpio77", "gpio106", +}; +static const char * const gcc_gp3_groups[] = { + "gpio78", "gpio107", +}; +static const char * const host2wlan_sol_groups[] = { + "gpio26", +}; +static const char * const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio36", "gpio37", +}; +static const char * const jitter_bist_groups[] = { + "gpio79", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio94", "gpio95", +}; +static const char * const mdp_vsync_groups[] = { + "gpio14", "gpio16", "gpio79", "gpio80", "gpio81", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio80", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio80", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync4_groups[] = { + "gpio80", +}; +static const char * const mdp_vsync5_groups[] = { + "gpio81", +}; +static const char * const mi2s0_data0_groups[] = { + "gpio98", +}; +static const char * const mi2s0_data1_groups[] = { + "gpio99", +}; +static const char * const mi2s0_sck_groups[] = { + "gpio97", +}; +static const char * const mi2s0_ws_groups[] = { + "gpio100", +}; +static const char * const mi2s1_data0_groups[] = { + "gpio107", +}; +static const char * const mi2s1_data1_groups[] = { + "gpio105", +}; +static const char * const mi2s1_sck_groups[] = { + "gpio106", +}; +static const char * const mi2s1_ws_groups[] = { + "gpio108", +}; +static const char * const mi2s2_data0_groups[] = { + "gpio102", +}; +static const char * const mi2s2_data1_groups[] = { + "gpio104", +}; +static const char * const mi2s2_sck_groups[] = { + "gpio101", +}; +static const char * const mi2s2_ws_groups[] = { + "gpio103", +}; +static const char * const mss_grfc0_groups[] = { + "gpio117", "gpio132", +}; +static const char * const mss_grfc1_groups[] = { + "gpio118", +}; +static const char * const mss_grfc10_groups[] = { + "gpio127", +}; +static const char * const mss_grfc11_groups[] = { + "gpio128", +}; +static const char * const mss_grfc12_groups[] = { + "gpio131", +}; +static const char * const mss_grfc2_groups[] = { + "gpio119", +}; +static const char * const mss_grfc3_groups[] = { + "gpio120", +}; +static const char * const mss_grfc4_groups[] = { + "gpio121", +}; +static const char * const mss_grfc5_groups[] = { + "gpio122", +}; +static const char * const mss_grfc6_groups[] = { + "gpio123", +}; +static const char * const mss_grfc7_groups[] = { + "gpio124", +}; +static const char * const mss_grfc8_groups[] = { + "gpio125", +}; +static const char * const mss_grfc9_groups[] = { + "gpio126", +}; +static const char * const nav_gpio0_groups[] = { + "gpio129", +}; +static const char * const nav_gpio1_groups[] = { + "gpio130", +}; +static const char * const nav_gpio2_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio131", +}; +static const char * const pcie0_clkreqn_groups[] = { + "gpio88", +}; +static const char * const pcie1_clkreqn_groups[] = { + "gpio79", +}; +static const char * const phase_flag_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio18", "gpio19", "gpio56", "gpio57", + "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", + "gpio63", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", + "gpio131", "gpio132", +}; +static const char * const pll_bist_groups[] = { + "gpio80", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio66", +}; +static const char * const pll_clk_groups[] = { + "gpio140", +}; +static const char * const pll_reset_groups[] = { + "gpio67", +}; +static const char * const pri_mi2s_groups[] = { + "gpio96", +}; +static const char * const prng_rosc_groups[] = { + "gpio123", +}; +static const char * const qdss_groups[] = { + "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", + "gpio11", "gpio12", "gpio13", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio58", "gpio59", + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio171", "gpio172", "gpio173", + "gpio174", +}; +static const char * const qdss_cti_groups[] = { + "gpio15", "gpio16", "gpio18", "gpio19", "gpio156", "gpio157", + "gpio165", "gpio166", +}; +static const char * const qlink0_enable_groups[] = { + "gpio134", +}; +static const char * const qlink0_request_groups[] = { + "gpio133", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio135", +}; +static const char * const qlink1_enable_groups[] = { + "gpio137", +}; +static const char * const qlink1_request_groups[] = { + "gpio136", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio138", +}; +static const char * const qspi_clk_groups[] = { + "gpio14", +}; +static const char * const qspi_cs_groups[] = { + "gpio15", "gpio19", +}; +static const char * const qspi_data_groups[] = { + "gpio12", "gpio13", "gpio16", "gpio17", +}; +static const char * const qup00_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup01_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qup02_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qup03_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup04_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const qup05_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qup06_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const qup07_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const qup10_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const qup11_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup12_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char * const qup13_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const qup14_groups[] = { + "gpio38", "gpio48", "gpio49", "gpio50", "gpio51", "gpio54", "gpio55", +}; +static const char * const qup15_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char * const qup16_groups[] = { + "gpio50", "gpio56", "gpio57", "gpio58", "gpio59", "gpio62", "gpio63", +}; +static const char * const qup17_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const sd_write_groups[] = { + "gpio61", +}; +static const char * const sdc40_groups[] = { + "gpio12", +}; +static const char * const sdc41_groups[] = { + "gpio13", +}; +static const char * const sdc42_groups[] = { + "gpio16", +}; +static const char * const sdc43_groups[] = { + "gpio17", +}; +static const char * const sdc4_clk_groups[] = { + "gpio14", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio19", +}; +static const char * const sec_mi2s_groups[] = { + "gpio105", +}; +static const char * const tb_trig_groups[] = { + "gpio12", "gpio13", "gpio15", +}; +static const char * const tgu_ch0_groups[] = { + "gpio65", +}; +static const char * const tgu_ch1_groups[] = { + "gpio66", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio61", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio61", +}; +static const char * const uim0_clk_groups[] = { + "gpio114", +}; +static const char * const uim0_data_groups[] = { + "gpio113", +}; +static const char * const uim0_present_groups[] = { + "gpio116", +}; +static const char * const uim0_reset_groups[] = { + "gpio115", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio84", "gpio85", +}; +static const char * const usb_phy_groups[] = { + "gpio140", +}; +static const char * const vfr_0_groups[] = { + "gpio80", +}; +static const char * const vfr_1_groups[] = { + "gpio103", +}; +static const char * const vsense_trigger_groups[] = { + "gpio100", +}; + +static const struct msm_function sc7280_functions[] = { + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_usb0), + FUNCTION(atest_usb00), + FUNCTION(atest_usb01), + FUNCTION(atest_usb02), + FUNCTION(atest_usb03), + FUNCTION(atest_usb1), + FUNCTION(atest_usb10), + FUNCTION(atest_usb11), + FUNCTION(atest_usb12), + FUNCTION(atest_usb13), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cmu_rng0), + FUNCTION(cmu_rng1), + FUNCTION(cmu_rng2), + FUNCTION(cmu_rng3), + FUNCTION(coex_uart1), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(dp_hot), + FUNCTION(dp_lcd), + FUNCTION(edp_hot), + FUNCTION(edp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gpio), + FUNCTION(host2wlan_sol), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(lpass_slimbus), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mdp_vsync4), + FUNCTION(mdp_vsync5), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(mss_grfc0), + FUNCTION(mss_grfc1), + FUNCTION(mss_grfc10), + FUNCTION(mss_grfc11), + FUNCTION(mss_grfc12), + FUNCTION(mss_grfc2), + FUNCTION(mss_grfc3), + FUNCTION(mss_grfc4), + FUNCTION(mss_grfc5), + FUNCTION(mss_grfc6), + FUNCTION(mss_grfc7), + FUNCTION(mss_grfc8), + FUNCTION(mss_grfc9), + FUNCTION(nav_gpio0), + FUNCTION(nav_gpio1), + FUNCTION(nav_gpio2), + FUNCTION(pa_indicator), + FUNCTION(pcie0_clkreqn), + FUNCTION(pcie1_clkreqn), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_clk), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(qdss), + FUNCTION(qdss_cti), + FUNCTION(qlink0_enable), + FUNCTION(qlink0_request), + FUNCTION(qlink0_wmss), + FUNCTION(qlink1_enable), + FUNCTION(qlink1_request), + FUNCTION(qlink1_wmss), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qspi_data), + FUNCTION(qup00), + FUNCTION(qup01), + FUNCTION(qup02), + FUNCTION(qup03), + FUNCTION(qup04), + FUNCTION(qup05), + FUNCTION(qup06), + FUNCTION(qup07), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sd_write), + FUNCTION(sec_mi2s), + FUNCTION(tb_trig), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(uim0_clk), + FUNCTION(uim0_data), + FUNCTION(uim0_present), + FUNCTION(uim0_reset), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(usb2phy_ac), + FUNCTION(usb_phy), + FUNCTION(vfr_0), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sc7280_groups[] = { + [0] = PINGROUP(0, qup00, ibi_i3c, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup00, ibi_i3c, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup00, qup07, _, qdss, _, _, _, _, _), + [3] = PINGROUP(3, qup00, qup07, _, qdss, _, _, _, _, _), + [4] = PINGROUP(4, qup01, ibi_i3c, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup01, ibi_i3c, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup01, qup07, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup01, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup02, _, qdss, _, _, _, _, _, _), + [9] = PINGROUP(9, qup02, _, qdss, _, _, _, _, _, _), + [10] = PINGROUP(10, qup02, _, qdss, _, _, _, _, _, _), + [11] = PINGROUP(11, qup02, _, qdss, _, _, _, _, _, _), + [12] = PINGROUP(12, qup03, qspi_data, sdc40, tb_trig, phase_flag, qdss, ddr_pxi1, _, _), + [13] = PINGROUP(13, qup03, qspi_data, sdc41, tb_trig, phase_flag, qdss, ddr_pxi1, _, _), + [14] = PINGROUP(14, qup03, qspi_clk, sdc4_clk, mdp_vsync, phase_flag, ddr_pxi0, _, _, _), + [15] = PINGROUP(15, qup03, qspi_cs, tb_trig, phase_flag, qdss_cti, ddr_pxi0, _, _, _), + [16] = PINGROUP(16, qup04, qspi_data, sdc42, mdp_vsync, phase_flag, qdss_cti, _, _, _), + [17] = PINGROUP(17, qup04, qspi_data, sdc43, _, phase_flag, _, _, _, _), + [18] = PINGROUP(18, qup04, _, phase_flag, qdss_cti, _, _, _, _, _), + [19] = PINGROUP(19, qup04, qspi_cs, sdc4_cmd, _, phase_flag, qdss_cti, _, _, _), + [20] = PINGROUP(20, qup05, cci_timer0, _, qdss, _, _, _, _, _), + [21] = PINGROUP(21, qup05, cci_timer1, _, qdss, _, _, _, _, _), + [22] = PINGROUP(22, qup05, _, qdss, _, _, _, _, _, _), + [23] = PINGROUP(23, qup05, _, qdss, _, _, _, _, _, _), + [24] = PINGROUP(24, qup06, _, qdss, _, _, _, _, _, _), + [25] = PINGROUP(25, qup06, _, qdss, _, _, _, _, _, _), + [26] = PINGROUP(26, qup06, host2wlan_sol, _, qdss, _, _, _, _, _), + [27] = PINGROUP(27, qup06, _, qdss, _, _, _, _, _, _), + [28] = PINGROUP(28, qup07, _, qdss, _, _, _, _, _, _), + [29] = PINGROUP(29, qup07, qdss, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup07, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup07, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup10, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup10, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup10, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup10, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup11, ibi_i3c, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup11, ibi_i3c, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup11, qup14, dbg_out, _, _, _, _, _, _), + [39] = PINGROUP(39, qup11, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup12, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup12, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup12, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup12, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup13, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup13, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup13, edp_lcd, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup13, dp_hot, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup14, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, qup14, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, qup14, qup16, _, _, _, _, _, _, _), + [51] = PINGROUP(51, qup14, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup15, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup15, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup15, qup14, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup15, qup14, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup16, ddr_bist, phase_flag, _, _, _, _, _, _), + [57] = PINGROUP(57, qup16, ddr_bist, phase_flag, _, _, _, _, _, _), + [58] = PINGROUP(58, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _), + [59] = PINGROUP(59, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _), + [60] = PINGROUP(60, qup17, edp_hot, _, phase_flag, _, _, _, _, _), + [61] = PINGROUP(61, qup17, sd_write, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _, _), + [62] = PINGROUP(62, qup17, qup16, phase_flag, _, _, _, _, _, _), + [63] = PINGROUP(63, qup17, qup16, phase_flag, _, _, _, _, _, _), + [64] = PINGROUP(64, cam_mclk, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, cam_mclk, tgu_ch0, _, _, _, _, _, _, _), + [66] = PINGROUP(66, cam_mclk, pll_bypassnl, tgu_ch1, _, _, _, _, _, _), + [67] = PINGROUP(67, cam_mclk, pll_reset, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cci_i2c, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, cci_i2c, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_i2c, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cci_i2c, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, cci_i2c, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cci_i2c, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cci_i2c, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, cci_i2c, gcc_gp1, _, _, _, _, _, _, _), + [77] = PINGROUP(77, cci_timer2, gcc_gp2, _, atest_usb13, atest_char0, _, _, _, _), + [78] = PINGROUP(78, cci_timer3, cci_async, gcc_gp3, _, atest_usb12, atest_char1, _, _, _), + [79] = PINGROUP(79, cci_timer4, cci_async, pcie1_clkreqn, mdp_vsync, jitter_bist, atest_usb11, atest_char2, _, _), + [80] = PINGROUP(80, mdp_vsync, vfr_0, mdp_vsync0, mdp_vsync1, mdp_vsync4, pll_bist, atest_usb10, atest_char3, _), + [81] = PINGROUP(81, mdp_vsync, dp_lcd, mdp_vsync2, mdp_vsync3, mdp_vsync5, atest_usb1, atest_char, _, _), + [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, usb2phy_ac, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, usb2phy_ac, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, pcie0_clkreqn, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_mclk, cci_async, _, _, _, _, _, _, _), + [94] = PINGROUP(94, lpass_slimbus, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, lpass_slimbus, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, pri_mi2s, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mi2s0_sck, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, mi2s0_data0, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, mi2s0_data1, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mi2s0_ws, _, vsense_trigger, _, _, _, _, _, _), + [101] = PINGROUP(101, mi2s2_sck, _, qdss, _, _, _, _, _, _), + [102] = PINGROUP(102, mi2s2_data0, _, _, qdss, _, _, _, _, _), + [103] = PINGROUP(103, mi2s2_ws, vfr_1, _, _, qdss, _, atest_usb03, _, _), + [104] = PINGROUP(104, mi2s2_data1, _, _, qdss, _, atest_usb02, _, _, _), + [105] = PINGROUP(105, sec_mi2s, mi2s1_data1, audio_ref, gcc_gp1, _, qdss, atest_usb01, _, _), + [106] = PINGROUP(106, mi2s1_sck, gcc_gp2, _, qdss, atest_usb00, _, _, _, _), + [107] = PINGROUP(107, mi2s1_data0, gcc_gp3, _, qdss, atest_usb0, _, _, _, _), + [108] = PINGROUP(108, mi2s1_ws, _, qdss, _, _, _, _, _, _), + [109] = PINGROUP(109, uim1_data, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, uim1_clk, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, uim1_reset, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, uim1_present, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, uim0_data, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, uim0_clk, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, uim0_reset, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, uim0_present, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, mss_grfc0, cmu_rng3, phase_flag, _, _, _, _, _), + [118] = PINGROUP(118, _, mss_grfc1, cmu_rng2, phase_flag, _, _, _, _, _), + [119] = PINGROUP(119, _, mss_grfc2, cmu_rng1, phase_flag, _, _, _, _, _), + [120] = PINGROUP(120, _, mss_grfc3, cmu_rng0, phase_flag, _, _, _, _, _), + [121] = PINGROUP(121, _, mss_grfc4, cri_trng0, phase_flag, _, _, _, _, _), + [122] = PINGROUP(122, _, mss_grfc5, cri_trng1, phase_flag, _, _, _, _, _), + [123] = PINGROUP(123, _, mss_grfc6, prng_rosc, phase_flag, _, _, _, _, _), + [124] = PINGROUP(124, _, mss_grfc7, cri_trng, phase_flag, _, _, _, _, _), + [125] = PINGROUP(125, _, mss_grfc8, phase_flag, _, _, _, _, _, _), + [126] = PINGROUP(126, _, mss_grfc9, phase_flag, _, _, _, _, _, _), + [127] = PINGROUP(127, coex_uart1, mss_grfc10, phase_flag, _, _, _, _, _, _), + [128] = PINGROUP(128, coex_uart1, mss_grfc11, phase_flag, _, _, _, _, _, _), + [129] = PINGROUP(129, nav_gpio0, phase_flag, _, _, _, _, _, _, _), + [130] = PINGROUP(130, nav_gpio1, phase_flag, _, _, _, _, _, _, _), + [131] = PINGROUP(131, mss_grfc12, nav_gpio2, pa_indicator, phase_flag, _, _, _, _, _), + [132] = PINGROUP(132, mss_grfc0, phase_flag, _, _, _, _, _, _, _), + [133] = PINGROUP(133, qlink0_request, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, qlink0_enable, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, qlink0_wmss, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, qlink1_request, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, qlink1_enable, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, qlink1_wmss, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, usb_phy, pll_clk, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _), + [175] = UFS_RESET(ufs_reset, 0x1be000), + [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0), + [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6), + [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3), + [179] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0), + [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6), + [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3), + [182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sc7280_pinctrl = { + .pins = sc7280_pins, + .npins = ARRAY_SIZE(sc7280_pins), + .functions = sc7280_functions, + .nfunctions = ARRAY_SIZE(sc7280_functions), + .groups = sc7280_groups, + .ngroups = ARRAY_SIZE(sc7280_groups), + .ngpios = 176, +}; + +static int sc7280_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc7280_pinctrl); +} + +static const struct of_device_id sc7280_pinctrl_of_match[] = { + { .compatible = "qcom,sc7280-pinctrl", }, + { }, +}; + +static struct platform_driver sc7280_pinctrl_driver = { + .driver = { + .name = "sc7280-pinctrl", + .of_match_table = sc7280_pinctrl_of_match, + }, + .probe = sc7280_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc7280_pinctrl_init(void) +{ + return platform_driver_register(&sc7280_pinctrl_driver); +} +arch_initcall(sc7280_pinctrl_init); + +static void __exit sc7280_pinctrl_exit(void) +{ + platform_driver_unregister(&sc7280_pinctrl_driver); +} +module_exit(sc7280_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sc7280 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match); From 6de7ed693c631d4689acfe90c434147598d75543 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 10 Nov 2020 14:22:55 +0800 Subject: [PATCH 61/80] pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller A100's pin starts with PB, so it should start with 1. Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller") Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/9db51667bf9065be55beafd56e5c319e3bbe8310.1604988979.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c index 19cfd1e76ee2..e69f6da40dc0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -677,7 +677,7 @@ static const struct sunxi_desc_pin a100_pins[] = { SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)), }; -static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6}; +static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7}; static const struct sunxi_pinctrl_desc a100_pinctrl_data = { .pins = a100_pins, From fd5198dde36af5ae54940c3ea6923fa6459da88c Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 10 Nov 2020 14:23:44 +0800 Subject: [PATCH 62/80] pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON The interrupt descriptor cannot be found in the interrupt processing function, and this situation cannot happen when the system is running normally. It doesn't seem right to return directly to the status of not handling gic. In this case, it must be a bug, let's mark it with WARN_ON. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/470ebae22fc5434ad5409c4f6e29255467b3cef6.1604988979.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 8e792f8e2dc9..9d8b59dafa4b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1139,8 +1139,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) if (irq == pctl->irq[bank]) break; - if (bank == pctl->desc->irq_banks) - return; + WARN_ON(bank == pctl->desc->irq_banks); reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); val = readl(pctl->membase + reg); From a1158e36f876f6269978a4176e3a1d48d27fe7a1 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 10 Nov 2020 14:24:40 +0800 Subject: [PATCH 63/80] pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler It is found on many allwinner soc that there is a low probability that the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This will cause the interrupt status of a gpio bank to always be active on gic, preventing gic from responding to other spi interrupts correctly. So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler(). Signed-off-by: Yangtao Li Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9d8b59dafa4b..dc8d39ae045b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1141,20 +1141,22 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) WARN_ON(bank == pctl->desc->irq_banks); + chained_irq_enter(chip, desc); + reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); val = readl(pctl->membase + reg); if (val) { int irqoffset; - chained_irq_enter(chip, desc); for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { int pin_irq = irq_find_mapping(pctl->domain, bank * IRQ_PER_BANK + irqoffset); generic_handle_irq(pin_irq); } - chained_irq_exit(chip, desc); } + + chained_irq_exit(chip, desc); } static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, From b6071c8914648703e7c7f7fd9d06a16a0ad030e9 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 13 Nov 2020 15:24:29 +0200 Subject: [PATCH 64/80] pinctrl: at91-pio4: add support for fewer lines on last PIO bank Some products, like sama7g5, do not have a full last bank of PIO lines. In this case for example, sama7g5 only has 8 lines for the PE bank. PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines. To cope with this situation, added a data attribute that is product dependent, to specify the number of lines of the last bank. In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK, adjust the total number of lines accordingly. This will avoid advertising 160 lines instead of the actual 136, as this product supports, and to avoid reading/writing to invalid register addresses. Signed-off-by: Eugen Hristev Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 157fea808629..36c6078b93b3 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -71,8 +71,15 @@ /* Custom pinconf parameters */ #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) +/** + * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct + * @nbanks: number of PIO banks + * @last_bank_count: number of lines in the last bank (can be less than + * the rest of the banks). + */ struct atmel_pioctrl_data { unsigned nbanks; + unsigned last_bank_count; }; struct atmel_group { @@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pctrl_pm_ops = { * We can have up to 16 banks. */ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { - .nbanks = 4, + .nbanks = 4, + .last_bank_count = ATMEL_PIO_NPINS_PER_BANK, }; static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { - .nbanks = 5, + .nbanks = 5, + .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ }; static const struct of_device_id atmel_pctrl_of_match[] = { @@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl_data = match->data; atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; + /* if last bank has limited number of pins, adjust accordingly */ + if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { + atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; + atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; + } atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(atmel_pioctrl->reg_base)) From ce4d7816c827a35516ecd89303847e658d67b738 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Fri, 13 Nov 2020 15:51:49 +0100 Subject: [PATCH 65/80] dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver This adds DT bindings for the Microsemi/Microchip SGPIO controller, bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and mscc,luton-sgpio. Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201113145151.68900-2-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- .../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml new file mode 100644 index 000000000000..08325bf77a81 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi/Microchip Serial GPIO controller + +maintainers: + - Lars Povlsen + +description: | + By using a serial interface, the SIO controller significantly extend + the number of available GPIOs with a minimum number of additional + pins on the device. The primary purpose of the SIO controllers is to + connect control signals from SFP modules and to act as an LED + controller. + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - microchip,sparx5-sgpio + - mscc,ocelot-sgpio + - mscc,luton-sgpio + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + microchip,sgpio-port-ranges: + description: This is a sequence of tuples, defining intervals of + enabled ports in the serial input stream. The enabled ports must + match the hardware configuration in order for signals to be + properly written/read to/from the controller holding + registers. Being tuples, then number of arguments must be + even. The tuples mast be ordered (low, high) and are + inclusive. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "low" indicates start bit number of range + minimum: 0 + maximum: 31 + - description: | + "high" indicates end bit number of range + minimum: 0 + maximum: 31 + minItems: 1 + maxItems: 32 + + bus-frequency: + description: The sgpio controller frequency (Hz). This dictates + the serial bitstream speed, which again affects the latency in + getting control signals back and forth between external shift + registers. The speed must be no larger than half the system + clock, and larger than zero. + default: 12500000 + +patternProperties: + "^gpio@[0-1]$": + type: object + properties: + compatible: + const: microchip,sparx5-sgpio-bank + + reg: + description: | + The GPIO bank number. "0" is designates the input pin bank, + "1" the output bank. + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: | + Specifies the pin (port and bit) and flags. Note that the + SGIO pin is defined by *2* numbers, a port number between 0 + and 31, and a bit index, 0 to 3. The maximum bit number is + controlled indirectly by the "ngpios" property: (ngpios/32). + const: 3 + + ngpios: + description: The numbers of GPIO's exposed. This must be a + multiple of 32. + minimum: 32 + maximum: 128 + + required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - ngpios + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - microchip,sgpio-port-ranges + - "#address-cells" + - "#size-cells" + +examples: + - | + sgpio2: gpio@1101059c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x1101059c 0x100>; + microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; + bus-frequency = <25000000>; + sgpio_in2: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out2: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; From 7e5ea974e61c8dd0832dcfe931ef959b2eb02587 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Fri, 13 Nov 2020 15:51:50 +0100 Subject: [PATCH 66/80] pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO (SGPIO) device used in various SoC's. The driver is added as a pinctrl driver, albeit only having just GPIO support currently. The hardware supports other functions that will be added following. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20201113145151.68900-3-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 16 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-microchip-sgpio.c | 709 ++++++++++++++++++++++ 4 files changed, 727 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-microchip-sgpio.c diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..75a00dfa824a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2117,6 +2117,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported T: git git://github.com/microchip-ung/linux-upstream.git F: arch/arm64/boot/dts/microchip/ +F: drivers/pinctrl/pinctrl-microchip-sgpio.c N: sparx5 ARM/MIOA701 MACHINE SUPPORT diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 815095326e2d..9b8ed7516355 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -374,6 +374,22 @@ config PINCTRL_OCELOT select OF_GPIO select REGMAP_MMIO +config PINCTRL_MICROCHIP_SGPIO + bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + depends on HAS_IOMEM + select GPIOLIB + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + help + Support for the serial GPIO interface used on Microsemi and + Microchip SoC's. By using a serial interface, the SIO + controller significantly extends the number of available + GPIOs with a minimum number of additional pins on the + device. The primary purpose of the SIO controller is to + connect control signals from SFP modules and to act as an + LED controller. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f53933b2ff02..c9fcfafc45c7 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o +obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-y += actions/ diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c new file mode 100644 index 000000000000..d6c31cc7678e --- /dev/null +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Microsemi/Microchip SoCs serial gpio driver + * + * Author: Lars Povlsen + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinconf.h" + +#define SGPIO_BITS_PER_WORD 32 +#define SGPIO_MAX_BITS 4 +#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ + +enum { + REG_INPUT_DATA, + REG_PORT_CONFIG, + REG_PORT_ENABLE, + REG_SIO_CONFIG, + REG_SIO_CLOCK, + MAXREG +}; + +enum { + SGPIO_ARCH_LUTON, + SGPIO_ARCH_OCELOT, + SGPIO_ARCH_SPARX5, +}; + +struct sgpio_properties { + int arch; + u8 regoff[MAXREG]; +}; + +#define SGPIO_LUTON_AUTO_REPEAT BIT(5) +#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) +#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) +#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) + +#define SGPIO_OCELOT_AUTO_REPEAT BIT(10) +#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) +#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) +#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) + +#define SGPIO_SPARX5_AUTO_REPEAT BIT(6) +#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) +#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) +#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) + +const struct sgpio_properties properties_luton = { + .arch = SGPIO_ARCH_LUTON, + .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, +}; + +const struct sgpio_properties properties_ocelot = { + .arch = SGPIO_ARCH_OCELOT, + .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, +}; + +const struct sgpio_properties properties_sparx5 = { + .arch = SGPIO_ARCH_SPARX5, + .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, +}; + +static const char * const functions[] = { "gpio" }; + +struct sgpio_bank { + struct sgpio_priv *priv; + bool is_input; + struct gpio_chip gpio; + struct pinctrl_desc pctl_desc; +}; + +struct sgpio_priv { + struct device *dev; + struct sgpio_bank in; + struct sgpio_bank out; + u32 bitcount; + u32 ports; + u32 clock; + u32 __iomem *regs; + const struct sgpio_properties *properties; +}; + +struct sgpio_port_addr { + u8 port; + u8 bit; +}; + +static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, + struct sgpio_port_addr *addr) +{ + addr->port = pin / priv->bitcount; + addr->bit = pin % priv->bitcount; +} + +static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) +{ + u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + + return readl(reg); +} + +static inline void sgpio_writel(struct sgpio_priv *priv, + u32 val, u32 rno, u32 off) +{ + u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + + writel(val, reg); +} + +static inline void sgpio_clrsetbits(struct sgpio_priv *priv, + u32 rno, u32 off, u32 clear, u32 set) +{ + u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + u32 val = readl(reg); + + val &= ~clear; + val |= set; + + writel(val, reg); +} + +static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) +{ + int width = priv->bitcount - 1; + u32 clr, set; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + clr = SGPIO_LUTON_PORT_WIDTH; + set = SGPIO_LUTON_AUTO_REPEAT | + FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); + break; + case SGPIO_ARCH_OCELOT: + clr = SGPIO_OCELOT_PORT_WIDTH; + set = SGPIO_OCELOT_AUTO_REPEAT | + FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); + break; + case SGPIO_ARCH_SPARX5: + clr = SGPIO_SPARX5_PORT_WIDTH; + set = SGPIO_SPARX5_AUTO_REPEAT | + FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); + break; + default: + return; + } + sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); +} + +static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) +{ + u32 clr, set; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + clr = SGPIO_LUTON_CLK_FREQ; + set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); + break; + case SGPIO_ARCH_OCELOT: + clr = SGPIO_OCELOT_CLK_FREQ; + set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); + break; + case SGPIO_ARCH_SPARX5: + clr = SGPIO_SPARX5_CLK_FREQ; + set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); + break; + default: + return; + } + sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); +} + +static void sgpio_output_set(struct sgpio_priv *priv, + struct sgpio_port_addr *addr, + int value) +{ + unsigned int bit = SGPIO_SRC_BITS * addr->bit; + u32 clr, set; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); + set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); + break; + case SGPIO_ARCH_OCELOT: + clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); + set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); + break; + case SGPIO_ARCH_SPARX5: + clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); + set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); + break; + default: + return; + } + sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); +} + +static int sgpio_output_get(struct sgpio_priv *priv, + struct sgpio_port_addr *addr) +{ + u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); + unsigned int bit = SGPIO_SRC_BITS * addr->bit; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); + break; + case SGPIO_ARCH_OCELOT: + val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); + break; + case SGPIO_ARCH_SPARX5: + val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); + break; + default: + val = 0; + break; + } + return !!(val & BIT(bit)); +} + +static int sgpio_input_get(struct sgpio_priv *priv, + struct sgpio_port_addr *addr) +{ + return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); +} + +static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + u32 param = pinconf_to_config_param(*config); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + int val; + + sgpio_pin_to_addr(priv, pin, &addr); + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + val = bank->is_input; + break; + + case PIN_CONFIG_OUTPUT_ENABLE: + val = !bank->is_input; + break; + + case PIN_CONFIG_OUTPUT: + if (bank->is_input) + return -EINVAL; + val = sgpio_output_get(priv, &addr); + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, val); + + return 0; +} + +static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + int cfg, err = 0; + u32 param, arg; + + sgpio_pin_to_addr(priv, pin, &addr); + + for (cfg = 0; cfg < num_configs; cfg++) { + param = pinconf_to_config_param(configs[cfg]); + arg = pinconf_to_config_argument(configs[cfg]); + + switch (param) { + case PIN_CONFIG_OUTPUT: + if (bank->is_input) + return -EINVAL; + sgpio_output_set(priv, &addr, arg); + break; + + default: + err = -ENOTSUPP; + } + } + + return err; +} + +static const struct pinconf_ops sgpio_confops = { + .is_generic = true, + .pin_config_get = sgpio_pinconf_get, + .pin_config_set = sgpio_pinconf_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) +{ + return 1; +} + +static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return functions[0]; +} + +static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned *const num_groups) +{ + *groups = functions; + *num_groups = ARRAY_SIZE(functions); + + return 0; +} + +static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + return 0; +} + +static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + return (input == bank->is_input) ? 0 : -EINVAL; +} + +static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(priv, offset, &addr); + + if ((priv->ports & BIT(addr.port)) == 0) { + dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", + addr.port, addr.bit); + return -EINVAL; + } + + return 0; +} + +static const struct pinmux_ops sgpio_pmx_ops = { + .get_functions_count = sgpio_get_functions_count, + .get_function_name = sgpio_get_function_name, + .get_function_groups = sgpio_get_function_groups, + .set_mux = sgpio_pinmux_set_mux, + .gpio_set_direction = sgpio_gpio_set_direction, + .gpio_request_enable = sgpio_gpio_request_enable, +}; + +static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + return bank->pctl_desc.npins; +} + +static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + return bank->pctl_desc.pins[group].name; +} + +static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + *pins = &bank->pctl_desc.pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops sgpio_pctl_ops = { + .get_groups_count = sgpio_pctl_get_groups_count, + .get_group_name = sgpio_pctl_get_group_name, + .get_group_pins = sgpio_pctl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + + /* Fixed-position function */ + return bank->is_input ? 0 : -EINVAL; +} + +static int microchip_sgpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + + /* Fixed-position function */ + if (bank->is_input) + return -EINVAL; + + sgpio_pin_to_addr(priv, gpio, &addr); + + sgpio_output_set(priv, &addr, value); + + return 0; +} + +static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + + return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static void microchip_sgpio_set_value(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + microchip_sgpio_direction_output(gc, gpio, value); +} + +static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(priv, gpio, &addr); + + return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); +} + +static int microchip_sgpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + struct sgpio_priv *priv = bank->priv; + int pin; + + /* + * Note that the SGIO pin is defined by *2* numbers, a port + * number between 0 and 31, and a bit index, 0 to 3. + */ + if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || + gpiospec->args[1] > priv->bitcount) + return -EINVAL; + + pin = gpiospec->args[1] + gpiospec->args[0] * priv->bitcount; + + if (pin > gc->ngpio) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[2]; + + return pin; +} + +static int microchip_sgpio_get_ports(struct sgpio_priv *priv) +{ + const char *range_property_name = "microchip,sgpio-port-ranges"; + struct device *dev = priv->dev; + u32 range_params[64]; + int i, nranges, ret; + + /* Calculate port mask */ + nranges = device_property_count_u32(dev, range_property_name); + if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { + dev_err(dev, "%s port range: '%s' property\n", + nranges == -EINVAL ? "Missing" : "Invalid", + range_property_name); + return -EINVAL; + } + + ret = device_property_read_u32_array(dev, range_property_name, + range_params, nranges); + if (ret) { + dev_err(dev, "failed to parse '%s' property: %d\n", + range_property_name, ret); + return ret; + } + for (i = 0; i < nranges; i += 2) { + int start, end; + + start = range_params[i]; + end = range_params[i + 1]; + if (start > end || end >= SGPIO_BITS_PER_WORD) { + dev_err(dev, "Ill-formed port-range [%d:%d]\n", + start, end); + } + priv->ports |= GENMASK(end, start); + } + + return 0; +} + +static int microchip_sgpio_register_bank(struct device *dev, + struct sgpio_priv *priv, + struct fwnode_handle *fwnode, + int bankno) +{ + struct pinctrl_pin_desc *pins; + struct pinctrl_desc *pctl_desc; + struct pinctrl_dev *pctldev; + struct sgpio_bank *bank; + struct gpio_chip *gc; + u32 ngpios; + int i, ret; + + /* Get overall bank struct */ + bank = (bankno == 0) ? &priv->in : &priv->out; + bank->priv = priv; + + if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { + dev_info(dev, "failed to get number of gpios for bank%d\n", + bankno); + ngpios = 64; + } + + priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; + if (priv->bitcount > SGPIO_MAX_BITS) { + dev_err(dev, "Bit width exceeds maximum (%d)\n", + SGPIO_MAX_BITS); + return -EINVAL; + } + + pctl_desc = &bank->pctl_desc; + pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", + dev_name(dev), + bank->is_input ? "in" : "out"); + pctl_desc->pctlops = &sgpio_pctl_ops; + pctl_desc->pmxops = &sgpio_pmx_ops; + pctl_desc->confops = &sgpio_confops; + pctl_desc->owner = THIS_MODULE; + + pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pctl_desc->npins = ngpios; + pctl_desc->pins = pins; + + for (i = 0; i < ngpios; i++) { + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(priv, i, &addr); + + pins[i].number = i; + pins[i].name = devm_kasprintf(dev, GFP_KERNEL, + "SGPIO_%c_p%db%d", + bank->is_input ? 'I' : 'O', + addr.port, addr.bit); + if (!pins[i].name) + return -ENOMEM; + } + + pctldev = devm_pinctrl_register(dev, pctl_desc, bank); + if (IS_ERR(pctldev)) + return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); + + gc = &bank->gpio; + gc->label = pctl_desc->name; + gc->parent = dev; + gc->of_node = to_of_node(fwnode); + gc->owner = THIS_MODULE; + gc->get_direction = microchip_sgpio_get_direction; + gc->direction_input = microchip_sgpio_direction_input; + gc->direction_output = microchip_sgpio_direction_output; + gc->get = microchip_sgpio_get_value; + gc->set = microchip_sgpio_set_value; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->of_xlate = microchip_sgpio_of_xlate; + gc->of_gpio_n_cells = 3; + gc->base = -1; + gc->ngpio = ngpios; + + ret = devm_gpiochip_add_data(dev, gc, bank); + if (ret) + dev_err(dev, "Failed to register: ret %d\n", ret); + + return ret; +} + +static int microchip_sgpio_probe(struct platform_device *pdev) +{ + int div_clock = 0, ret, port, i, nbanks; + struct device *dev = &pdev->dev; + struct fwnode_handle *fwnode; + struct sgpio_priv *priv; + struct clk *clk; + u32 val; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); + + div_clock = clk_get_rate(clk); + if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) + priv->clock = 12500000; + if (priv->clock == 0 || priv->clock > (div_clock / 2)) { + dev_err(dev, "Invalid frequency %d\n", priv->clock); + return -EINVAL; + } + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + priv->properties = device_get_match_data(dev); + priv->in.is_input = true; + + /* Get rest of device properties */ + ret = microchip_sgpio_get_ports(priv); + if (ret) + return ret; + + nbanks = device_get_child_node_count(dev); + if (nbanks != 2) { + dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); + return -EINVAL; + } + + i = 0; + device_for_each_child_node(dev, fwnode) { + ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); + if (ret) + return ret; + } + + if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { + dev_err(dev, "Banks must have same GPIO count\n"); + return -ERANGE; + } + + sgpio_configure_bitstream(priv); + + val = max(2U, div_clock / priv->clock); + sgpio_configure_clock(priv, val); + + for (port = 0; port < SGPIO_BITS_PER_WORD; port++) + sgpio_writel(priv, 0, REG_PORT_CONFIG, port); + sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); + + return 0; +} + +static const struct of_device_id microchip_sgpio_gpio_of_match[] = { + { + .compatible = "microchip,sparx5-sgpio", + .data = &properties_sparx5, + }, { + .compatible = "mscc,luton-sgpio", + .data = &properties_luton, + }, { + .compatible = "mscc,ocelot-sgpio", + .data = &properties_ocelot, + }, { + /* sentinel */ + } +}; + +static struct platform_driver microchip_sgpio_pinctrl_driver = { + .driver = { + .name = "pinctrl-microchip-sgpio", + .of_match_table = microchip_sgpio_gpio_of_match, + .suppress_bind_attrs = true, + }, + .probe = microchip_sgpio_probe, +}; +builtin_platform_driver(microchip_sgpio_pinctrl_driver); From 552a9cc02b0e8a63d802b3a80ceefce0c89cee8a Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 25 Nov 2020 13:20:14 +0100 Subject: [PATCH 67/80] pinctrl: pinctrl-microchip-sgpio: Add OF config dependency The pinctrl-microchip-sgpio driver needs OF support, so add that to Kconfig. Reported-by: Randy Dunlap Signed-off-by: Lars Povlsen Acked-by: Randy Dunlap Link: https://lore.kernel.org/r/20201125122014.11237-1-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9b8ed7516355..94e49da49f5c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -376,11 +376,13 @@ config PINCTRL_OCELOT config PINCTRL_MICROCHIP_SGPIO bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + depends on OF depends on HAS_IOMEM select GPIOLIB select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS + select OF_GPIO help Support for the serial GPIO interface used on Microsemi and Microchip SoC's. By using a serial interface, the SIO From 43bb48c38e817b5f89fce340f49436a605e47e66 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Wed, 18 Nov 2020 20:10:00 +0200 Subject: [PATCH 68/80] pinctrl: actions: pinctrl-s500: Constify s500_padinfo[] s500_padinfo[] is never modified and should be made 'const' to allow the compiler to optimize code generation, i.e. put it in the text section instead of the data section. Before: text data bss dec hex filename 12503 5088 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o After: text data bss dec hex filename 14435 3156 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/24505deb08d050eb4ce38f186f4037d7541ea217.1605722628.git.cristian.ciocaltea@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-s500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/actions/pinctrl-s500.c b/drivers/pinctrl/actions/pinctrl-s500.c index 38e30914af6e..ced778079b76 100644 --- a/drivers/pinctrl/actions/pinctrl-s500.c +++ b/drivers/pinctrl/actions/pinctrl-s500.c @@ -1485,7 +1485,7 @@ static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1); static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1); /* Pad info table */ -static struct owl_padinfo s500_padinfo[NUM_PADS] = { +static const struct owl_padinfo s500_padinfo[NUM_PADS] = { [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS), [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN), [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), From 89cce2b3f247a434ee174ab6803698041df98014 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Thu, 19 Nov 2020 09:12:19 +0800 Subject: [PATCH 69/80] pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe() if of_find_device_by_node() succeed, pinctrl_falcon_probe() doesn't have a corresponding put_device(). Thus add put_device() to fix the exception handling for this function implementation. Fixes: e316cb2b16bb ("OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC") Signed-off-by: Yu Kuai Link: https://lore.kernel.org/r/20201119011219.2248232-1-yukuai3@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-falcon.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index 62c02b969327..7521a924dffb 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -431,24 +431,28 @@ static int pinctrl_falcon_probe(struct platform_device *pdev) /* load and remap the pad resources of the different banks */ for_each_compatible_node(np, NULL, "lantiq,pad-falcon") { - struct platform_device *ppdev = of_find_device_by_node(np); const __be32 *bank = of_get_property(np, "lantiq,bank", NULL); struct resource res; + struct platform_device *ppdev; u32 avail; int pins; if (!of_device_is_available(np)) continue; - if (!ppdev) { - dev_err(&pdev->dev, "failed to find pad pdev\n"); - continue; - } if (!bank || *bank >= PORTS) continue; if (of_address_to_resource(np, 0, &res)) continue; + + ppdev = of_find_device_by_node(np); + if (!ppdev) { + dev_err(&pdev->dev, "failed to find pad pdev\n"); + continue; + } + falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); + put_device(&ppdev->dev); if (IS_ERR(falcon_info.clk[*bank])) { dev_err(&ppdev->dev, "failed to get clock\n"); of_node_put(np); From 517c3f5a8683c950efe17aa01e55efb3b0f2c770 Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Fri, 20 Nov 2020 17:30:58 +0800 Subject: [PATCH 70/80] pinctrl: mtk: Fix low level output voltage issue This patch is used to fix low level output voltage issue. A pin is changed from input pull-up to output high. The Dout value of the pin is default as 0. If we change the direction of the pin before the dout value of the pin, It maybe produce a low level output voltage between "input pull-up" and "output high". Signed-off-by: Zhiyong Tao Link: https://lore.kernel.org/r/20201120093058.7248-2-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-paris.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 623af4410b07..039ce9be19c5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -247,13 +247,13 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg); break; case PIN_CONFIG_OUTPUT: - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, - MTK_OUTPUT); + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, + arg); if (err) goto err; - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, - arg); + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, + MTK_OUTPUT); break; case PIN_CONFIG_INPUT_SCHMITT: case PIN_CONFIG_INPUT_SCHMITT_ENABLE: From 0a03658d222a99b192a7f84e41e8af197a87259e Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 24 Nov 2020 17:17:03 +0800 Subject: [PATCH 71/80] pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error If CONFIG_HAS_IOMEM is not set, devm_platform_ioremap_resource() will be not built in drivers/base/platform.c and then there exists a build error about undefined reference to "devm_platform_ioremap_resource" in pinctrl-at91-pio4.c under COMPILE_TEST and CONFIG_PINCTRL_AT91PIO4, make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix it. Reported-by: kernel test robot Signed-off-by: Tiezhu Yang Link: https://lore.kernel.org/r/1606209423-4742-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 94e49da49f5c..5946f8077e71 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -82,6 +82,7 @@ config PINCTRL_AT91 config PINCTRL_AT91PIO4 bool "AT91 PIO4 pinctrl driver" depends on OF + depends on HAS_IOMEM depends on ARCH_AT91 || COMPILE_TEST select PINMUX select GENERIC_PINCONF From d05b7691904b4b754b8469aa98a6b82523fdadad Mon Sep 17 00:00:00 2001 From: Zou Wei Date: Tue, 24 Nov 2020 19:42:53 +0800 Subject: [PATCH 72/80] pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword Fix the following sparse warnings: drivers/pinctrl/pinctrl-microchip-sgpio.c:63:31: warning: symbol 'properties_luton' was not declared. Should it be static? drivers/pinctrl/pinctrl-microchip-sgpio.c:68:31: warning: symbol 'properties_ocelot' was not declared. Should it be static? drivers/pinctrl/pinctrl-microchip-sgpio.c:73:31: warning: symbol 'properties_sparx5' was not declared. Should it be static? Signed-off-by: Zou Wei Link: https://lore.kernel.org/r/1606218173-3722-1-git-send-email-zou_wei@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-microchip-sgpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index d6c31cc7678e..e1824197318e 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -60,17 +60,17 @@ struct sgpio_properties { #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) -const struct sgpio_properties properties_luton = { +static const struct sgpio_properties properties_luton = { .arch = SGPIO_ARCH_LUTON, .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, }; -const struct sgpio_properties properties_ocelot = { +static const struct sgpio_properties properties_ocelot = { .arch = SGPIO_ARCH_OCELOT, .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, }; -const struct sgpio_properties properties_sparx5 = { +static const struct sgpio_properties properties_sparx5 = { .arch = SGPIO_ARCH_SPARX5, .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, }; From 4247e3f562619a05682b3d3d5d92d54ca46a2a43 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 26 Nov 2020 14:51:50 +0530 Subject: [PATCH 73/80] dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support Add support for the PMX55 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201126092151.1082697-1-vkoul@kernel.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index c3d1914381ae..7648ab00f4e2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -29,6 +29,7 @@ PMIC's from Qualcomm. "qcom,pm8150b-gpio" "qcom,pm6150-gpio" "qcom,pm6150l-gpio" + "qcom,pmx55-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -110,6 +111,8 @@ to specify in a pin configuration subnode: gpio1-gpio12 for pm8150l (hole on gpio7) gpio1-gpio10 for pm6150 gpio1-gpio12 for pm6150l + gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 + and gpio11) - function: Usage: required From ceb58de4365fff8b503b1e6ba7d1110613adb305 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 26 Nov 2020 14:51:51 +0530 Subject: [PATCH 74/80] pinctrl: qcom-pmic-gpio: Add support for pmx55 PM55 pmic support gpio controller so add compatible and comment for gpio holes Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201126092151.1082697-2-vkoul@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 17441388ce8f..9801c717e311 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1129,6 +1129,8 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, + /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ + { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, { }, }; From 700a51192d09a2f7bbd49ab9b7e7920ecdc5c1bf Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 16:34:42 +0000 Subject: [PATCH 75/80] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings Add device tree binding Documentation details for Qualcomm SM8250 LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201202163443.26499-2-srinivas.kandagatla@linaro.org Signed-off-by: Linus Walleij --- .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..e47ebf934daf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8250-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 14 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 14>; + }; From 6e261d1090d6db0e9dd22978b6f38a2c58558a3f Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 16:34:43 +0000 Subject: [PATCH 76/80] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org [Add some dependencies] Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 11 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++++++++++++++++++++++ 3 files changed, 707 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 54412f270738..a003776506d0 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -265,4 +265,15 @@ config PINCTRL_SM8250 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_LPASS_LPI + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + select PINMUX + select PINCONF + select GENERIC_PINCONF + depends on GPIOLIB + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SoCs. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index c28a33c48aa5..91875a3f5ac4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c new file mode 100644 index 000000000000..369ee20a7ea9 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../core.h" +#include "../pinctrl-utils.h" + +#define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_TLMM_REG_OFFSET 0x1000 +#define LPI_SLEW_RATE_MAX 0x03 +#define LPI_SLEW_BITS_SIZE 0x02 +#define LPI_SLEW_RATE_MASK GENMASK(1, 0) +#define LPI_GPIO_CFG_REG 0x00 +#define LPI_GPIO_PULL_MASK GENMASK(1, 0) +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2) +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6) +#define LPI_GPIO_OE_MASK BIT(9) +#define LPI_GPIO_VALUE_REG 0x04 +#define LPI_GPIO_VALUE_IN_MASK BIT(0) +#define LPI_GPIO_VALUE_OUT_MASK BIT(1) + +#define LPI_GPIO_BIAS_DISABLE 0x0 +#define LPI_GPIO_PULL_DOWN 0x1 +#define LPI_GPIO_KEEPER 0x2 +#define LPI_GPIO_PULL_UP 0x3 +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1) +#define NO_SLEW -1 + +#define LPI_FUNCTION(fname) \ + [LPI_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .pin = id, \ + .slew_offset = soff, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + } + +struct lpi_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + unsigned int pin; + /* Bit offset in slew register for SoundWire pins only */ + int slew_offset; + unsigned int *funcs; + unsigned int nfuncs; +}; + +struct lpi_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +struct lpi_pinctrl_variant_data { + const struct pinctrl_pin_desc *pins; + int npins; + const struct lpi_pingroup *groups; + int ngroups; + const struct lpi_function *functions; + int nfunctions; +}; + +#define MAX_LPI_NUM_CLKS 2 + +struct lpi_pinctrl { + struct device *dev; + struct pinctrl_dev *ctrl; + struct gpio_chip chip; + struct pinctrl_desc desc; + char __iomem *tlmm_base; + char __iomem *slew_base; + struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; + struct mutex slew_access_lock; + const struct lpi_pinctrl_variant_data *data; +}; + +/* sm8250 variant specific data */ +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), +}; + +enum sm8250_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const unsigned int gpio0_pins[] = { 0 }; +static const unsigned int gpio1_pins[] = { 1 }; +static const unsigned int gpio2_pins[] = { 2 }; +static const unsigned int gpio3_pins[] = { 3 }; +static const unsigned int gpio4_pins[] = { 4 }; +static const unsigned int gpio5_pins[] = { 5 }; +static const unsigned int gpio6_pins[] = { 6 }; +static const unsigned int gpio7_pins[] = { 7 }; +static const unsigned int gpio8_pins[] = { 8 }; +static const unsigned int gpio9_pins[] = { 9 }; +static const unsigned int gpio10_pins[] = { 10 }; +static const unsigned int gpio11_pins[] = { 11 }; +static const unsigned int gpio12_pins[] = { 12 }; +static const unsigned int gpio13_pins[] = { 13 }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; + +static const struct lpi_pingroup sm8250_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), +}; + +static const struct lpi_function sm8250_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static struct lpi_pinctrl_variant_data sm8250_lpi_data = { + .pins = sm8250_lpi_pins, + .npins = ARRAY_SIZE(sm8250_lpi_pins), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), +}; + +static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr) +{ + return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); +} + +static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, unsigned int val) +{ + iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + + return 0; +} + +static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->ngroups; +} + +static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->groups[group].name; +} + +static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->data->groups[group].pins; + *num_pins = pctrl->data->groups[group].npins; + + return 0; +} + +static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { + .get_groups_count = lpi_gpio_get_groups_count, + .get_group_name = lpi_gpio_get_group_name, + .get_group_pins = lpi_gpio_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->nfunctions; +} + +static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->functions[function].name; +} + +static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned *const num_qgroups) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->data->functions[function].groups; + *num_qgroups = pctrl->data->functions[function].ngroups; + + return 0; +} + +static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group_num) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct lpi_pingroup *g = &pctrl->data->groups[group_num]; + u32 val; + int i, pin = g->pin; + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); + lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + + return 0; +} + +static const struct pinmux_ops lpi_gpio_pinmux_ops = { + .get_functions_count = lpi_gpio_get_functions_count, + .get_function_name = lpi_gpio_get_function_name, + .get_function_groups = lpi_gpio_get_function_groups, + .set_mux = lpi_gpio_set_mux, +}; + +static int lpi_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + unsigned int param = pinconf_to_config_param(*config); + struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); + unsigned int arg = 0; + int is_out; + int pull; + u32 ctl_reg; + + ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + is_out = ctl_reg & LPI_GPIO_OE_MASK; + pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull == LPI_GPIO_BIAS_DISABLE) + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pull == LPI_GPIO_PULL_DOWN) + arg = 1; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + if (pull == LPI_GPIO_KEEPER) + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull == LPI_GPIO_PULL_UP) + arg = 1; + break; + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + if (is_out) + arg = 1; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, + unsigned long *configs, unsigned int nconfs) +{ + struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev); + unsigned int param, arg, pullup, strength; + bool value, output_enabled = false; + const struct lpi_pingroup *g; + unsigned long sval; + int i, slew_offset; + u32 val; + + g = &pctrl->data->groups[group]; + for (i = 0; i < nconfs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pullup = LPI_GPIO_BIAS_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + pullup = LPI_GPIO_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + pullup = LPI_GPIO_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + pullup = LPI_GPIO_PULL_UP; + break; + case PIN_CONFIG_INPUT_ENABLE: + output_enabled = false; + break; + case PIN_CONFIG_OUTPUT: + output_enabled = true; + value = arg; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + strength = arg; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg > LPI_SLEW_RATE_MAX) { + dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", + arg, group); + return -EINVAL; + } + + slew_offset = g->slew_offset; + if (slew_offset == NO_SLEW) + break; + + mutex_lock(&pctrl->slew_access_lock); + + sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); + sval |= arg << slew_offset; + iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + + mutex_unlock(&pctrl->slew_access_lock); + break; + default: + return -EINVAL; + } + } + + val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + + u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); + u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), + LPI_GPIO_OUT_STRENGTH_MASK); + u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); + + lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); + + if (output_enabled) { + val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + } + + return 0; +} + +static const struct pinconf_ops lpi_gpio_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = lpi_config_get, + .pin_config_group_set = lpi_config_set, +}; + +static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); + + return lpi_config_set(state->ctrl, pin, &config, 1); +} + +static int lpi_gpio_direction_output(struct gpio_chip *chip, + unsigned int pin, int val) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + + return lpi_config_set(state->ctrl, pin, &config, 1); +} + +static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + + return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & + LPI_GPIO_VALUE_IN_MASK; +} + +static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + + lpi_config_set(state->ctrl, pin, &config, 1); +} + +#ifdef CONFIG_DEBUG_FS +#include + +static unsigned int lpi_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static void lpi_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned int offset, + unsigned int gpio) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + struct pinctrl_pin_desc pindesc; + unsigned int func; + int is_out; + int drive; + int pull; + u32 ctl_reg; + + static const char * const pulls[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + pctldev = pctldev ? : state->ctrl; + pindesc = pctldev->desc->pins[offset]; + ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + is_out = ctl_reg & LPI_GPIO_OE_MASK; + + func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); + drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg); + pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); + + seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func); + seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); + seq_printf(s, " %s", pulls[pull]); +} + +static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned int gpio = chip->base; + unsigned int i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define lpi_gpio_dbg_show NULL +#endif + +static const struct gpio_chip lpi_gpio_template = { + .direction_input = lpi_gpio_direction_input, + .direction_output = lpi_gpio_direction_output, + .get = lpi_gpio_get, + .set = lpi_gpio_set, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .dbg_show = lpi_gpio_dbg_show, +}; + +static int lpi_pinctrl_probe(struct platform_device *pdev) +{ + const struct lpi_pinctrl_variant_data *data; + struct device *dev = &pdev->dev; + struct lpi_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctrl); + + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pctrl->data = data; + pctrl->dev = &pdev->dev; + + pctrl->clks[0].id = "core"; + pctrl->clks[1].id = "audio"; + + pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->tlmm_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), + "TLMM resource not provided\n"); + + pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pctrl->slew_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), + "Slew resource not provided\n"); + + ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Can't get clocks\n"); + + ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Can't enable clocks\n"); + + pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; + pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; + pctrl->desc.confops = &lpi_gpio_pinconf_ops; + pctrl->desc.owner = THIS_MODULE; + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = data->pins; + pctrl->desc.npins = data->npins; + pctrl->chip = lpi_gpio_template; + pctrl->chip.parent = dev; + pctrl->chip.base = -1; + pctrl->chip.ngpio = data->npins; + pctrl->chip.label = dev_name(dev); + pctrl->chip.of_gpio_n_cells = 2; + pctrl->chip.can_sleep = false; + + mutex_init(&pctrl->slew_access_lock); + + pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->ctrl)) { + ret = PTR_ERR(pctrl->ctrl); + dev_err(dev, "failed to add pin controller\n"); + goto err_pinctrl; + } + + ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "can't add gpio chip\n"); + goto err_pinctrl; + } + + return 0; + +err_pinctrl: + mutex_destroy(&pctrl->slew_access_lock); + clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); + + return ret; +} + +static int lpi_pinctrl_remove(struct platform_device *pdev) +{ + struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); + + mutex_destroy(&pctrl->slew_access_lock); + clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); + + return 0; +} + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8250-lpass-lpi-pinctrl", + .data = &sm8250_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From be2dc859abd4d7ad5e0f5d12ed767a3313b4e839 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 9 Dec 2020 15:27:51 +0100 Subject: [PATCH 77/80] pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5) This adds 'interrupt-controller' features for the signals available on the Microchip SGPIO controller, however only for controller versions on the Sparx5 platform (or later). Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20201209142753.683208-2-lars.povlsen@microchip.com [Select GPIOLIB_IRQCHIP in Kconfig] Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/pinctrl-microchip-sgpio.c | 187 +++++++++++++++++++++- 2 files changed, 186 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 5946f8077e71..67352375036f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -380,6 +380,7 @@ config PINCTRL_MICROCHIP_SGPIO depends on OF depends on HAS_IOMEM select GPIOLIB + select GPIOLIB_IRQCHIP select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index e1824197318e..f35edb0eac40 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -31,6 +31,11 @@ enum { REG_PORT_ENABLE, REG_SIO_CONFIG, REG_SIO_CLOCK, + REG_INT_POLARITY, + REG_INT_TRIGGER, + REG_INT_ACK, + REG_INT_ENABLE, + REG_INT_IDENT, MAXREG }; @@ -40,8 +45,13 @@ enum { SGPIO_ARCH_SPARX5, }; +enum { + SGPIO_FLAGS_HAS_IRQ = BIT(0), +}; + struct sgpio_properties { int arch; + int flags; u8 regoff[MAXREG]; }; @@ -60,6 +70,16 @@ struct sgpio_properties { #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) +#define SGPIO_MASTER_INTR_ENA BIT(0) + +#define SGPIO_INT_TRG_LEVEL 0 +#define SGPIO_INT_TRG_EDGE 1 +#define SGPIO_INT_TRG_EDGE_FALL 2 +#define SGPIO_INT_TRG_EDGE_RISE 3 + +#define SGPIO_TRG_LEVEL_HIGH 0 +#define SGPIO_TRG_LEVEL_LOW 1 + static const struct sgpio_properties properties_luton = { .arch = SGPIO_ARCH_LUTON, .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, @@ -72,7 +92,8 @@ static const struct sgpio_properties properties_ocelot = { static const struct sgpio_properties properties_sparx5 = { .arch = SGPIO_ARCH_SPARX5, - .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, + .flags = SGPIO_FLAGS_HAS_IRQ, + .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, }; static const char * const functions[] = { "gpio" }; @@ -107,6 +128,11 @@ static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, addr->bit = pin % priv->bitcount; } +static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) +{ + return bit + port * priv->bitcount; +} + static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) { u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; @@ -478,7 +504,7 @@ static int microchip_sgpio_of_xlate(struct gpio_chip *gc, gpiospec->args[1] > priv->bitcount) return -EINVAL; - pin = gpiospec->args[1] + gpiospec->args[0] * priv->bitcount; + pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); if (pin > gc->ngpio) return -EINVAL; @@ -527,6 +553,133 @@ static int microchip_sgpio_get_ports(struct sgpio_priv *priv) return 0; } +static void microchip_sgpio_irq_settype(struct irq_data *data, + int type, + int polarity) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct sgpio_bank *bank = gpiochip_get_data(chip); + unsigned int gpio = irqd_to_hwirq(data); + struct sgpio_port_addr addr; + u32 ena; + + sgpio_pin_to_addr(bank->priv, gpio, &addr); + + /* Disable interrupt while changing type */ + ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); + sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); + + /* Type value spread over 2 registers sets: low, high bit */ + sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, + BIT(addr.port), (!!(type & 0x1)) << addr.port); + sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit, + BIT(addr.port), (!!(type & 0x2)) << addr.port); + + if (type == SGPIO_INT_TRG_LEVEL) + sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, + BIT(addr.port), polarity << addr.port); + + /* Possibly re-enable interrupts */ + sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); +} + +static void microchip_sgpio_irq_setreg(struct irq_data *data, + int reg, + bool clear) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct sgpio_bank *bank = gpiochip_get_data(chip); + unsigned int gpio = irqd_to_hwirq(data); + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(bank->priv, gpio, &addr); + + if (clear) + sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); + else + sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); +} + +static void microchip_sgpio_irq_mask(struct irq_data *data) +{ + microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); +} + +static void microchip_sgpio_irq_unmask(struct irq_data *data) +{ + microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); +} + +static void microchip_sgpio_irq_ack(struct irq_data *data) +{ + microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); +} + +static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + type &= IRQ_TYPE_SENSE_MASK; + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: + irq_set_handler_locked(data, handle_edge_irq); + microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); + break; + case IRQ_TYPE_EDGE_RISING: + irq_set_handler_locked(data, handle_edge_irq); + microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); + break; + case IRQ_TYPE_EDGE_FALLING: + irq_set_handler_locked(data, handle_edge_irq); + microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_set_handler_locked(data, handle_level_irq); + microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); + break; + case IRQ_TYPE_LEVEL_LOW: + irq_set_handler_locked(data, handle_level_irq); + microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct irq_chip microchip_sgpio_irqchip = { + .name = "gpio", + .irq_mask = microchip_sgpio_irq_mask, + .irq_ack = microchip_sgpio_irq_ack, + .irq_unmask = microchip_sgpio_irq_unmask, + .irq_set_type = microchip_sgpio_irq_set_type, +}; + +static void sgpio_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *parent_chip = irq_desc_get_chip(desc); + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct sgpio_bank *bank = gpiochip_get_data(chip); + struct sgpio_priv *priv = bank->priv; + int bit, port, gpio; + long val; + + for (bit = 0; bit < priv->bitcount; bit++) { + val = sgpio_readl(priv, REG_INT_IDENT, bit); + if (!val) + continue; + + chained_irq_enter(parent_chip, desc); + + for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { + gpio = sgpio_addr_to_pin(priv, port, bit); + generic_handle_irq(irq_linear_revmap(chip->irq.domain, gpio)); + } + + chained_irq_exit(parent_chip, desc); + } +} + static int microchip_sgpio_register_bank(struct device *dev, struct sgpio_priv *priv, struct fwnode_handle *fwnode, @@ -608,6 +761,36 @@ static int microchip_sgpio_register_bank(struct device *dev, gc->base = -1; gc->ngpio = ngpios; + if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { + int irq = fwnode_irq_get(fwnode, 0); + + if (irq) { + struct gpio_irq_chip *girq = &gc->irq; + + girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip, + sizeof(microchip_sgpio_irqchip), + GFP_KERNEL); + if (!girq->chip) + return -ENOMEM; + girq->parent_handler = sgpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + /* Disable all individual pins */ + for (i = 0; i < SGPIO_MAX_BITS; i++) + sgpio_writel(priv, 0, REG_INT_ENABLE, i); + /* Master enable */ + sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); + } + } + ret = devm_gpiochip_add_data(dev, gc, bank); if (ret) dev_err(dev, "Failed to register: ret %d\n", ret); From 01a9350bdd49fb161502fc7a7ee03342d3a4d37a Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 9 Dec 2020 15:27:52 +0100 Subject: [PATCH 78/80] dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support This describe the new bindings for the added IRQ support in the pinctrl-microchip-sgpio driver. Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201209142753.683208-3-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/microchip,sparx5-sgpio.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml index 08325bf77a81..df0c83cb1c6e 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -91,6 +91,18 @@ patternProperties: controlled indirectly by the "ngpios" property: (ngpios/32). const: 3 + interrupts: + description: Specifies the sgpio IRQ (in parent controller) + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the pin (port and bit) and flags, as defined in + defined in include/dt-bindings/interrupt-controller/irq.h + const: 3 + ngpios: description: The numbers of GPIO's exposed. This must be a multiple of 32. @@ -118,6 +130,7 @@ required: examples: - | + #include sgpio2: gpio@1101059c { #address-cells = <1>; #size-cells = <0>; @@ -134,6 +147,9 @@ examples: gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out2: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; From a15f859694c2e36bc98e08c9635b27cf2239f4f2 Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Thu, 10 Dec 2020 21:59:02 +0800 Subject: [PATCH 79/80] pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1() Simplify the return expression. Signed-off-by: Zheng Yongjun Link: https://lore.kernel.org/r/20201210135902.1548-1-zhengyongjun3@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 7e950f5d62d0..7aeb552d16ce 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -488,14 +488,8 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc) { - int err; - - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, - MTK_DISABLE); - if (err) - return err; - - return 0; + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, + MTK_DISABLE); } EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); From 3df09cb8c92e2bdfb78c81f678f6990bd780f09a Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Thu, 10 Dec 2020 21:57:46 +0800 Subject: [PATCH 80/80] pinctrl/spear: simplify the return expression of spear300_pinctrl_probe() Simplify the return expression. Signed-off-by: Zheng Yongjun Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20201210135746.1492-1-zhengyongjun3@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-spear300.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c index e39913a18139..d53a04597cbe 100644 --- a/drivers/pinctrl/spear/pinctrl-spear300.c +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -654,8 +654,6 @@ static const struct of_device_id spear300_pinctrl_of_match[] = { static int spear300_pinctrl_probe(struct platform_device *pdev) { - int ret; - spear3xx_machdata.groups = spear300_pingroups; spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); spear3xx_machdata.functions = spear300_functions; @@ -669,11 +667,7 @@ static int spear300_pinctrl_probe(struct platform_device *pdev) pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; + return spear_pinctrl_probe(pdev, &spear3xx_machdata); } static struct platform_driver spear300_pinctrl_driver = {