Amlogic clock driver updates for 4.13
* Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJZMYA7AAoJEAFRo5MEFpTROkYQAIil0GjmG8azaiGXFWZ3LMf1 NupLsoH6Xd3nBnUmFR0DIHcH8ZadK5Io0+hWSVG0xopJzQS7+HWr/CfgQzdSiAa1 VDRSBZcoEmTBgiMkXfzN56HgUW1fz/bkQ2vZavQFsRJznkH2/kR09uL+/4BAY41k v4uYZwXLbEFfYEytFrHzppV43W2CnaMN1EH7GpKUvP3VldxpCt0yYAQZFS7k2wyJ If44bKN7sGma8g4IxrcrJ3AnpvE+OyLQAYgMyC1jm5WdRyEfWjqMNj54YL4cyIpl x6v+38oB5y39g7/k+YCvCugoY25DnVcdzCdtkAY8rWfoStOl9R67CVKshEIfG9WN WfRFLGBoC5RINvMEffjWSGPaGms1Cuk0UNWBOFNGzjwbc6Gw3OYZ4oXq4oSz8vby /GZcogEocizX343id/vX/6WZWz2Pp2hPzFi3OrqIB0xb2jrTFxZ2zqYOeEp/ChCx 5HHVOwfrkKTEw6vvGre7VcIBipZ/MYoTWVUO86cVOpj+QuK2wigsTjTQWU0dVh2w JOOGfk+3nrLoKzPpRLHdicc3FYv038RJcV35UqPOVmOhUh7+lGkRBTgEZunLXJI4 6qLmT49OFgSqLtx4u2R92xIdZYRGq5ysmIutUkmw69quWcfytsj9rZALp+2TWf8i 02pZYwcKJbrwHwK+Eqkk =8rsv -----END PGP SIGNATURE----- Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next Pull Amlogic clock driver updates from Jerome Brunet: * Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks * tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: Add EE 32K Clock for CEC clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 clk: meson: meson8b: mark clk81 as critical clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
This commit is contained in:
Stephen Boyd
commit
f6b3130919
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@ -278,20 +278,6 @@ static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
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{ /* sentinel */ },
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};
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static const struct clk_div_table cpu_div_table[] = {
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{ .val = 1, .div = 1 },
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{ .val = 2, .div = 2 },
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{ .val = 3, .div = 3 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 6 },
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{ .val = 4, .div = 8 },
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{ .val = 5, .div = 10 },
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{ .val = 6, .div = 12 },
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{ .val = 7, .div = 14 },
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{ .val = 8, .div = 16 },
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{ /* sentinel */ },
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};
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static struct meson_clk_pll gxbb_fixed_pll = {
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.m = {
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.reg_off = HHI_MPLL_CNTL,
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@ -612,21 +598,10 @@ static struct meson_clk_mpll gxbb_mpll2 = {
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};
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/*
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* FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
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* post-dividers and should be modeled with their respective PLLs via the
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* forthcoming coordinated clock rates feature
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* FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
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* and should be modeled with their respective PLLs via the forthcoming
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* coordinated clock rates feature
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*/
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static struct meson_clk_cpu gxbb_cpu_clk = {
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.reg_off = HHI_SYS_CPU_CLK_CNTL1,
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.div_table = cpu_div_table,
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.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk",
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.ops = &meson_clk_cpu_ops,
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.parent_names = (const char *[]){ "sys_pll" },
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.num_parents = 1,
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},
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};
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static u32 mux_table_clk81[] = { 6, 5, 7 };
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@ -676,7 +651,7 @@ static struct clk_gate gxbb_clk81 = {
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "mpeg_clk_div" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL),
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.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
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},
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};
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@ -951,6 +926,51 @@ static struct clk_mux gxbb_cts_i958 = {
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},
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};
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static struct clk_divider gxbb_32k_clk_div = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.shift = 0,
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.width = 14,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "32k_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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},
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};
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static struct clk_gate gxbb_32k_clk = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.bit_idx = 15,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "32k_clk_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const char *gxbb_32k_clk_parent_names[] = {
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"xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
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};
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static struct clk_mux gxbb_32k_clk_sel = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.mask = 0x3,
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.shift = 16,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk_sel",
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.ops = &clk_mux_ops,
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.parent_names = gxbb_32k_clk_parent_names,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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@ -1045,7 +1065,6 @@ static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
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static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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.hws = {
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[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
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[CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
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[CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
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[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
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[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
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@ -1158,6 +1177,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
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[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
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[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -1165,7 +1187,6 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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.hws = {
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[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
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[CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
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[CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
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[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
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[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
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@ -1278,6 +1299,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
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[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
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[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -1392,6 +1416,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
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&gxbb_mali_1,
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&gxbb_cts_amclk,
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&gxbb_cts_mclk_i958,
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&gxbb_32k_clk,
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};
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static struct clk_mux *const gxbb_clk_muxes[] = {
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@ -1403,6 +1428,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
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&gxbb_cts_amclk_sel,
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&gxbb_cts_mclk_i958_sel,
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&gxbb_cts_i958,
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&gxbb_32k_clk_sel,
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};
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static struct clk_divider *const gxbb_clk_dividers[] = {
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@ -1411,6 +1437,7 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
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&gxbb_mali_0_div,
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&gxbb_mali_1_div,
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&gxbb_cts_mclk_i958_div,
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&gxbb_32k_clk_div,
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};
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static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
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@ -1430,7 +1457,6 @@ struct clkc_data {
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unsigned int clk_dividers_count;
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struct meson_clk_audio_divider *const *clk_audio_dividers;
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unsigned int clk_audio_dividers_count;
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struct meson_clk_cpu *cpu_clk;
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struct clk_hw_onecell_data *hw_onecell_data;
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};
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@ -1447,7 +1473,6 @@ static const struct clkc_data gxbb_clkc_data = {
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.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
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.clk_audio_dividers = gxbb_audio_dividers,
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.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
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.cpu_clk = &gxbb_cpu_clk,
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.hw_onecell_data = &gxbb_hw_onecell_data,
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};
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@ -1464,7 +1489,6 @@ static const struct clkc_data gxl_clkc_data = {
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.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
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.clk_audio_dividers = gxbb_audio_dividers,
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.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
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.cpu_clk = &gxbb_cpu_clk,
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.hw_onecell_data = &gxl_hw_onecell_data,
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};
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@ -1479,8 +1503,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
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const struct clkc_data *clkc_data;
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void __iomem *clk_base;
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int ret, clkid, i;
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struct clk_hw *parent_hw;
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struct clk *parent_clk;
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struct device *dev = &pdev->dev;
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clkc_data = of_device_get_match_data(&pdev->dev);
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@ -1502,9 +1524,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
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for (i = 0; i < clkc_data->clk_mplls_count; i++)
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clkc_data->clk_mplls[i]->base = clk_base;
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/* Populate the base address for CPU clk */
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clkc_data->cpu_clk->base = clk_base;
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/* Populate base address for gates */
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for (i = 0; i < clkc_data->clk_gates_count; i++)
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clkc_data->clk_gates[i]->reg = clk_base +
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@ -1538,29 +1557,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
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goto iounmap;
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}
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/*
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* Register CPU clk notifier
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*
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* FIXME this is wrong for a lot of reasons. First, the muxes should be
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* struct clk_hw objects. Second, we shouldn't program the muxes in
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* notifier handlers. The tricky programming sequence will be handled
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* by the forthcoming coordinated clock rates mechanism once that
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* feature is released.
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*
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* Furthermore, looking up the parent this way is terrible. At some
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* point we will stop allocating a default struct clk when registering
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* a new clk_hw, and this hack will no longer work. Releasing the ccr
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* feature before that time solves the problem :-)
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*/
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parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw);
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parent_clk = parent_hw->clk;
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ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for cpu_clk\n",
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__func__);
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goto iounmap;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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clkc_data->hw_onecell_data);
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@ -171,7 +171,7 @@
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* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
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*/
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#define CLKID_SYS_PLL 0
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/* CLKID_CPUCLK */
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/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
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/* CLKID_HDMI_PLL */
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#define CLKID_FIXED_PLL 3
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/* CLKID_FCLK_DIV2 */
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@ -191,12 +191,12 @@
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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/* CLKID_SPICC */
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/* CLKID_I2C */
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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/* CLKID_RNG0 */
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#define CLKID_UART0 26
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/* CLKID_UART0 */
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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@ -209,7 +209,7 @@
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/* CLKID_ETH */
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#define CLKID_DEMUX 37
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/* CLKID_AIU_GLUE */
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#define CLKID_IEC958 39
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/* CLKID_IEC958 */
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/* CLKID_I2S_OUT */
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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@ -218,7 +218,7 @@
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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/* CLKID_AIU */
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#define CLKID_UART1 48
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/* CLKID_UART1 */
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#define CLKID_G2D 49
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/* CLKID_USB0 */
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/* CLKID_USB1 */
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@ -238,7 +238,7 @@
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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/* CLKID_UART2 */
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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@ -251,7 +251,7 @@
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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/* CLKID_AOCLK_GATE */
|
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#define CLKID_IEC958_GATE 81
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/* CLKID_IEC958_GATE */
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCI_INT1 84
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||||
|
|
@ -277,15 +277,18 @@
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|||
#define CLKID_MALI_1_DIV 104
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||||
/* CLKID_MALI_1 */
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||||
/* CLKID_MALI */
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
/* CLKID_CTS_AMCLK */
|
||||
#define CLKID_CTS_AMCLK_SEL 108
|
||||
#define CLKID_CTS_AMCLK_DIV 109
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
/* CLKID_CTS_MCLK_I958 */
|
||||
#define CLKID_CTS_MCLK_I958_SEL 111
|
||||
#define CLKID_CTS_MCLK_I958_DIV 112
|
||||
#define CLKID_CTS_I958 113
|
||||
/* CLKID_CTS_I958 */
|
||||
#define CLKID_32K_CLK 114
|
||||
#define CLKID_32K_CLK_SEL 115
|
||||
#define CLKID_32K_CLK_DIV 116
|
||||
|
||||
#define NR_CLKS 114
|
||||
#define NR_CLKS 117
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
|
|
|||
|
|
@ -399,7 +399,7 @@ struct clk_gate meson8b_clk81 = {
|
|||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "mpeg_clk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@
|
|||
#ifndef __GXBB_CLKC_H
|
||||
#define __GXBB_CLKC_H
|
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#define CLKID_CPUCLK 1
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#define CLKID_HDMI_PLL 2
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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|
|
@ -13,24 +12,30 @@
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SPI 34
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||||
#define CLKID_ETH 36
|
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#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_MIXER_IFACE 44
|
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#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
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#define CLKID_AO_I2C 93
|
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#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
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|
|
@ -42,5 +47,8 @@
|
|||
#define CLKID_MALI_1_SEL 103
|
||||
#define CLKID_MALI_1 105
|
||||
#define CLKID_MALI 106
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_I958 113
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue