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spi: stm32: add st,stm32mp25-spi compatible supporting STM32MP25 soc
Add support for the STM32MP25: - Burst should not be enabled with the new DMA used on STM32MP25. - STM32MP25 SPI8 has a limited feature set, it can only send words of 8 or 16 bits and with a maximum words number of 1024. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://msgid.link/r/20231218155721.359198-4-alain.volmat@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
f034a15105
commit
f6cd66231a
1 changed files with 120 additions and 12 deletions
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@ -154,6 +154,20 @@
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/* STM32H7_SPI_I2SCFGR bit fields */
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/* STM32H7_SPI_I2SCFGR bit fields */
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#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
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#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
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/* STM32MP25 SPI registers bit fields */
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#define STM32MP25_SPI_HWCFGR1 0x3F0
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/* STM32MP25_SPI_CR2 bit fields */
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#define STM32MP25_SPI_TSIZE_MAX_LIMITED GENMASK(9, 0)
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/* STM32MP25_SPI_HWCFGR1 */
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#define STM32MP25_SPI_HWCFGR1_FULLCFG GENMASK(27, 24)
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#define STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED 0x0
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#define STM32MP25_SPI_HWCFGR1_FULLCFG_FULL 0x1
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#define STM32MP25_SPI_HWCFGR1_DSCFG GENMASK(19, 16)
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#define STM32MP25_SPI_HWCFGR1_DSCFG_16_B 0x0
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#define STM32MP25_SPI_HWCFGR1_DSCFG_32_B 0x1
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/* STM32H7 SPI Master Baud Rate min/max divisor */
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/* STM32H7 SPI Master Baud Rate min/max divisor */
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#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
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#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
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#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
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#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
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@ -207,6 +221,7 @@ struct stm32_spi_reg {
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* @br: baud rate register and bitfields
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* @br: baud rate register and bitfields
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* @rx: SPI RX data register
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* @rx: SPI RX data register
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* @tx: SPI TX data register
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* @tx: SPI TX data register
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* @fullcfg: SPI full or limited feature set register
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*/
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*/
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struct stm32_spi_regspec {
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struct stm32_spi_regspec {
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const struct stm32_spi_reg en;
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const struct stm32_spi_reg en;
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@ -219,6 +234,7 @@ struct stm32_spi_regspec {
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const struct stm32_spi_reg br;
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const struct stm32_spi_reg br;
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const struct stm32_spi_reg rx;
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const struct stm32_spi_reg rx;
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const struct stm32_spi_reg tx;
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const struct stm32_spi_reg tx;
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const struct stm32_spi_reg fullcfg;
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};
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};
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struct stm32_spi;
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struct stm32_spi;
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@ -250,6 +266,7 @@ struct stm32_spi;
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* @has_fifo: boolean to know if fifo is used for driver
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* @has_fifo: boolean to know if fifo is used for driver
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* @has_device_mode: is this compatible capable to switch on device mode
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* @has_device_mode: is this compatible capable to switch on device mode
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* @flags: compatible specific SPI controller flags used at registration time
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* @flags: compatible specific SPI controller flags used at registration time
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* @prevent_dma_burst: boolean to indicate to prevent DMA burst
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*/
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*/
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struct stm32_spi_cfg {
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struct stm32_spi_cfg {
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const struct stm32_spi_regspec *regs;
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const struct stm32_spi_regspec *regs;
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@ -274,6 +291,7 @@ struct stm32_spi_cfg {
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bool has_fifo;
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bool has_fifo;
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bool has_device_mode;
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bool has_device_mode;
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u16 flags;
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u16 flags;
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bool prevent_dma_burst;
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};
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};
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/**
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/**
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@ -287,6 +305,8 @@ struct stm32_spi_cfg {
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* @lock: prevent I/O concurrent access
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* @lock: prevent I/O concurrent access
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* @irq: SPI controller interrupt line
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* @irq: SPI controller interrupt line
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* @fifo_size: size of the embedded fifo in bytes
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* @fifo_size: size of the embedded fifo in bytes
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* @t_size_max: maximum number of data of one transfer
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* @feature_set: SPI full or limited feature set
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* @cur_midi: host inter-data idleness in ns
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* @cur_midi: host inter-data idleness in ns
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* @cur_speed: speed configured in Hz
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* @cur_speed: speed configured in Hz
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* @cur_half_period: time of a half bit in us
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* @cur_half_period: time of a half bit in us
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@ -314,6 +334,10 @@ struct stm32_spi {
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spinlock_t lock; /* prevent I/O concurrent access */
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spinlock_t lock; /* prevent I/O concurrent access */
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int irq;
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int irq;
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unsigned int fifo_size;
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unsigned int fifo_size;
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unsigned int t_size_max;
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unsigned int feature_set;
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#define STM32_SPI_FEATURE_LIMITED STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED /* 0x0 */
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#define STM32_SPI_FEATURE_FULL STM32MP25_SPI_HWCFGR1_FULLCFG_FULL /* 0x1 */
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unsigned int cur_midi;
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unsigned int cur_midi;
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unsigned int cur_speed;
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unsigned int cur_speed;
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@ -371,6 +395,28 @@ static const struct stm32_spi_regspec stm32h7_spi_regspec = {
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.tx = { STM32H7_SPI_TXDR },
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.tx = { STM32H7_SPI_TXDR },
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};
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};
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static const struct stm32_spi_regspec stm32mp25_spi_regspec = {
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/* SPI data transfer is enabled but spi_ker_ck is idle.
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* CFG1 and CFG2 registers are write protected when SPE is enabled.
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*/
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.en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
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.dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
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.dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
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.cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
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.cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
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.lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
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.cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
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.br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
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STM32H7_SPI_CFG1_MBR_SHIFT },
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.rx = { STM32H7_SPI_RXDR },
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.tx = { STM32H7_SPI_TXDR },
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.fullcfg = { STM32MP25_SPI_HWCFGR1, STM32MP25_SPI_HWCFGR1_FULLCFG },
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};
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static inline void stm32_spi_set_bits(struct stm32_spi *spi,
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static inline void stm32_spi_set_bits(struct stm32_spi *spi,
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u32 offset, u32 bits)
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u32 offset, u32 bits)
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{
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{
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@ -457,6 +503,28 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
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return SPI_BPW_RANGE_MASK(4, max_bpw);
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return SPI_BPW_RANGE_MASK(4, max_bpw);
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}
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}
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/**
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* stm32mp25_spi_get_bpw_mask - Return bits per word mask
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* @spi: pointer to the spi controller data structure
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*/
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static int stm32mp25_spi_get_bpw_mask(struct stm32_spi *spi)
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{
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u32 dscfg, max_bpw;
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if (spi->feature_set == STM32_SPI_FEATURE_LIMITED) {
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dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
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return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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}
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dscfg = FIELD_GET(STM32MP25_SPI_HWCFGR1_DSCFG,
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readl_relaxed(spi->base + STM32MP25_SPI_HWCFGR1));
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max_bpw = 16;
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if (dscfg == STM32MP25_SPI_HWCFGR1_DSCFG_32_B)
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max_bpw = 32;
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dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
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return SPI_BPW_RANGE_MASK(4, max_bpw);
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}
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/**
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/**
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* stm32_spi_prepare_mbr - Determine baud rate divisor value
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* stm32_spi_prepare_mbr - Determine baud rate divisor value
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* @spi: pointer to the spi controller data structure
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* @spi: pointer to the spi controller data structure
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@ -1103,7 +1171,7 @@ static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
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int ret;
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int ret;
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ret = spi_split_transfers_maxwords(ctrl, msg,
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ret = spi_split_transfers_maxwords(ctrl, msg,
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STM32H7_SPI_TSIZE_MAX,
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spi->t_size_max,
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GFP_KERNEL | GFP_DMA);
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GFP_KERNEL | GFP_DMA);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -1168,7 +1236,7 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
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{
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{
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enum dma_slave_buswidth buswidth;
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enum dma_slave_buswidth buswidth;
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struct dma_slave_caps caps;
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struct dma_slave_caps caps;
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u32 maxburst;
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u32 maxburst = 1;
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int ret;
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int ret;
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if (spi->cur_bpw <= 8)
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if (spi->cur_bpw <= 8)
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@ -1178,15 +1246,9 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
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else
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else
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buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
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buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
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if (spi->cfg->has_fifo) {
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/* Valid for DMA Half or Full Fifo threshold */
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/* Valid for DMA Half or Full Fifo threshold */
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if (spi->cur_fthlv == 2)
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if (!spi->cfg->prevent_dma_burst && spi->cfg->has_fifo && spi->cur_fthlv != 2)
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maxburst = 1;
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else
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maxburst = spi->cur_fthlv;
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maxburst = spi->cur_fthlv;
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} else {
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maxburst = 1;
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}
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/* Get the DMA channel caps, and adjust maxburst if possible */
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/* Get the DMA channel caps, and adjust maxburst if possible */
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ret = dma_get_slave_caps(dma_chan, &caps);
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ret = dma_get_slave_caps(dma_chan, &caps);
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@ -1671,7 +1733,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
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*/
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*/
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static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
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static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
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{
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{
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if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
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if (nb_words <= spi->t_size_max) {
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writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
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writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
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spi->base + STM32H7_SPI_CR2);
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spi->base + STM32H7_SPI_CR2);
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} else {
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} else {
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@ -1954,7 +2016,37 @@ static const struct stm32_spi_cfg stm32h7_spi_cfg = {
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.has_device_mode = true,
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.has_device_mode = true,
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};
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};
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/*
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* STM32MP2 is compatible with the STM32H7 except:
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* - enforce the DMA maxburst value to 1
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* - spi8 have limited feature set (TSIZE_MAX = 1024, BPW of 8 OR 16)
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*/
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static const struct stm32_spi_cfg stm32mp25_spi_cfg = {
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.regs = &stm32mp25_spi_regspec,
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.get_fifo_size = stm32h7_spi_get_fifo_size,
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.get_bpw_mask = stm32mp25_spi_get_bpw_mask,
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.disable = stm32h7_spi_disable,
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.config = stm32h7_spi_config,
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.set_bpw = stm32h7_spi_set_bpw,
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.set_mode = stm32h7_spi_set_mode,
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.set_data_idleness = stm32h7_spi_data_idleness,
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.set_number_of_data = stm32h7_spi_number_of_data,
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.transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
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.dma_rx_cb = stm32_spi_dma_rx_cb,
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/*
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* dma_tx_cb is not necessary since in case of TX, dma is followed by
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* SPI access hence handling is performed within the SPI interrupt
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*/
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.transfer_one_irq = stm32h7_spi_transfer_one_irq,
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.irq_handler_thread = stm32h7_spi_irq_thread,
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.baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
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.baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
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.has_fifo = true,
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.prevent_dma_burst = true,
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};
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static const struct of_device_id stm32_spi_of_match[] = {
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static const struct of_device_id stm32_spi_of_match[] = {
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{ .compatible = "st,stm32mp25-spi", .data = (void *)&stm32mp25_spi_cfg },
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{ .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
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{ .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
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{ .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
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{ .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
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{ .compatible = "st,stm32f7-spi", .data = (void *)&stm32f7_spi_cfg },
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{ .compatible = "st,stm32f7-spi", .data = (void *)&stm32f7_spi_cfg },
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@ -2058,6 +2150,22 @@ static int stm32_spi_probe(struct platform_device *pdev)
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if (spi->cfg->has_fifo)
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if (spi->cfg->has_fifo)
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spi->fifo_size = spi->cfg->get_fifo_size(spi);
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spi->fifo_size = spi->cfg->get_fifo_size(spi);
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spi->feature_set = STM32_SPI_FEATURE_FULL;
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if (spi->cfg->regs->fullcfg.reg) {
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spi->feature_set =
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FIELD_GET(STM32MP25_SPI_HWCFGR1_FULLCFG,
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readl_relaxed(spi->base + spi->cfg->regs->fullcfg.reg));
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dev_dbg(spi->dev, "%s feature set\n",
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spi->feature_set == STM32_SPI_FEATURE_FULL ? "full" : "limited");
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}
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/* Only for STM32H7 and after */
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spi->t_size_max = spi->feature_set == STM32_SPI_FEATURE_FULL ?
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STM32H7_SPI_TSIZE_MAX :
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STM32MP25_SPI_TSIZE_MAX_LIMITED;
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dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max);
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ret = spi->cfg->config(spi);
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ret = spi->cfg->config(spi);
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if (ret) {
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if (ret) {
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dev_err(&pdev->dev, "controller configuration failed: %d\n",
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dev_err(&pdev->dev, "controller configuration failed: %d\n",
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