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tile: updates to pci root complex from community feedback
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
parent
f100625789
commit
f6d2ce00da
3 changed files with 47 additions and 64 deletions
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@ -128,15 +128,10 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH())
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/*
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* End of the PCI memory resource.
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* Start of the PCI memory resource, which starts at the end of the
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* maximum system physical RAM address.
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*/
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#define TILE_PCI_MEM_END \
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((1ULL << CHIP_PA_WIDTH()) + TILE_PCI_BAR_WINDOW_TOP)
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/*
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* Start of the PCI memory resource.
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*/
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#define TILE_PCI_MEM_START (TILE_PCI_MEM_END - TILE_PCI_BAR_WINDOW_SIZE)
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#define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH())
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/*
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* Structure of a PCI controller (host bridge) on Gx.
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@ -159,17 +154,19 @@ struct pci_controller {
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int index; /* PCI domain number */
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struct pci_bus *root_bus;
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/* PCI memory space resource for this controller. */
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struct resource mem_space;
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char mem_space_name[32];
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uint64_t mem_offset; /* cpu->bus memory mapping offset. */
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int last_busno;
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int first_busno;
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struct pci_ops *ops;
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/* Table that maps the INTx numbers to Linux irq numbers. */
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int irq_intx_table[4];
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struct resource mem_space;
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/* Address ranges that are routed to this controller/bridge. */
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struct resource mem_resources[3];
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};
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@ -179,14 +176,6 @@ extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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extern void
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pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res);
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extern void
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pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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/*
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* The PCI address space does not equal the physical memory address
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* space (we have an IOMMU). The IDE and SCSI device layers use this
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@ -96,21 +96,6 @@ static struct pci_ops tile_cfg_ops;
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/* Mask of CPUs that should receive PCIe interrupts. */
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static struct cpumask intr_cpus_map;
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/* PCI I/O space support is not implemented. */
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static struct resource pci_ioport_resource = {
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.name = "PCI IO",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci_iomem_resource = {
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.name = "PCI mem",
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.start = TILE_PCI_MEM_START,
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.end = TILE_PCI_MEM_END,
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.flags = IORESOURCE_MEM,
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};
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/*
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* We don't need to worry about the alignment of resources.
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*/
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@ -437,9 +422,26 @@ int __init tile_pci_init(void)
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struct pci_controller *controller = &pci_controllers[i];
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controller->index = i;
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controller->last_busno = 0xff;
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controller->ops = &tile_cfg_ops;
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/*
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* The PCI memory resource is located above the PA space.
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* For every host bridge, the BAR window or the MMIO aperture
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* is in range [3GB, 4GB - 1] of a 4GB space beyond the
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* PA space.
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*/
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controller->mem_offset = TILE_PCI_MEM_START +
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(i * TILE_PCI_BAR_WINDOW_TOP);
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controller->mem_space.start = controller->mem_offset +
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TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
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controller->mem_space.end = controller->mem_offset +
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TILE_PCI_BAR_WINDOW_TOP - 1;
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controller->mem_space.flags = IORESOURCE_MEM;
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snprintf(controller->mem_space_name,
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sizeof(controller->mem_space_name),
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"PCI mem domain %d", i);
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controller->mem_space.name = controller->mem_space_name;
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}
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return num_rc_controllers;
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@ -588,6 +590,7 @@ int __init pcibios_init(void)
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{
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resource_size_t offset;
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LIST_HEAD(resources);
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int next_busno;
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int i;
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tile_pci_init();
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@ -628,7 +631,7 @@ int __init pcibios_init(void)
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msleep(250);
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/* Scan all of the recorded PCI controllers. */
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for (i = 0; i < num_rc_controllers; i++) {
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for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
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struct pci_controller *controller = &pci_controllers[i];
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gxio_trio_context_t *trio_context = controller->trio;
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TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
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@ -843,13 +846,14 @@ int __init pcibios_init(void)
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* The memory range for the PCI root bus should not overlap
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* with the physical RAM
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*/
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pci_add_resource_offset(&resources, &iomem_resource,
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1ULL << CHIP_PA_WIDTH());
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pci_add_resource_offset(&resources, &controller->mem_space,
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controller->mem_offset);
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bus = pci_scan_root_bus(NULL, 0, controller->ops,
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controller->first_busno = next_busno;
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bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
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controller, &resources);
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controller->root_bus = bus;
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controller->last_busno = bus->subordinate;
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next_busno = bus->subordinate + 1;
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}
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@ -1011,20 +1015,9 @@ int __init pcibios_init(void)
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}
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subsys_initcall(pcibios_init);
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/*
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* PCI scan code calls the arch specific pcibios_fixup_bus() each time it scans
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* a new bridge. Called after each bus is probed, but before its children are
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* examined.
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*/
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/* Note: to be deleted after Linux 3.6 merge. */
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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if (!dev) {
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/* This is the root bus. */
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bus->resource[0] = &pci_ioport_resource;
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bus->resource[1] = &pci_iomem_resource;
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}
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}
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/*
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@ -1124,7 +1117,10 @@ void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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got_it:
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trio_fd = controller->trio->fd;
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offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + phys_addr;
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/* Convert the resource start to the bus address offset. */
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start = phys_addr - controller->mem_offset;
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offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
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/*
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* We need to keep the PCI bus address's in-page offset in the VA.
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@ -1172,11 +1168,11 @@ static int __devinit tile_cfg_read(struct pci_bus *bus,
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void *mmio_addr;
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/*
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* Map all accesses to the local device (bus == 0) into the
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* Map all accesses to the local device on root bus into the
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* MMIO space of the MAC. Accesses to the downstream devices
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* go to the PIO space.
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*/
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if (busnum == 0) {
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if (pci_is_root_bus(bus)) {
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if (device == 0) {
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/*
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* This is the internal downstream P2P bridge,
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@ -1205,11 +1201,11 @@ static int __devinit tile_cfg_read(struct pci_bus *bus,
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}
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/*
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* Accesses to the directly attached device (bus == 1) have to be
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* Accesses to the directly attached device have to be
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* sent as type-0 configs.
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*/
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if (busnum == 1) {
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if (busnum == (controller->first_busno + 1)) {
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/*
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* There is only one device off of our built-in P2P bridge.
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*/
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@ -1303,11 +1299,11 @@ static int __devinit tile_cfg_write(struct pci_bus *bus,
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u8 val_8 = (u8)val;
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/*
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* Map all accesses to the local device (bus == 0) into the
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* Map all accesses to the local device on root bus into the
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* MMIO space of the MAC. Accesses to the downstream devices
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* go to the PIO space.
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*/
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if (busnum == 0) {
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if (pci_is_root_bus(bus)) {
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if (device == 0) {
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/*
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* This is the internal downstream P2P bridge,
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@ -1336,11 +1332,11 @@ static int __devinit tile_cfg_write(struct pci_bus *bus,
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}
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/*
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* Accesses to the directly attached device (bus == 1) have to be
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* Accesses to the directly attached device have to be
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* sent as type-0 configs.
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*/
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if (busnum == 1) {
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if (busnum == (controller->first_busno + 1)) {
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/*
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* There is only one device off of our built-in P2P bridge.
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*/
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@ -1536,8 +1536,7 @@ static struct resource code_resource = {
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/*
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* On Pro, we reserve all resources above 4GB so that PCI won't try to put
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* mappings above 4GB; the standard allows that for some devices but
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* the probing code trunates values to 32 bits.
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* mappings above 4GB.
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*/
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#if defined(CONFIG_PCI) && !defined(__tilegx__)
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static struct resource* __init
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@ -1584,7 +1583,6 @@ static int __init request_standard_resources(void)
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int i;
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enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
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iomem_resource.end = -1LL;
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#if defined(CONFIG_PCI) && !defined(__tilegx__)
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insert_non_bus_resource();
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#endif
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