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amd64_edac: add F10h-and-later methods-p3
Borislav: - compute dct_sel_base_off in f10_match_to_this_node() correctly since it cannot be assumed that the Reserved bits are zero and they have to be masked out instead. - cleanup, remove StinkyIdentifiers, simplify logic - fix function return value patterns - cleanup debug calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
6163b5d4fb
commit
f71d0a0500
1 changed files with 265 additions and 4 deletions
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@ -1398,6 +1398,10 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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debugf0("Reading F10_DCTL_SEL_HIGH failed\n");
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}
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/*
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* determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory
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* Interleaving Modes.
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*/
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static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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int hi_range_sel, u32 intlv_en)
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{
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@ -1408,6 +1412,9 @@ static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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else if (hi_range_sel)
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cs = dct_sel_high;
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else if (dct_interleave_enabled(pvt)) {
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/*
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* see F2x110[DctSelIntLvAddr] - channel interleave mode
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*/
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if (dct_sel_interleave_addr(pvt) == 0)
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cs = sys_addr >> 6 & 1;
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else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) {
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@ -1445,22 +1452,23 @@ static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en)
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return 0;
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}
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static inline u64 f10_determine_base_addr_offset(u64 sys_addr, int hi_range_sel,
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/* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
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static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
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u32 dct_sel_base_addr,
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u64 dct_sel_base_off,
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u32 hole_en, u32 hole_off,
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u32 hole_valid, u32 hole_off,
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u64 dram_base)
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{
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u64 chan_off;
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if (hi_range_sel) {
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if (!(dct_sel_base_addr & 0xFFFFF800) &&
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(hole_en & 1) && (sys_addr >= 0x100000000ULL))
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hole_valid && (sys_addr >= 0x100000000ULL))
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chan_off = hole_off << 16;
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else
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chan_off = dct_sel_base_off;
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} else {
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if ((hole_en & 1) && (sys_addr >= 0x100000000ULL))
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if (hole_valid && (sys_addr >= 0x100000000ULL))
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chan_off = hole_off << 16;
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else
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chan_off = dram_base & 0xFFFFF8000000ULL;
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@ -1562,4 +1570,257 @@ static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
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return cs_found;
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}
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/* For a given @dram_range, check if @sys_addr falls within it. */
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static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range,
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u64 sys_addr, int *nid, int *chan_sel)
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{
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int node_id, cs_found = -EINVAL, high_range = 0;
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u32 intlv_en, intlv_sel, intlv_shift, hole_off;
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u32 hole_valid, tmp, dct_sel_base, channel;
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u64 dram_base, chan_addr, dct_sel_base_off;
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dram_base = pvt->dram_base[dram_range];
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intlv_en = pvt->dram_IntlvEn[dram_range];
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node_id = pvt->dram_DstNode[dram_range];
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intlv_sel = pvt->dram_IntlvSel[dram_range];
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debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
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dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]);
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/*
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* This assumes that one node's DHAR is the same as all the other
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* nodes' DHAR.
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*/
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hole_off = (pvt->dhar & 0x0000FF80);
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hole_valid = (pvt->dhar & 0x1);
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dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16;
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debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n",
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hole_off, hole_valid, intlv_sel);
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if (intlv_en ||
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(intlv_sel != ((sys_addr >> 12) & intlv_en)))
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return -EINVAL;
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dct_sel_base = dct_sel_baseaddr(pvt);
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/*
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* check whether addresses >= DctSelBaseAddr[47:27] are to be used to
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* select between DCT0 and DCT1.
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*/
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if (dct_high_range_enabled(pvt) &&
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!dct_ganging_enabled(pvt) &&
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((sys_addr >> 27) >= (dct_sel_base >> 11)))
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high_range = 1;
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channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en);
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chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base,
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dct_sel_base_off, hole_valid,
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hole_off, dram_base);
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intlv_shift = f10_map_intlv_en_to_shift(intlv_en);
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/* remove Node ID (in case of memory interleaving) */
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tmp = chan_addr & 0xFC0;
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chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp;
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/* remove channel interleave and hash */
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if (dct_interleave_enabled(pvt) &&
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!dct_high_range_enabled(pvt) &&
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!dct_ganging_enabled(pvt)) {
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if (dct_sel_interleave_addr(pvt) != 1)
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chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL;
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else {
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tmp = chan_addr & 0xFC0;
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chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1)
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| tmp;
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}
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}
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debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n",
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chan_addr, (u32)(chan_addr >> 8));
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cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel);
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if (cs_found >= 0) {
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*nid = node_id;
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*chan_sel = channel;
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}
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return cs_found;
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}
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static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
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int *node, int *chan_sel)
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{
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int dram_range, cs_found = -EINVAL;
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u64 dram_base, dram_limit;
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for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) {
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if (!pvt->dram_rw_en[dram_range])
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continue;
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dram_base = pvt->dram_base[dram_range];
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dram_limit = pvt->dram_limit[dram_range];
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if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) {
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cs_found = f10_match_to_this_node(pvt, dram_range,
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sys_addr, node,
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chan_sel);
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if (cs_found >= 0)
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break;
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}
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}
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return cs_found;
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}
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/*
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* This the F10h reference code from AMD to map a @sys_addr to NodeID,
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* CSROW, Channel.
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*
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* The @sys_addr is usually an error address received from the hardware.
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*/
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static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info,
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u64 sys_addr)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 page, offset;
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unsigned short syndrome;
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int nid, csrow, chan = 0;
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csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
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if (csrow >= 0) {
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error_address_to_page_and_offset(sys_addr, &page, &offset);
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syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8;
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syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh);
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/*
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* Is CHIPKILL on? If so, then we can attempt to use the
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* syndrome to isolate which channel the error was on.
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*/
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if (pvt->nbcfg & K8_NBCFG_CHIPKILL)
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chan = get_channel_from_ecc_syndrome(syndrome);
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if (chan >= 0) {
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edac_mc_handle_ce(mci, page, offset, syndrome,
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csrow, chan, EDAC_MOD_STR);
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} else {
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/*
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* Channel unknown, report all channels on this
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* CSROW as failed.
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*/
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for (chan = 0; chan < mci->csrows[csrow].nr_channels;
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chan++) {
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edac_mc_handle_ce(mci, page, offset,
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syndrome,
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csrow, chan,
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EDAC_MOD_STR);
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}
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}
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} else {
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
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}
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}
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/*
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* Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift
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* table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0
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* indicates an empty DIMM slot, as reported by Hardware on empty slots.
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*
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* Normalize to 128MB by subracting 27 bit shift.
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*/
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static int map_dbam_to_csrow_size(int index)
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{
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int mega_bytes = 0;
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if (index > 0 && index <= DBAM_MAX_VALUE)
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mega_bytes = ((128 << (revf_quad_ddr2_shift[index]-27)));
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return mega_bytes;
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}
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/*
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* debug routine to display the memory sizes of a DIMM (ganged or not) and it
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* CSROWs as well
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*/
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static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
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int ganged)
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{
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int dimm, size0, size1;
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u32 dbam;
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u32 *dcsb;
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debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl,
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ctrl ? pvt->dbam1 : pvt->dbam0,
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ganged ? "GANGED - dbam1 not used" : "NON-GANGED");
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dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
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dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0;
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/* Dump memory sizes for DIMM and its CSROWs */
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for (dimm = 0; dimm < 4; dimm++) {
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size0 = 0;
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if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE)
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size0 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam));
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size1 = 0;
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if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE)
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size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam));
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debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB "
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"CSROW-%d=%5dMB\n",
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ctrl,
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dimm,
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size0 + size1,
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dimm * 2,
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size0,
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dimm * 2 + 1,
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size1);
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}
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}
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/*
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* Very early hardware probe on pci_probe thread to determine if this module
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* supports the hardware.
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*
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* Return:
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* 0 for OK
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* 1 for error
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*/
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static int f10_probe_valid_hardware(struct amd64_pvt *pvt)
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{
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int ret = 0;
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/*
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* If we are on a DDR3 machine, we don't know yet if
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* we support that properly at this time
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*/
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if ((pvt->dchr0 & F10_DCHR_Ddr3Mode) ||
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(pvt->dchr1 & F10_DCHR_Ddr3Mode)) {
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amd64_printk(KERN_WARNING,
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"%s() This machine is running with DDR3 memory. "
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"This is not currently supported. "
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"DCHR0=0x%x DCHR1=0x%x\n",
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__func__, pvt->dchr0, pvt->dchr1);
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amd64_printk(KERN_WARNING,
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" Contact '%s' module MAINTAINER to help add"
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" support.\n",
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EDAC_MOD_STR);
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ret = 1;
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}
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return ret;
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}
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