macb: initial support for Cadence GEM
The Cadence GEM is based on the MACB Ethernet controller but has a few
small changes with regards to register and bitfield placement. This
patch detects the presence of a GEM by reading the module ID register
and setting a flag appropriately.
This handles the new HW address, USRIO and hash register base register
locations in GEM.
v3: - convert to macb_is_gem() inline rather than storing a boolean
flag
- handle rx_overrun stats for gem
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Jamie Iles
Jamie Iles
parent
c220f8cd01
commit
f75ba50bdc
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@ -10,7 +10,7 @@ obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
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obj-$(CONFIG_NET_VENDOR_AMD) += amd/
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obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
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obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
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obj-$(CONFIG_NET_ATMEL) += cadence/
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obj-$(CONFIG_NET_CADENCE) += cadence/
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obj-$(CONFIG_NET_BFIN) += adi/
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obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
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obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
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@ -5,8 +5,8 @@
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config HAVE_NET_MACB
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bool
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config NET_ATMEL
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bool "Atmel devices"
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config NET_CADENCE
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bool "Cadence devices"
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depends on HAVE_NET_MACB || (ARM && ARCH_AT91RM9200)
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---help---
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If you have a network (Ethernet) card belonging to this class, say Y.
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@ -20,7 +20,7 @@ config NET_ATMEL
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the remaining Atmel network card questions. If you say Y, you will be
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asked for your specific card in the following questions.
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if NET_ATMEL
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if NET_CADENCE
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config ARM_AT91_ETHER
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tristate "AT91RM9200 Ethernet support"
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@ -32,14 +32,16 @@ config ARM_AT91_ETHER
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ethernet support, then you should always answer Y to this.
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config MACB
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tristate "Atmel MACB support"
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tristate "Cadence MACB/GEM support"
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depends on HAVE_NET_MACB
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select PHYLIB
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---help---
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The Atmel MACB ethernet interface is found on many AT32 and AT91
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parts. Say Y to include support for the MACB chip.
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The Cadence MACB ethernet interface is found on many Atmel AT32 and
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AT91 parts. This driver also supports the Cadence GEM (Gigabit
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Ethernet MAC found in some ARM SoC devices). Note: the Gigabit mode
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is not yet supported. Say Y to include support for the MACB/GEM chip.
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To compile this driver as a module, choose M here: the module
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will be called macb.
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endif # NET_ATMEL
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endif # NET_CADENCE
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@ -1,5 +1,5 @@
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/*
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* Atmel MACB Ethernet Controller driver
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* Cadence MACB/GEM Ethernet Controller driver
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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@ -59,9 +59,9 @@ static void __macb_set_hwaddr(struct macb *bp)
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u16 top;
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bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
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macb_writel(bp, SA1B, bottom);
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macb_or_gem_writel(bp, SA1B, bottom);
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top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
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macb_writel(bp, SA1T, top);
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macb_or_gem_writel(bp, SA1T, top);
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}
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static void __init macb_get_hwaddr(struct macb *bp)
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@ -70,8 +70,8 @@ static void __init macb_get_hwaddr(struct macb *bp)
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u16 top;
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u8 addr[6];
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bottom = macb_readl(bp, SA1B);
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top = macb_readl(bp, SA1T);
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bottom = macb_or_gem_readl(bp, SA1B);
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top = macb_or_gem_readl(bp, SA1T);
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addr[0] = bottom & 0xff;
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addr[1] = (bottom >> 8) & 0xff;
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@ -580,7 +580,10 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
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if (status & MACB_BIT(ISR_ROVR)) {
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/* We missed at least one packet */
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bp->hw_stats.rx_overruns++;
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if (macb_is_gem(bp))
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bp->hw_stats.gem.rx_overruns++;
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else
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bp->hw_stats.macb.rx_overruns++;
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}
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if (status & MACB_BIT(HRESP)) {
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@ -902,8 +905,8 @@ static void macb_sethashtable(struct net_device *dev)
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mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
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}
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macb_writel(bp, HRB, mc_filter[0]);
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macb_writel(bp, HRT, mc_filter[1]);
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macb_or_gem_writel(bp, HRB, mc_filter[0]);
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macb_or_gem_writel(bp, HRT, mc_filter[1]);
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}
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/*
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@ -925,8 +928,8 @@ static void macb_set_rx_mode(struct net_device *dev)
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if (dev->flags & IFF_ALLMULTI) {
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/* Enable all multicast mode */
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macb_writel(bp, HRB, -1);
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macb_writel(bp, HRT, -1);
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macb_or_gem_writel(bp, HRB, -1);
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macb_or_gem_writel(bp, HRT, -1);
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cfg |= MACB_BIT(NCFGR_MTI);
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} else if (!netdev_mc_empty(dev)) {
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/* Enable specific multicasts */
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@ -934,8 +937,8 @@ static void macb_set_rx_mode(struct net_device *dev)
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cfg |= MACB_BIT(NCFGR_MTI);
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} else if (dev->flags & (~IFF_ALLMULTI)) {
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/* Disable all multicast mode */
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macb_writel(bp, HRB, 0);
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macb_writel(bp, HRT, 0);
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macb_or_gem_writel(bp, HRB, 0);
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macb_or_gem_writel(bp, HRT, 0);
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cfg &= ~MACB_BIT(NCFGR_MTI);
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}
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@ -1196,15 +1199,16 @@ static int __init macb_probe(struct platform_device *pdev)
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if (pdata && pdata->is_rmii)
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#if defined(CONFIG_ARCH_AT91)
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macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
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macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
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MACB_BIT(CLKEN)));
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#else
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macb_writel(bp, USRIO, 0);
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macb_or_gem_writel(bp, USRIO, 0);
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#endif
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else
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#if defined(CONFIG_ARCH_AT91)
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macb_writel(bp, USRIO, MACB_BIT(CLKEN));
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macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
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#else
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macb_writel(bp, USRIO, MACB_BIT(MII));
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macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
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#endif
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bp->tx_pending = DEF_TX_RING_PENDING;
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@ -1221,8 +1225,9 @@ static int __init macb_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, dev);
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netdev_info(dev, "Atmel MACB at 0x%08lx irq %d (%pM)\n",
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dev->base_addr, dev->irq, dev->dev_addr);
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netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
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macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
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dev->irq, dev->dev_addr);
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phydev = bp->phy_dev;
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netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
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@ -1332,6 +1337,6 @@ module_init(macb_init);
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module_exit(macb_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
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MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
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MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
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MODULE_ALIAS("platform:macb");
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@ -59,6 +59,15 @@
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#define MACB_TPQ 0x00bc
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#define MACB_USRIO 0x00c0
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#define MACB_WOL 0x00c4
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#define MACB_MID 0x00fc
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/* GEM register offsets. */
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#define GEM_NCFGR 0x0004
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#define GEM_USRIO 0x000c
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#define GEM_HRB 0x0080
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#define GEM_HRT 0x0084
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#define GEM_SA1B 0x0088
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#define GEM_SA1T 0x008C
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/* Bitfields in NCR */
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#define MACB_LB_OFFSET 0
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@ -228,6 +237,12 @@
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#define MACB_WOL_MTI_OFFSET 19
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#define MACB_WOL_MTI_SIZE 1
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/* Bitfields in MID */
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#define MACB_IDNUM_OFFSET 16
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#define MACB_IDNUM_SIZE 16
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#define MACB_REV_OFFSET 0
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#define MACB_REV_SIZE 16
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/* Constants for CLK */
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#define MACB_CLK_DIV8 0
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#define MACB_CLK_DIV16 1
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@ -254,11 +269,52 @@
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<< MACB_##name##_OFFSET)) \
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| MACB_BF(name,value))
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#define GEM_BIT(name) \
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(1 << GEM_##name##_OFFSET)
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#define GEM_BF(name, value) \
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(((value) & ((1 << GEM_##name##_SIZE) - 1)) \
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<< GEM_##name##_OFFSET)
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#define GEM_BFEXT(name, value)\
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(((value) >> GEM_##name##_OFFSET) \
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& ((1 << GEM_##name##_SIZE) - 1))
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#define GEM_BFINS(name, value, old) \
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(((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
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<< GEM_##name##_OFFSET)) \
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| GEM_BF(name, value))
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/* Register access macros */
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#define macb_readl(port,reg) \
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__raw_readl((port)->regs + MACB_##reg)
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#define macb_writel(port,reg,value) \
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__raw_writel((value), (port)->regs + MACB_##reg)
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#define gem_readl(port, reg) \
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__raw_readl((port)->regs + GEM_##reg)
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#define gem_writel(port, reg, value) \
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__raw_writel((value), (port)->regs + GEM_##reg)
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/*
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* Conditional GEM/MACB macros. These perform the operation to the correct
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* register dependent on whether the device is a GEM or a MACB. For registers
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* and bitfields that are common across both devices, use macb_{read,write}l
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* to avoid the cost of the conditional.
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*/
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#define macb_or_gem_writel(__bp, __reg, __value) \
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({ \
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if (macb_is_gem((__bp))) \
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gem_writel((__bp), __reg, __value); \
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else \
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macb_writel((__bp), __reg, __value); \
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})
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#define macb_or_gem_readl(__bp, __reg) \
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({ \
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u32 __v; \
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if (macb_is_gem((__bp))) \
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__v = gem_readl((__bp), __reg); \
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else \
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__v = macb_readl((__bp), __reg); \
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__v; \
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})
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struct dma_desc {
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u32 addr;
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@ -391,4 +447,9 @@ struct macb {
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unsigned int duplex;
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};
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static inline bool macb_is_gem(struct macb *bp)
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{
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return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;
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}
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#endif /* _MACB_H */
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