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373
Documentation/networking/e1000.txt
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@ -1,82 +1,35 @@
Linux* Base Driver for the Intel(R) PRO/1000 Family of Adapters
===============================================================
September 26, 2006
Intel Gigabit Linux driver.
Copyright(c) 1999 - 2010 Intel Corporation.
Contents
========
- In This Release
- Identifying Your Adapter
- Building and Installation
- Command Line Parameters
- Speed and Duplex Configuration
- Additional Configurations
- Known Issues
- Support
In This Release
===============
This file describes the Linux* Base Driver for the Intel(R) PRO/1000 Family
of Adapters. This driver includes support for Itanium(R)2-based systems.
For questions related to hardware requirements, refer to the documentation
supplied with your Intel PRO/1000 adapter. All hardware requirements listed
apply to use with Linux.
The following features are now available in supported kernels:
- Native VLANs
- Channel Bonding (teaming)
- SNMP
Channel Bonding documentation can be found in the Linux kernel source:
/Documentation/networking/bonding.txt
The driver information previously displayed in the /proc filesystem is not
supported in this release. Alternatively, you can use ethtool (version 1.6
or later), lspci, and ifconfig to obtain the same information.
Instructions on updating ethtool can be found in the section "Additional
Configurations" later in this document.
NOTE: The Intel(R) 82562v 10/100 Network Connection only provides 10/100
support.
Identifying Your Adapter
========================
For more information on how to identify your adapter, go to the Adapter &
Driver ID Guide at:
http://support.intel.com/support/network/adapter/pro100/21397.htm
http://support.intel.com/support/go/network/adapter/idguide.htm
For the latest Intel network drivers for Linux, refer to the following
website. In the search field, enter your adapter name or type, or use the
networking link on the left to search for your adapter:
http://downloadfinder.intel.com/scripts-df/support_intel.asp
http://support.intel.com/support/go/network/adapter/home.htm
Command Line Parameters
=======================
If the driver is built as a module, the following optional parameters
are used by entering them on the command line with the modprobe command
using this syntax:
modprobe e1000 [<option>=<VAL1>,<VAL2>,...]
For example, with two PRO/1000 PCI adapters, entering:
modprobe e1000 TxDescriptors=80,128
loads the e1000 driver with 80 TX descriptors for the first adapter and
128 TX descriptors for the second adapter.
The default value for each parameter is generally the recommended setting,
unless otherwise noted.
@ -89,10 +42,6 @@ NOTES: For more information about the AutoNeg, Duplex, and Speed
parameters, see the application note at:
http://www.intel.com/design/network/applnots/ap450.htm
A descriptor describes a data buffer and attributes related to
the data buffer. This information is accessed by the hardware.
AutoNeg
-------
(Supported only on adapters with copper connections)
@ -106,7 +55,6 @@ Duplex parameters must not be specified.
NOTE: Refer to the Speed and Duplex section of this readme for more
information on the AutoNeg parameter.
Duplex
------
(Supported only on adapters with copper connections)
@ -119,7 +67,6 @@ set to auto-negotiate, the board auto-detects the correct duplex. If the
link partner is forced (either full or half), Duplex defaults to half-
duplex.
FlowControl
-----------
Valid Range: 0-3 (0=none, 1=Rx only, 2=Tx only, 3=Rx&Tx)
@ -128,16 +75,16 @@ Default Value: Reads flow control settings from the EEPROM
This parameter controls the automatic generation(Tx) and response(Rx)
to Ethernet PAUSE frames.
InterruptThrottleRate
---------------------
(not supported on Intel(R) 82542, 82543 or 82544-based adapters)
Valid Range: 0,1,3,100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
Valid Range: 0,1,3,4,100-100000 (0=off, 1=dynamic, 3=dynamic conservative,
4=simplified balancing)
Default Value: 3
The driver can limit the amount of interrupts per second that the adapter
will generate for incoming packets. It does this by writing a value to the
adapter that is based on the maximum amount of interrupts that the adapter
will generate for incoming packets. It does this by writing a value to the
adapter that is based on the maximum amount of interrupts that the adapter
will generate per second.
Setting InterruptThrottleRate to a value greater or equal to 100
@ -146,37 +93,43 @@ per second, even if more packets have come in. This reduces interrupt
load on the system and can lower CPU utilization under heavy load,
but will increase latency as packets are not processed as quickly.
The default behaviour of the driver previously assumed a static
InterruptThrottleRate value of 8000, providing a good fallback value for
all traffic types,but lacking in small packet performance and latency.
The hardware can handle many more small packets per second however, and
The default behaviour of the driver previously assumed a static
InterruptThrottleRate value of 8000, providing a good fallback value for
all traffic types,but lacking in small packet performance and latency.
The hardware can handle many more small packets per second however, and
for this reason an adaptive interrupt moderation algorithm was implemented.
Since 7.3.x, the driver has two adaptive modes (setting 1 or 3) in which
it dynamically adjusts the InterruptThrottleRate value based on the traffic
it dynamically adjusts the InterruptThrottleRate value based on the traffic
that it receives. After determining the type of incoming traffic in the last
timeframe, it will adjust the InterruptThrottleRate to an appropriate value
timeframe, it will adjust the InterruptThrottleRate to an appropriate value
for that traffic.
The algorithm classifies the incoming traffic every interval into
classes. Once the class is determined, the InterruptThrottleRate value is
adjusted to suit that traffic type the best. There are three classes defined:
classes. Once the class is determined, the InterruptThrottleRate value is
adjusted to suit that traffic type the best. There are three classes defined:
"Bulk traffic", for large amounts of packets of normal size; "Low latency",
for small amounts of traffic and/or a significant percentage of small
packets; and "Lowest latency", for almost completely small packets or
packets; and "Lowest latency", for almost completely small packets or
minimal traffic.
In dynamic conservative mode, the InterruptThrottleRate value is set to 4000
for traffic that falls in class "Bulk traffic". If traffic falls in the "Low
latency" or "Lowest latency" class, the InterruptThrottleRate is increased
In dynamic conservative mode, the InterruptThrottleRate value is set to 4000
for traffic that falls in class "Bulk traffic". If traffic falls in the "Low
latency" or "Lowest latency" class, the InterruptThrottleRate is increased
stepwise to 20000. This default mode is suitable for most applications.
For situations where low latency is vital such as cluster or
grid computing, the algorithm can reduce latency even more when
InterruptThrottleRate is set to mode 1. In this mode, which operates
the same as mode 3, the InterruptThrottleRate will be increased stepwise to
the same as mode 3, the InterruptThrottleRate will be increased stepwise to
70000 for traffic in class "Lowest latency".
In simplified mode the interrupt rate is based on the ratio of Tx and
Rx traffic. If the bytes per second rate is approximately equal, the
interrupt rate will drop as low as 2000 interrupts per second. If the
traffic is mostly transmit or mostly receive, the interrupt rate could
be as high as 8000.
Setting InterruptThrottleRate to 0 turns off any interrupt moderation
and may improve small packet latency, but is generally not suitable
for bulk throughput traffic.
@ -212,8 +165,6 @@ NOTE: When e1000 is loaded with default settings and multiple adapters
be platform-specific. If CPU utilization is not a concern, use
RX_POLLING (NAPI) and default driver settings.
RxDescriptors
-------------
Valid Range: 80-256 for 82542 and 82543-based adapters
@ -225,15 +176,14 @@ by the driver. Increasing this value allows the driver to buffer more
incoming packets, at the expense of increased system memory utilization.
Each descriptor is 16 bytes. A receive buffer is also allocated for each
descriptor and can be either 2048, 4096, 8192, or 16384 bytes, depending
descriptor and can be either 2048, 4096, 8192, or 16384 bytes, depending
on the MTU setting. The maximum MTU size is 16110.
NOTE: MTU designates the frame size. It only needs to be set for Jumbo
Frames. Depending on the available system resources, the request
for a higher number of receive descriptors may be denied. In this
NOTE: MTU designates the frame size. It only needs to be set for Jumbo
Frames. Depending on the available system resources, the request
for a higher number of receive descriptors may be denied. In this
case, use a lower number.
RxIntDelay
----------
Valid Range: 0-65535 (0=off)
@ -254,7 +204,6 @@ CAUTION: When setting RxIntDelay to a value other than 0, adapters may
restoring the network connection. To eliminate the potential
for the hang ensure that RxIntDelay is set to 0.
RxAbsIntDelay
-------------
(This parameter is supported only on 82540, 82545 and later adapters.)
@ -268,7 +217,6 @@ packet is received within the set amount of time. Proper tuning,
along with RxIntDelay, may improve traffic throughput in specific network
conditions.
Speed
-----
(This parameter is supported only on adapters with copper connections.)
@ -280,7 +228,6 @@ Speed forces the line speed to the specified value in megabits per second
partner is set to auto-negotiate, the board will auto-detect the correct
speed. Duplex should also be set when Speed is set to either 10 or 100.
TxDescriptors
-------------
Valid Range: 80-256 for 82542 and 82543-based adapters
@ -295,6 +242,36 @@ NOTE: Depending on the available system resources, the request for a
higher number of transmit descriptors may be denied. In this case,
use a lower number.
TxDescriptorStep
----------------
Valid Range: 1 (use every Tx Descriptor)
4 (use every 4th Tx Descriptor)
Default Value: 1 (use every Tx Descriptor)
On certain non-Intel architectures, it has been observed that intense TX
traffic bursts of short packets may result in an improper descriptor
writeback. If this occurs, the driver will report a "TX Timeout" and reset
the adapter, after which the transmit flow will restart, though data may
have stalled for as much as 10 seconds before it resumes.
The improper writeback does not occur on the first descriptor in a system
memory cache-line, which is typically 32 bytes, or 4 descriptors long.
Setting TxDescriptorStep to a value of 4 will ensure that all TX descriptors
are aligned to the start of a system memory cache line, and so this problem
will not occur.
NOTES: Setting TxDescriptorStep to 4 effectively reduces the number of
TxDescriptors available for transmits to 1/4 of the normal allocation.
This has a possible negative performance impact, which may be
compensated for by allocating more descriptors using the TxDescriptors
module parameter.
There are other conditions which may result in "TX Timeout", which will
not be resolved by the use of the TxDescriptorStep parameter. As the
issue addressed by this parameter has never been observed on Intel
Architecture platforms, it should not be used on Intel platforms.
TxIntDelay
----------
@ -307,7 +284,6 @@ efficiency if properly tuned for specific network traffic. If the
system is reporting dropped transmits, this value may be set too high
causing the driver to run out of available transmit descriptors.
TxAbsIntDelay
-------------
(This parameter is supported only on 82540, 82545 and later adapters.)
@ -330,6 +306,35 @@ Default Value: 1
A value of '1' indicates that the driver should enable IP checksum
offload for received packets (both UDP and TCP) to the adapter hardware.
Copybreak
---------
Valid Range: 0-xxxxxxx (0=off)
Default Value: 256
Usage: insmod e1000.ko copybreak=128
Driver copies all packets below or equaling this size to a fresh Rx
buffer before handing it up the stack.
This parameter is different than other parameters, in that it is a
single (not 1,1,1 etc.) parameter applied to all driver instances and
it is also available during runtime at
/sys/module/e1000/parameters/copybreak
SmartPowerDownEnable
--------------------
Valid Range: 0-1
Default Value: 0 (disabled)
Allows PHY to turn off in lower power states. The user can turn off
this parameter in supported chipsets.
KumeranLockLoss
---------------
Valid Range: 0-1
Default Value: 1 (enabled)
This workaround skips resetting the PHY at shutdown for the initial
silicon releases of ICH8 systems.
Speed and Duplex Configuration
==============================
@ -385,40 +390,9 @@ If the link partner is forced to a specific speed and duplex, then this
parameter should not be used. Instead, use the Speed and Duplex parameters
previously mentioned to force the adapter to the same speed and duplex.
Additional Configurations
=========================
Configuring the Driver on Different Distributions
-------------------------------------------------
Configuring a network driver to load properly when the system is started
is distribution dependent. Typically, the configuration process involves
adding an alias line to /etc/modules.conf or /etc/modprobe.conf as well
as editing other system startup scripts and/or configuration files. Many
popular Linux distributions ship with tools to make these changes for you.
To learn the proper way to configure a network device for your system,
refer to your distribution documentation. If during this process you are
asked for the driver or module name, the name for the Linux Base Driver
for the Intel(R) PRO/1000 Family of Adapters is e1000.
As an example, if you install the e1000 driver for two PRO/1000 adapters
(eth0 and eth1) and set the speed and duplex to 10full and 100half, add
the following to modules.conf or or modprobe.conf:
alias eth0 e1000
alias eth1 e1000
options e1000 Speed=10,100 Duplex=2,1
Viewing Link Messages
---------------------
Link messages will not be displayed to the console if the distribution is
restricting system messages. In order to see network driver link messages
on your console, set dmesg to eight by entering the following:
dmesg -n 8
NOTE: This setting is not saved across reboots.
Jumbo Frames
------------
Jumbo Frames support is enabled by changing the MTU to a value larger than
@ -437,9 +411,11 @@ Additional Configurations
setting in a different location.
Notes:
- To enable Jumbo Frames, increase the MTU size on the interface beyond
1500.
Degradation in throughput performance may be observed in some Jumbo frames
environments. If this is observed, increasing the application's socket buffer
size and/or increasing the /proc/sys/net/ipv4/tcp_*mem entry values may help.
See the specific application manual and /usr/src/linux*/Documentation/
networking/ip-sysctl.txt for more details.
- The maximum MTU setting for Jumbo Frames is 16110. This value coincides
with the maximum Jumbo Frames size of 16128.
@ -447,40 +423,11 @@ Additional Configurations
- Using Jumbo Frames at 10 or 100 Mbps may result in poor performance or
loss of link.
- Some Intel gigabit adapters that support Jumbo Frames have a frame size
limit of 9238 bytes, with a corresponding MTU size limit of 9216 bytes.
The adapters with this limitation are based on the Intel(R) 82571EB,
82572EI, 82573L and 80003ES2LAN controller. These correspond to the
following product names:
Intel(R) PRO/1000 PT Server Adapter
Intel(R) PRO/1000 PT Desktop Adapter
Intel(R) PRO/1000 PT Network Connection
Intel(R) PRO/1000 PT Dual Port Server Adapter
Intel(R) PRO/1000 PT Dual Port Network Connection
Intel(R) PRO/1000 PF Server Adapter
Intel(R) PRO/1000 PF Network Connection
Intel(R) PRO/1000 PF Dual Port Server Adapter
Intel(R) PRO/1000 PB Server Connection
Intel(R) PRO/1000 PL Network Connection
Intel(R) PRO/1000 EB Network Connection with I/O Acceleration
Intel(R) PRO/1000 EB Backplane Connection with I/O Acceleration
Intel(R) PRO/1000 PT Quad Port Server Adapter
- Adapters based on the Intel(R) 82542 and 82573V/E controller do not
support Jumbo Frames. These correspond to the following product names:
Intel(R) PRO/1000 Gigabit Server Adapter
Intel(R) PRO/1000 PM Network Connection
- The following adapters do not support Jumbo Frames:
Intel(R) 82562V 10/100 Network Connection
Intel(R) 82566DM Gigabit Network Connection
Intel(R) 82566DC Gigabit Network Connection
Intel(R) 82566MM Gigabit Network Connection
Intel(R) 82566MC Gigabit Network Connection
Intel(R) 82562GT 10/100 Network Connection
Intel(R) 82562G 10/100 Network Connection
Ethtool
-------
The driver utilizes the ethtool interface for driver configuration and
@ -490,142 +437,14 @@ Additional Configurations
The latest release of ethtool can be found from
http://sourceforge.net/projects/gkernel.
NOTE: Ethtool 1.6 only supports a limited set of ethtool options. Support
for a more complete ethtool feature set can be enabled by upgrading
ethtool to ethtool-1.8.1.
Enabling Wake on LAN* (WoL)
---------------------------
WoL is configured through the Ethtool* utility. Ethtool is included with
all versions of Red Hat after Red Hat 7.2. For other Linux distributions,
download and install Ethtool from the following website:
http://sourceforge.net/projects/gkernel.
For instructions on enabling WoL with Ethtool, refer to the website listed
above.
WoL is configured through the Ethtool* utility.
WoL will be enabled on the system during the next shut down or reboot.
For this driver version, in order to enable WoL, the e1000 driver must be
loaded when shutting down or rebooting the system.
Wake On LAN is only supported on port A for the following devices:
Intel(R) PRO/1000 PT Dual Port Network Connection
Intel(R) PRO/1000 PT Dual Port Server Connection
Intel(R) PRO/1000 PT Dual Port Server Adapter
Intel(R) PRO/1000 PF Dual Port Server Adapter
Intel(R) PRO/1000 PT Quad Port Server Adapter
NAPI
----
NAPI (Rx polling mode) is enabled in the e1000 driver.
See www.cyberus.ca/~hadi/usenix-paper.tgz for more information on NAPI.
Known Issues
============
Dropped Receive Packets on Half-duplex 10/100 Networks
------------------------------------------------------
If you have an Intel PCI Express adapter running at 10mbps or 100mbps, half-
duplex, you may observe occasional dropped receive packets. There are no
workarounds for this problem in this network configuration. The network must
be updated to operate in full-duplex, and/or 1000mbps only.
Jumbo Frames System Requirement
-------------------------------
Memory allocation failures have been observed on Linux systems with 64 MB
of RAM or less that are running Jumbo Frames. If you are using Jumbo
Frames, your system may require more than the advertised minimum
requirement of 64 MB of system memory.
Performance Degradation with Jumbo Frames
-----------------------------------------
Degradation in throughput performance may be observed in some Jumbo frames
environments. If this is observed, increasing the application's socket
buffer size and/or increasing the /proc/sys/net/ipv4/tcp_*mem entry values
may help. See the specific application manual and
/usr/src/linux*/Documentation/
networking/ip-sysctl.txt for more details.
Jumbo Frames on Foundry BigIron 8000 switch
-------------------------------------------
There is a known issue using Jumbo frames when connected to a Foundry
BigIron 8000 switch. This is a 3rd party limitation. If you experience
loss of packets, lower the MTU size.
Allocating Rx Buffers when Using Jumbo Frames
---------------------------------------------
Allocating Rx buffers when using Jumbo Frames on 2.6.x kernels may fail if
the available memory is heavily fragmented. This issue may be seen with PCI-X
adapters or with packet split disabled. This can be reduced or eliminated
by changing the amount of available memory for receive buffer allocation, by
increasing /proc/sys/vm/min_free_kbytes.
Multiple Interfaces on Same Ethernet Broadcast Network
------------------------------------------------------
Due to the default ARP behavior on Linux, it is not possible to have
one system on two IP networks in the same Ethernet broadcast domain
(non-partitioned switch) behave as expected. All Ethernet interfaces
will respond to IP traffic for any IP address assigned to the system.
This results in unbalanced receive traffic.
If you have multiple interfaces in a server, either turn on ARP
filtering by entering:
echo 1 > /proc/sys/net/ipv4/conf/all/arp_filter
(this only works if your kernel's version is higher than 2.4.5),
NOTE: This setting is not saved across reboots. The configuration
change can be made permanent by adding the line:
net.ipv4.conf.all.arp_filter = 1
to the file /etc/sysctl.conf
or,
install the interfaces in separate broadcast domains (either in
different switches or in a switch partitioned to VLANs).
82541/82547 can't link or are slow to link with some link partners
-----------------------------------------------------------------
There is a known compatibility issue with 82541/82547 and some
low-end switches where the link will not be established, or will
be slow to establish. In particular, these switches are known to
be incompatible with 82541/82547:
Planex FXG-08TE
I-O Data ETG-SH8
To workaround this issue, the driver can be compiled with an override
of the PHY's master/slave setting. Forcing master or forcing slave
mode will improve time-to-link.
# make CFLAGS_EXTRA=-DE1000_MASTER_SLAVE=<n>
Where <n> is:
0 = Hardware default
1 = Master mode
2 = Slave mode
3 = Auto master/slave
Disable rx flow control with ethtool
------------------------------------
In order to disable receive flow control using ethtool, you must turn
off auto-negotiation on the same command line.
For example:
ethtool -A eth? autoneg off rx off
Unplugging network cable while ethtool -p is running
----------------------------------------------------
In kernel versions 2.5.50 and later (including 2.6 kernel), unplugging
the network cable while ethtool -p is running will cause the system to
become unresponsive to keyboard commands, except for control-alt-delete.
Restarting the system appears to be the only remedy.
Support
=======

302
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@ -0,0 +1,302 @@
Linux* Driver for Intel(R) Network Connection
===============================================================
Intel Gigabit Linux driver.
Copyright(c) 1999 - 2010 Intel Corporation.
Contents
========
- Identifying Your Adapter
- Command Line Parameters
- Additional Configurations
- Support
Identifying Your Adapter
========================
The e1000e driver supports all PCI Express Intel(R) Gigabit Network
Connections, except those that are 82575, 82576 and 82580-based*.
* NOTE: The Intel(R) PRO/1000 P Dual Port Server Adapter is supported by
the e1000 driver, not the e1000e driver due to the 82546 part being used
behind a PCI Express bridge.
For more information on how to identify your adapter, go to the Adapter &
Driver ID Guide at:
http://support.intel.com/support/go/network/adapter/idguide.htm
For the latest Intel network drivers for Linux, refer to the following
website. In the search field, enter your adapter name or type, or use the
networking link on the left to search for your adapter:
http://support.intel.com/support/go/network/adapter/home.htm
Command Line Parameters
=======================
The default value for each parameter is generally the recommended setting,
unless otherwise noted.
NOTES: For more information about the InterruptThrottleRate,
RxIntDelay, TxIntDelay, RxAbsIntDelay, and TxAbsIntDelay
parameters, see the application note at:
http://www.intel.com/design/network/applnots/ap450.htm
InterruptThrottleRate
---------------------
Valid Range: 0,1,3,4,100-100000 (0=off, 1=dynamic, 3=dynamic conservative,
4=simplified balancing)
Default Value: 3
The driver can limit the amount of interrupts per second that the adapter
will generate for incoming packets. It does this by writing a value to the
adapter that is based on the maximum amount of interrupts that the adapter
will generate per second.
Setting InterruptThrottleRate to a value greater or equal to 100
will program the adapter to send out a maximum of that many interrupts
per second, even if more packets have come in. This reduces interrupt
load on the system and can lower CPU utilization under heavy load,
but will increase latency as packets are not processed as quickly.
The driver has two adaptive modes (setting 1 or 3) in which
it dynamically adjusts the InterruptThrottleRate value based on the traffic
that it receives. After determining the type of incoming traffic in the last
timeframe, it will adjust the InterruptThrottleRate to an appropriate value
for that traffic.
The algorithm classifies the incoming traffic every interval into
classes. Once the class is determined, the InterruptThrottleRate value is
adjusted to suit that traffic type the best. There are three classes defined:
"Bulk traffic", for large amounts of packets of normal size; "Low latency",
for small amounts of traffic and/or a significant percentage of small
packets; and "Lowest latency", for almost completely small packets or
minimal traffic.
In dynamic conservative mode, the InterruptThrottleRate value is set to 4000
for traffic that falls in class "Bulk traffic". If traffic falls in the "Low
latency" or "Lowest latency" class, the InterruptThrottleRate is increased
stepwise to 20000. This default mode is suitable for most applications.
For situations where low latency is vital such as cluster or
grid computing, the algorithm can reduce latency even more when
InterruptThrottleRate is set to mode 1. In this mode, which operates
the same as mode 3, the InterruptThrottleRate will be increased stepwise to
70000 for traffic in class "Lowest latency".
In simplified mode the interrupt rate is based on the ratio of Tx and
Rx traffic. If the bytes per second rate is approximately equal the
interrupt rate will drop as low as 2000 interrupts per second. If the
traffic is mostly transmit or mostly receive, the interrupt rate could
be as high as 8000.
Setting InterruptThrottleRate to 0 turns off any interrupt moderation
and may improve small packet latency, but is generally not suitable
for bulk throughput traffic.
NOTE: InterruptThrottleRate takes precedence over the TxAbsIntDelay and
RxAbsIntDelay parameters. In other words, minimizing the receive
and/or transmit absolute delays does not force the controller to
generate more interrupts than what the Interrupt Throttle Rate
allows.
NOTE: When e1000e is loaded with default settings and multiple adapters
are in use simultaneously, the CPU utilization may increase non-
linearly. In order to limit the CPU utilization without impacting
the overall throughput, we recommend that you load the driver as
follows:
modprobe e1000e InterruptThrottleRate=3000,3000,3000
This sets the InterruptThrottleRate to 3000 interrupts/sec for
the first, second, and third instances of the driver. The range
of 2000 to 3000 interrupts per second works on a majority of
systems and is a good starting point, but the optimal value will
be platform-specific. If CPU utilization is not a concern, use
RX_POLLING (NAPI) and default driver settings.
RxIntDelay
----------
Valid Range: 0-65535 (0=off)
Default Value: 0
This value delays the generation of receive interrupts in units of 1.024
microseconds. Receive interrupt reduction can improve CPU efficiency if
properly tuned for specific network traffic. Increasing this value adds
extra latency to frame reception and can end up decreasing the throughput
of TCP traffic. If the system is reporting dropped receives, this value
may be set too high, causing the driver to run out of available receive
descriptors.
CAUTION: When setting RxIntDelay to a value other than 0, adapters may
hang (stop transmitting) under certain network conditions. If
this occurs a NETDEV WATCHDOG message is logged in the system
event log. In addition, the controller is automatically reset,
restoring the network connection. To eliminate the potential
for the hang ensure that RxIntDelay is set to 0.
RxAbsIntDelay
-------------
Valid Range: 0-65535 (0=off)
Default Value: 8
This value, in units of 1.024 microseconds, limits the delay in which a
receive interrupt is generated. Useful only if RxIntDelay is non-zero,
this value ensures that an interrupt is generated after the initial
packet is received within the set amount of time. Proper tuning,
along with RxIntDelay, may improve traffic throughput in specific network
conditions.
TxIntDelay
----------
Valid Range: 0-65535 (0=off)
Default Value: 8
This value delays the generation of transmit interrupts in units of
1.024 microseconds. Transmit interrupt reduction can improve CPU
efficiency if properly tuned for specific network traffic. If the
system is reporting dropped transmits, this value may be set too high
causing the driver to run out of available transmit descriptors.
TxAbsIntDelay
-------------
Valid Range: 0-65535 (0=off)
Default Value: 32
This value, in units of 1.024 microseconds, limits the delay in which a
transmit interrupt is generated. Useful only if TxIntDelay is non-zero,
this value ensures that an interrupt is generated after the initial
packet is sent on the wire within the set amount of time. Proper tuning,
along with TxIntDelay, may improve traffic throughput in specific
network conditions.
Copybreak
---------
Valid Range: 0-xxxxxxx (0=off)
Default Value: 256
Driver copies all packets below or equaling this size to a fresh Rx
buffer before handing it up the stack.
This parameter is different than other parameters, in that it is a
single (not 1,1,1 etc.) parameter applied to all driver instances and
it is also available during runtime at
/sys/module/e1000e/parameters/copybreak
SmartPowerDownEnable
--------------------
Valid Range: 0-1
Default Value: 0 (disabled)
Allows PHY to turn off in lower power states. The user can set this parameter
in supported chipsets.
KumeranLockLoss
---------------
Valid Range: 0-1
Default Value: 1 (enabled)
This workaround skips resetting the PHY at shutdown for the initial
silicon releases of ICH8 systems.
IntMode
-------
Valid Range: 0-2 (0=legacy, 1=MSI, 2=MSI-X)
Default Value: 2
Allows changing the interrupt mode at module load time, without requiring a
recompile. If the driver load fails to enable a specific interrupt mode, the
driver will try other interrupt modes, from least to most compatible. The
interrupt order is MSI-X, MSI, Legacy. If specifying MSI (IntMode=1)
interrupts, only MSI and Legacy will be attempted.
CrcStripping
------------
Valid Range: 0-1
Default Value: 1 (enabled)
Strip the CRC from received packets before sending up the network stack. If
you have a machine with a BMC enabled but cannot receive IPMI traffic after
loading or enabling the driver, try disabling this feature.
WriteProtectNVM
---------------
Valid Range: 0-1
Default Value: 1 (enabled)
Set the hardware to ignore all write/erase cycles to the GbE region in the
ICHx NVM (non-volatile memory). This feature can be disabled by the
WriteProtectNVM module parameter (enabled by default) only after a hardware
reset, but the machine must be power cycled before trying to enable writes.
Note: the kernel boot option iomem=relaxed may need to be set if the kernel
config option CONFIG_STRICT_DEVMEM=y, if the root user wants to write the
NVM from user space via ethtool.
Additional Configurations
=========================
Jumbo Frames
------------
Jumbo Frames support is enabled by changing the MTU to a value larger than
the default of 1500. Use the ifconfig command to increase the MTU size.
For example:
ifconfig eth<x> mtu 9000 up
This setting is not saved across reboots.
Notes:
- The maximum MTU setting for Jumbo Frames is 9216. This value coincides
with the maximum Jumbo Frames size of 9234 bytes.
- Using Jumbo Frames at 10 or 100 Mbps is not supported and may result in
poor performance or loss of link.
- Some adapters limit Jumbo Frames sized packets to a maximum of
4096 bytes and some adapters do not support Jumbo Frames.
Ethtool
-------
The driver utilizes the ethtool interface for driver configuration and
diagnostics, as well as displaying statistical information. We
strongly recommend downloading the latest version of Ethtool at:
http://sourceforge.net/projects/gkernel.
Speed and Duplex
----------------
Speed and Duplex are configured through the Ethtool* utility. For
instructions, refer to the Ethtool man page.
Enabling Wake on LAN* (WoL)
---------------------------
WoL is configured through the Ethtool* utility. For instructions on
enabling WoL with Ethtool, refer to the Ethtool man page.
WoL will be enabled on the system during the next shut down or reboot.
For this driver version, in order to enable WoL, the e1000e driver must be
loaded when shutting down or rebooting the system.
In most cases Wake On LAN is only supported on port A for multiple port
adapters. To verify if a port supports Wake on LAN run ethtool eth<X>.
Support
=======
For general information, go to the Intel support website at:
www.intel.com/support/
or the Intel Wired Networking project hosted by Sourceforge at:
http://sourceforge.net/projects/e1000
If an issue is identified with the released source code on the supported
kernel with a supported adapter, email the specific information related
to the issue to e1000-devel@lists.sf.net

40
Documentation/networking/ixgbevf.txt Executable file → Normal file
View file

@ -1,19 +1,16 @@
Linux* Base Driver for Intel(R) Network Connection
==================================================
November 24, 2009
Intel Gigabit Linux driver.
Copyright(c) 1999 - 2010 Intel Corporation.
Contents
========
- In This Release
- Identifying Your Adapter
- Known Issues/Troubleshooting
- Support
In This Release
===============
This file describes the ixgbevf Linux* Base Driver for Intel Network
Connection.
@ -33,7 +30,7 @@ Identifying Your Adapter
For more information on how to identify your adapter, go to the Adapter &
Driver ID Guide at:
http://support.intel.com/support/network/sb/CS-008441.htm
http://support.intel.com/support/go/network/adapter/idguide.htm
Known Issues/Troubleshooting
============================
@ -57,34 +54,3 @@ or the Intel Wired Networking project hosted by Sourceforge at:
If an issue is identified with the released source code on the supported
kernel with a supported adapter, email the specific information related
to the issue to e1000-devel@lists.sf.net
License
=======
Intel 10 Gigabit Linux driver.
Copyright(c) 1999 - 2009 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
version 2, as published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
The full GNU General Public License is included in this distribution in
the file called "COPYING".
Trademarks
==========
Intel, Itanium, and Pentium are trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other
countries.
* Other names and brands may be claimed as the property of others.

2
Documentation/vm/page-types.c
View file

@ -478,7 +478,7 @@ static void prepare_hwpoison_fd(void)
}
if (opt_unpoison && !hwpoison_forget_fd) {
sprintf(buf, "%s/renew-pfn", hwpoison_debug_fs);
sprintf(buf, "%s/unpoison-pfn", hwpoison_debug_fs);
hwpoison_forget_fd = checked_open(buf, O_WRONLY);
}
}

38
MAINTAINERS
View file

@ -969,6 +969,16 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-s5p*/
ARM/SAMSUNG S5P SERIES FIMC SUPPORT
M: Kyungmin Park <kyungmin.park@samsung.com>
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
L: linux-arm-kernel@lists.infradead.org
L: linux-media@vger.kernel.org
S: Maintained
F: arch/arm/plat-s5p/dev-fimc*
F: arch/arm/plat-samsung/include/plat/*fimc*
F: drivers/media/video/s5p-fimc/
ARM/SHMOBILE ARM ARCHITECTURE
M: Paul Mundt <lethal@linux-sh.org>
M: Magnus Damm <magnus.damm@gmail.com>
@ -2547,7 +2557,7 @@ S: Supported
F: drivers/scsi/gdt*
GENERIC GPIO I2C DRIVER
M: Haavard Skinnemoen <hskinnemoen@atmel.com>
M: Haavard Skinnemoen <hskinnemoen@gmail.com>
S: Supported
F: drivers/i2c/busses/i2c-gpio.c
F: include/linux/i2c-gpio.h
@ -3075,16 +3085,27 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ixp2000/
INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe)
INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe/ixgbevf)
M: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
M: Jesse Brandeburg <jesse.brandeburg@intel.com>
M: Bruce Allan <bruce.w.allan@intel.com>
M: Alex Duyck <alexander.h.duyck@intel.com>
M: Carolyn Wyborny <carolyn.wyborny@intel.com>
M: Don Skidmore <donald.c.skidmore@intel.com>
M: Greg Rose <gregory.v.rose@intel.com>
M: PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>
M: Alex Duyck <alexander.h.duyck@intel.com>
M: John Ronciak <john.ronciak@intel.com>
L: e1000-devel@lists.sourceforge.net
W: http://e1000.sourceforge.net/
S: Supported
F: Documentation/networking/e100.txt
F: Documentation/networking/e1000.txt
F: Documentation/networking/e1000e.txt
F: Documentation/networking/igb.txt
F: Documentation/networking/igbvf.txt
F: Documentation/networking/ixgb.txt
F: Documentation/networking/ixgbe.txt
F: Documentation/networking/ixgbevf.txt
F: drivers/net/e100.c
F: drivers/net/e1000/
F: drivers/net/e1000e/
@ -3092,6 +3113,7 @@ F: drivers/net/igb/
F: drivers/net/igbvf/
F: drivers/net/ixgb/
F: drivers/net/ixgbe/
F: drivers/net/ixgbevf/
INTEL PRO/WIRELESS 2100 NETWORK CONNECTION SUPPORT
L: linux-wireless@vger.kernel.org
@ -5020,6 +5042,12 @@ F: drivers/media/common/saa7146*
F: drivers/media/video/*7146*
F: include/media/*7146*
SAMSUNG AUDIO (ASoC) DRIVERS
M: Jassi Brar <jassi.brar@samsung.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Supported
F: sound/soc/s3c24xx
TLG2300 VIDEO4LINUX-2 DRIVER
M: Huang Shijie <shijie8@gmail.com>
M: Kang Yong <kangyong@telegent.com>
@ -6462,8 +6490,10 @@ F: include/linux/wm97xx.h
WOLFSON MICROELECTRONICS DRIVERS
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Ian Lartey <ian@opensource.wolfsonmicro.com>
M: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
T: git git://opensource.wolfsonmicro.com/linux-2.6-asoc
T: git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
W: http://opensource.wolfsonmicro.com/node/8
W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
S: Supported
F: Documentation/hwmon/wm83??
F: drivers/leds/leds-wm83*.c

4
Makefile
View file

@ -1,8 +1,8 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 36
EXTRAVERSION = -rc7
NAME = Sheep on Meth
EXTRAVERSION = -rc8
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"

25
arch/arm/Kconfig
View file

@ -680,8 +680,8 @@ config ARCH_S3C64XX
help
Samsung S3C64XX series based systems
config ARCH_S5P6440
bool "Samsung S5P6440"
config ARCH_S5P64X0
bool "Samsung S5P6440 S5P6450"
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
@ -690,7 +690,8 @@ config ARCH_S5P6440
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
help
Samsung S5P6440 CPU based systems
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
config ARCH_S5P6442
bool "Samsung S5P6442"
@ -941,7 +942,7 @@ if ARCH_S3C64XX
source "arch/arm/mach-s3c64xx/Kconfig"
endif
source "arch/arm/mach-s5p6440/Kconfig"
source "arch/arm/mach-s5p64x0/Kconfig"
source "arch/arm/mach-s5p6442/Kconfig"
@ -1114,6 +1115,20 @@ config ARM_ERRATA_720789
invalidated are not, resulting in an incoherency in the system page
tables. The workaround changes the TLB flushing routines to invalidate
entries regardless of the ASID.
config ARM_ERRATA_743622
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
depends on CPU_V7
help
This option enables the workaround for the 743622 Cortex-A9
(r2p0..r2p2) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer
optimisation, preventing the defect from occurring. This has no
visible impact on the overall performance or power consumption of the
processor.
endmenu
source "arch/arm/common/Kconfig"
@ -1270,7 +1285,7 @@ source kernel/Kconfig.preempt
config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91

2
arch/arm/Makefile
View file

@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P6440) := s5p6440
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210

3
arch/arm/configs/s5p6440_defconfig → arch/arm/configs/s5p64x0_defconfig
View file

@ -5,10 +5,11 @@ CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_S5P6440=y
CONFIG_ARCH_S5P64X0=y
CONFIG_S3C_BOOT_ERROR_RESET=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDK6440=y
CONFIG_MACH_SMDK6450=y
CONFIG_CPU_32v6K=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"

7
arch/arm/kernel/kprobes-decode.c
View file

@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
{
/*
* MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
* Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx
* Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
* ALU op with S bit and Rd == 15 :
* cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
*/
if ((insn & 0x0f900000) == 0x03200000 || /* MSR & Undef */
if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
(insn & 0x0ff00000) == 0x03400000 || /* Undef */
(insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
return INSN_REJECTED;
@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
* *S (bit 20) updates condition codes
* ADC/SBC/RSC reads the C flag
*/
insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */
insn &= 0xffff0fff; /* Rd = r0 */
asi->insn[0] = insn;
asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
emulate_alu_imm_rwflags : emulate_alu_imm_rflags;

7
arch/arm/mach-at91/include/mach/system.h
View file

@ -28,7 +28,6 @@
static inline void arch_idle(void)
{
#ifndef CONFIG_DEBUG_KERNEL
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
@ -38,11 +37,11 @@ static inline void arch_idle(void)
#else
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
#endif
#else
#ifndef CONFIG_CPU_ARM920T
/*
* Set the processor (CP15) into 'Wait for Interrupt' mode.
* Unlike disabling the processor clock via the PMC (above)
* this allows the processor to be woken via JTAG.
* Post-RM9200 processors need this in conjunction with the above
* to save power when idle.
*/
cpu_do_idle();
#endif

2
arch/arm/mach-ep93xx/dma-m2p.c
View file

@ -276,7 +276,7 @@ static void channel_disable(struct m2p_channel *ch)
v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
m2p_set_control(ch, v);
while (m2p_channel_state(ch) == STATE_ON)
while (m2p_channel_state(ch) >= STATE_ON)
cpu_relax();
m2p_set_control(ch, 0x0);

1
arch/arm/mach-imx/Kconfig
View file

@ -122,6 +122,7 @@ config MACH_CPUIMX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX27 platform. This includes
specific configurations for the module and its peripherals.

2
arch/arm/mach-imx/mach-cpuimx27.c
View file

@ -258,7 +258,7 @@ static void __init eukrea_cpuimx27_init(void)
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
imx27_add_imx_i2c(1, &cpuimx27_i2c1_data);
imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

33
arch/arm/mach-s5p6440/Kconfig
View file

@ -1,33 +0,0 @@
# arch/arm/mach-s5p6440/Kconfig
#
# Copyright (c) 2009 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
if ARCH_S5P6440
config CPU_S5P6440
bool
select S3C_PL330_DMA
help
Enable S5P6440 CPU support
config S5P6440_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config MACH_SMDK6440
bool "SMDK6440"
select CPU_S5P6440
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_TS
select S5P6440_SETUP_I2C1
help
Machine support for the Samsung SMDK6440
endif

25
arch/arm/mach-s5p6440/Makefile
View file

@ -1,25 +0,0 @@
# arch/arm/mach-s5p6440/Makefile
#
# Copyright (c) 2009 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S5P6440 system
obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o
obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o
# machine support
obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S5P6440_SETUP_I2C1) += setup-i2c1.o

846
arch/arm/mach-s5p6440/clock.c
View file

@ -1,846 +0,0 @@
/* linux/arch/arm/mach-s5p6440/clock.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p-clock.h>
#include <plat/pll.h>
#include <plat/s5p6440.h>
/* APLL Mux output clock */
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};
static int s5p6440_epll_enable(struct clk *clk, int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
if (enable)
__raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
else
__raw_writel(epll_con, S5P_EPLL_CON);
return 0;
}
static unsigned long s5p6440_epll_get_rate(struct clk *clk)
{
return clk->rate;
}
static u32 epll_div[][5] = {
{ 36000000, 0, 48, 1, 4 },
{ 48000000, 0, 32, 1, 3 },
{ 60000000, 0, 40, 1, 3 },
{ 72000000, 0, 48, 1, 3 },
{ 84000000, 0, 28, 1, 2 },
{ 96000000, 0, 32, 1, 2 },
{ 32768000, 45264, 43, 1, 4 },
{ 45158000, 6903, 30, 1, 3 },
{ 49152000, 50332, 32, 1, 3 },
{ 67738000, 10398, 45, 1, 3 },
{ 73728000, 9961, 49, 1, 3 }
};
static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int epll_con, epll_con_k;
unsigned int i;
if (clk->rate == rate) /* Return if nothing changed */
return 0;
epll_con = __raw_readl(S5P_EPLL_CON);
epll_con_k = __raw_readl(S5P_EPLL_CON_K);
epll_con_k &= ~(PLL90XX_KDIV_MASK);
epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
if (epll_div[i][0] == rate) {
epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
(epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
break;
}
}
if (i == ARRAY_SIZE(epll_div)) {
printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
return -EINVAL;
}
__raw_writel(epll_con, S5P_EPLL_CON);
__raw_writel(epll_con_k, S5P_EPLL_CON_K);
clk->rate = rate;
return 0;
}
static struct clk_ops s5p6440_epll_ops = {
.get_rate = s5p6440_epll_get_rate,
.set_rate = s5p6440_epll_set_rate,
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
};
enum perf_level {
L0 = 532*1000,
L1 = 266*1000,
L2 = 133*1000,
};
static const u32 clock_table[][3] = {
/*{ARM_CLK, DIVarm, DIVhclk}*/
{L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
{L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
};
static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv;
/* divisor mask starts at bit0, so no need to shift */
clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
return rate / (clkdiv + 1);
}
static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
unsigned long rate)
{
u32 iter;
for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
if (rate > clock_table[iter][0])
return clock_table[iter-1][0];
}
return clock_table[ARRAY_SIZE(clock_table) - 1][0];
}
static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
{
u32 round_tmp;
u32 iter;
u32 clk_div0_tmp;
u32 cur_rate = clk->ops->get_rate(clk);
unsigned long flags;
round_tmp = clk->ops->round_rate(clk, rate);
if (round_tmp == cur_rate)
return 0;
for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
if (round_tmp == clock_table[iter][0])
break;
}
if (iter >= ARRAY_SIZE(clock_table))
iter = ARRAY_SIZE(clock_table) - 1;
local_irq_save(flags);
if (cur_rate > round_tmp) {
/* Frequency Down */
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
clk_div0_tmp |= clock_table[iter][1];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
~(S5P_CLKDIV0_HCLK_MASK);
clk_div0_tmp |= clock_table[iter][2];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
} else {
/* Frequency Up */
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
~(S5P_CLKDIV0_HCLK_MASK);
clk_div0_tmp |= clock_table[iter][2];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
clk_div0_tmp |= clock_table[iter][1];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
}
local_irq_restore(flags);
clk->rate = clock_table[iter][0];
return 0;
}
static struct clk_ops s5p6440_clkarm_ops = {
.get_rate = s5p6440_armclk_get_rate,
.set_rate = s5p6440_armclk_set_rate,
.round_rate = s5p6440_armclk_round_rate,
};
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
.id = 1,
.parent = &clk_mout_apll.clk,
.ops = &s5p6440_clkarm_ops,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_dout_mpll = {
.clk = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
};
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clk *clkset_hclklow_list[] = {
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};
static struct clksrc_sources clkset_hclklow = {
.sources = clkset_hclklow_list,
.nr_sources = ARRAY_SIZE(clkset_hclklow_list),
};
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "hclk_low",
.id = -1,
},
.sources = &clkset_hclklow,
.reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
};
int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S5P_OTHERS);
if (enable)
val |= S5P_OTHERS_USB_SIG_MASK;
else
val &= ~S5P_OTHERS_USB_SIG_MASK;
__raw_writel(val, S5P_OTHERS);
local_irq_restore(flags);
return 0;
}
static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
}
static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
}
static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
}
static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
}
static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
}
static int s5p6440_mem_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
}
/*
* The following clocks will be disabled during clock initialization. It is
* recommended to keep the following clocks disabled until the driver requests
* for enabling the clock.
*/
static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_mem_ctrl,
.ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_IIC0,
}, {
.name = "i2s_v40",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_IIS2,
}, {
.name = "spi",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_SPI1,
}, {
.name = "sclk_spi_48",
.id = 0,
.parent = &clk_48m,
.enable = s5p6440_sclk_ctrl,
.ctrlbit = S5P_CLKCON_SCLK0_SPI0_48,
}, {
.name = "sclk_spi_48",
.id = 1,
.parent = &clk_48m,
.enable = s5p6440_sclk_ctrl,
.ctrlbit = S5P_CLKCON_SCLK0_SPI1_48,
}, {
.name = "mmc_48m",
.id = 0,
.parent = &clk_48m,
.enable = s5p6440_sclk_ctrl,
.ctrlbit = S5P_CLKCON_SCLK0_MMC0_48,
}, {
.name = "mmc_48m",
.id = 1,
.parent = &clk_48m,
.enable = s5p6440_sclk_ctrl,
.ctrlbit = S5P_CLKCON_SCLK0_MMC1_48,
}, {
.name = "mmc_48m",
.id = 2,
.parent = &clk_48m,
.enable = s5p6440_sclk_ctrl,
.ctrlbit = S5P_CLKCON_SCLK0_MMC2_48,
}, {
.name = "otg",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_USB
}, {
.name = "post",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_POST0
}, {
.name = "lcd",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_WDT,
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_PWM,
}, {
.name = "hclk_fimgvg",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pclk_fimgvg",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "etm",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dsim",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "gps",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "pcm",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "irom",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "dma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "2d",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 8),
},
};
/*
* The following clocks will be enabled during clock initialization.
*/
static struct clk init_clocks[] = {
{
.name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_GPIO,
}, {
.name = "uart",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART3,
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 1),
},
};
static struct clk clk_iis_cd_v40 = {
.name = "iis_cdclk_v40",
.id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
.id = -1,
};
static struct clk *clkset_group1_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
&clk_fin_epll,
};
static struct clksrc_sources clkset_group1 = {
.sources = clkset_group1_list,
.nr_sources = ARRAY_SIZE(clkset_group1_list),
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_audio_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
&clk_fin_epll,
&clk_iis_cd_v40,
&clk_pcm_cd,
};
static struct clksrc_sources clkset_audio = {
.sources = clkset_audio_list,
.nr_sources = ARRAY_SIZE(clkset_audio_list),
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "mmc_bus",
.id = 0,
.ctrlbit = S5P_CLKCON_SCLK0_MMC0,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "mmc_bus",
.id = 1,
.ctrlbit = S5P_CLKCON_SCLK0_MMC1,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "mmc_bus",
.id = 2,
.ctrlbit = S5P_CLKCON_SCLK0_MMC2,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = S5P_CLKCON_SCLK0_UART,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "spi_epll",
.id = 0,
.ctrlbit = S5P_CLKCON_SCLK0_SPI0,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "spi_epll",
.id = 1,
.ctrlbit = S5P_CLKCON_SCLK0_SPI1,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_post",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p6440_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimgvg",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p6440_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_audio2",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_audio,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
},
};
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_dout_mpll,
&clk_armclk,
&clk_hclk,
&clk_pclk,
&clk_hclk_low,
&clk_pclk_low,
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long epll;
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
/* Set S5P6440 functions for clk_fout_epll */
clk_fout_epll.enable = s5p6440_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops;
clk_48m.enable = s5p6440_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
__raw_readl(S5P_EPLL_CON_K));
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
pclk_low = clk_get_rate(&clk_pclk_low.clk);
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_iis_cd_v40,
&clk_pcm_cd,
};
void __init s5p6440_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
if (ret > 0)
printk(KERN_ERR "Failed to register %u clocks\n", ret);
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}

116
arch/arm/mach-s5p6440/cpu.c
View file

@ -1,116 +0,0 @@
/* linux/arch/arm/mach-s5p6440/cpu.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s5p6440.h>
#include <plat/adc-core.h>
static void s5p6440_idle(void)
{
unsigned long val;
if (!need_resched()) {
val = __raw_readl(S5P_PWR_CFG);
val &= ~(0x3<<5);
val |= (0x1<<5);
__raw_writel(val, S5P_PWR_CFG);
cpu_do_idle();
}
local_irq_enable();
}
/* s5p6440_map_io
*
* register the standard cpu IO areas
*/
void __init s5p6440_map_io(void)
{
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
}
void __init s5p6440_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5p6440_register_clocks();
s5p6440_setup_clocks();
}
void __init s5p6440_init_irq(void)
{
/* S5P6440 supports only 2 VIC */
u32 vic[2];
/*
* VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
* VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
*/
vic[0] = 0xff800ae7;
vic[1] = 0xffbf23e5;
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
struct sysdev_class s5p6440_sysclass = {
.name = "s5p6440-core",
};
static struct sys_device s5p6440_sysdev = {
.cls = &s5p6440_sysclass,
};
static int __init s5p6440_core_init(void)
{
return sysdev_class_register(&s5p6440_sysclass);
}
core_initcall(s5p6440_core_init);
int __init s5p6440_init(void)
{
printk(KERN_INFO "S5P6440: Initializing architecture\n");
/* set idle function */
pm_idle = s5p6440_idle;
return sysdev_register(&s5p6440_sysdev);
}

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arch/arm/mach-s5p6440/dev-audio.c
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/* linux/arch/arm/mach-s5p6440/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6440_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case -1:
s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_i2s_pdata = {
.cfg_gpio = s5p6440_cfg_i2s,
};
static struct resource s5p6440_iis0_resource[] = {
[0] = {
.start = S5P6440_PA_I2S,
.end = S5P6440_PA_I2S + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_iis = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6440_iis0_resource),
.resource = s5p6440_iis0_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6440_pcm_cfg_gpio,
};
static struct resource s5p6440_pcm0_resource[] = {
[0] = {
.start = S5P6440_PA_PCM,
.end = S5P6440_PA_PCM + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_pcm = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
.resource = s5p6440_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};

176
arch/arm/mach-s5p6440/dev-spi.c
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/* linux/arch/arm/mach-s5p6440/dev-spi.c
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/dma.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/spi-clocks.h>
#include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h>
static char *spi_src_clks[] = {
[S5P6440_SPI_SRCCLK_PCLK] = "pclk",
[S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
};
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
* The emulated CS is toggled by board specific mechanism, as it can
* be either some immediate GPIO or some signal out of some other
* chip in between ... or some yet another way.
* We simply do not assume anything about CS.
*/
static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
break;
case 1:
s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
return 0;
}
static struct resource s5p6440_spi0_resource[] = {
[0] = {
.start = S5P6440_PA_SPI0,
.end = S5P6440_PA_SPI0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_SPI0_TX,
.end = DMACH_SPI0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_SPI0_RX,
.end = DMACH_SPI0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_SPI0,
.end = IRQ_SPI0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
.cfg_gpio = s5p6440_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15,
};
static u64 spi_dmamask = DMA_BIT_MASK(32);
struct platform_device s5p6440_device_spi0 = {
.name = "s3c64xx-spi",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6440_spi0_resource),
.resource = s5p6440_spi0_resource,
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6440_spi0_pdata,
},
};
static struct resource s5p6440_spi1_resource[] = {
[0] = {
.start = S5P6440_PA_SPI1,
.end = S5P6440_PA_SPI1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_SPI1_TX,
.end = DMACH_SPI1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_SPI1_RX,
.end = DMACH_SPI1_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_SPI1,
.end = IRQ_SPI1,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
.cfg_gpio = s5p6440_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 15,
};
struct platform_device s5p6440_device_spi1 = {
.name = "s3c64xx-spi",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6440_spi1_resource),
.resource = s5p6440_spi1_resource,
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6440_spi1_pdata,
},
};
void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
{
struct s3c64xx_spi_info *pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0
|| src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
return;
}
switch (cntrlr) {
case 0:
pd = &s5p6440_spi0_pdata;
break;
case 1:
pd = &s5p6440_spi1_pdata;
break;
default:
printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
__func__, cntrlr);
return;
}
pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = spi_src_clks[src_clk_nr];
}

37
arch/arm/mach-s5p6440/include/mach/debug-macro.S
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/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
.macro addruart, rx, rtmp
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C_PA_UART
ldrne \rx, = S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>

80
arch/arm/mach-s5p6440/include/mach/gpio.h
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/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S5P6440_GPIO_A_NR (6)
#define S5P6440_GPIO_B_NR (7)
#define S5P6440_GPIO_C_NR (8)
#define S5P6440_GPIO_F_NR (2)
#define S5P6440_GPIO_G_NR (7)
#define S5P6440_GPIO_H_NR (10)
#define S5P6440_GPIO_I_NR (16)
#define S5P6440_GPIO_J_NR (12)
#define S5P6440_GPIO_N_NR (16)
#define S5P6440_GPIO_P_NR (8)
#define S5P6440_GPIO_R_NR (15)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5P6440_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
S5P6440_GPIO_A_START = 0,
S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
};
/* S5P6440 GPIO number definitions. */
#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
/* the end of the S5P6440 specific gpios */
#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
#define S3C_GPIO_END S5P6440_GPIO_END
/* define the number of gpios we need to the one after the GPR() range */
#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */

18
arch/arm/mach-s5p6440/include/mach/io.h
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@ -1,18 +0,0 @@
/* arch/arm/mach-s5p6440/include/mach/io.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for S3C64XX based
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif

86
arch/arm/mach-s5p6440/include/mach/map.h
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/* linux/arch/arm/mach-s5p6440/include/mach/map.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P6440_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5P6440_PA_CHIPID
#define S5P6440_PA_SYSCON (0xE0100000)
#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0)
#define S5P_PA_SYSCON S5P6440_PA_SYSCON
#define S5P6440_PA_GPIO (0xE0308000)
#define S5P_PA_GPIO S5P6440_PA_GPIO
#define S5P6440_PA_VIC0 (0xE4000000)
#define S5P_PA_VIC0 S5P6440_PA_VIC0
#define S5P6440_PA_PDMA 0xE9000000
#define S5P6440_PA_VIC1 (0xE4100000)
#define S5P_PA_VIC1 S5P6440_PA_VIC1
#define S5P6440_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5P6440_PA_TIMER
#define S5P6440_PA_RTC (0xEA100000)
#define S5P6440_PA_WDT (0xEA200000)
#define S5P_PA_WDT S5P6440_PA_WDT
#define S5P6440_PA_UART (0xEC000000)
#define S5P_PA_UART0 (S5P6440_PA_UART + 0x0)
#define S5P_PA_UART1 (S5P6440_PA_UART + 0x400)
#define S5P_PA_UART2 (S5P6440_PA_UART + 0x800)
#define S5P_PA_UART3 (S5P6440_PA_UART + 0xC00)
#define S5P_SZ_UART SZ_256
#define S5P6440_PA_IIC0 (0xEC104000)
#define S5P6440_PA_IIC1 (0xEC20F000)
#define S5P6440_PA_SPI0 0xEC400000
#define S5P6440_PA_SPI1 0xEC500000
#define S5P6440_PA_HSOTG (0xED100000)
#define S5P6440_PA_HSMMC0 (0xED800000)
#define S5P6440_PA_HSMMC1 (0xED900000)
#define S5P6440_PA_HSMMC2 (0xEDA00000)
#define S5P6440_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6440_PA_SDRAM
/* I2S */
#define S5P6440_PA_I2S 0xF2000000
/* PCM */
#define S5P6440_PA_PCM 0xF2100000
#define S5P6440_PA_ADC (0xF3000000)
/* compatibiltiy defines. */
#define S3C_PA_UART S5P6440_PA_UART
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_RTC S5P6440_PA_RTC
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_WDT S5P6440_PA_WDT
#define SAMSUNG_PA_ADC S5P6440_PA_ADC
#endif /* __ASM_ARCH_MAP_H */

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arch/arm/mach-s5p6440/include/mach/regs-clock.h
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/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
#define S5P_APLL_CON S5P_CLKREG(0x0C)
#define S5P_MPLL_CON S5P_CLKREG(0x10)
#define S5P_EPLL_CON S5P_CLKREG(0x14)
#define S5P_EPLL_CON_K S5P_CLKREG(0x18)
#define S5P_CLK_SRC0 S5P_CLKREG(0x1C)
#define S5P_CLK_DIV0 S5P_CLKREG(0x20)
#define S5P_CLK_DIV1 S5P_CLKREG(0x24)
#define S5P_CLK_DIV2 S5P_CLKREG(0x28)
#define S5P_CLK_OUT S5P_CLKREG(0x2C)
#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34)
#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
#define S5P_CLK_DIV3 S5P_CLKREG(0x40)
#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
#define S5P_AHB_CON0 S5P_CLKREG(0x100)
#define S5P_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P_SWRESET S5P_CLKREG(0x114)
#define S5P_SYS_ID S5P_CLKREG(0x118)
#define S5P_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
#define S5P_PWR_CFG S5P_CLKREG(0x804)
#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
#define S5P_STOP_CFG S5P_CLKREG(0x814)
#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
#define S5P_OSC_FREQ S5P_CLKREG(0x820)
#define S5P_OSC_STABLE S5P_CLKREG(0x824)
#define S5P_PWR_STABLE S5P_CLKREG(0x828)
#define S5P_MTC_STABLE S5P_CLKREG(0x830)
#define S5P_OTHERS S5P_CLKREG(0x900)
#define S5P_RST_STAT S5P_CLKREG(0x904)
#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
#define S5P_SLPEN S5P_CLKREG(0x930)
#define S5P_INFORM0 S5P_CLKREG(0xA00)
#define S5P_INFORM1 S5P_CLKREG(0xA04)
#define S5P_INFORM2 S5P_CLKREG(0xA08)
#define S5P_INFORM3 S5P_CLKREG(0xA0C)
/* CLKDIV0 */
#define S5P_CLKDIV0_PCLK_MASK (0xf << 12)
#define S5P_CLKDIV0_PCLK_SHIFT (12)
#define S5P_CLKDIV0_HCLK_MASK (0xf << 8)
#define S5P_CLKDIV0_HCLK_SHIFT (8)
#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4)
#define S5P_CLKDIV0_ARM_MASK (0xf << 0)
#define S5P_CLKDIV0_ARM_SHIFT (0)
/* CLKDIV3 */
#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12)
#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12)
#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8)
#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8)
/* HCLK0 GATE Registers */
#define S5P_CLKCON_HCLK0_USB (1<<20)
#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19)
#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18)
#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17)
#define S5P_CLKCON_HCLK0_POST0 (1<<5)
/* HCLK1 GATE Registers */
#define S5P_CLKCON_HCLK1_DISPCON (1<<1)
/* PCLK GATE Registers */
#define S5P_CLKCON_PCLK_IIS2 (1<<26)
#define S5P_CLKCON_PCLK_SPI1 (1<<22)
#define S5P_CLKCON_PCLK_SPI0 (1<<21)
#define S5P_CLKCON_PCLK_GPIO (1<<18)
#define S5P_CLKCON_PCLK_IIC0 (1<<17)
#define S5P_CLKCON_PCLK_TSADC (1<<12)
#define S5P_CLKCON_PCLK_PWM (1<<7)
#define S5P_CLKCON_PCLK_RTC (1<<6)
#define S5P_CLKCON_PCLK_WDT (1<<5)
#define S5P_CLKCON_PCLK_UART3 (1<<4)
#define S5P_CLKCON_PCLK_UART2 (1<<3)
#define S5P_CLKCON_PCLK_UART1 (1<<2)
#define S5P_CLKCON_PCLK_UART0 (1<<1)
/* SCLK0 GATE Registers */
#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29)
#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28)
#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27)
#define S5P_CLKCON_SCLK0_MMC2 (1<<26)
#define S5P_CLKCON_SCLK0_MMC1 (1<<25)
#define S5P_CLKCON_SCLK0_MMC0 (1<<24)
#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23)
#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22)
#define S5P_CLKCON_SCLK0_SPI1 (1<<21)
#define S5P_CLKCON_SCLK0_SPI0 (1<<20)
#define S5P_CLKCON_SCLK0_UART (1<<5)
/* SCLK1 GATE Registers */
/* MEM0 GATE Registers */
#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2)
/*OTHERS Resgister */
#define S5P_OTHERS_USB_SIG_MASK (1<<16)
#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6)
/* Compatibility defines */
#define ARM_CLK_DIV S5P_CLK_DIV0
#define ARM_DIV_RATIO_SHIFT 0
#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT)
#endif /* __ASM_ARCH_REGS_CLOCK_H */

17
arch/arm/mach-s5p6440/include/mach/spi-clocks.h
View file

@ -1,17 +0,0 @@
/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __S5P6440_PLAT_SPI_CLKS_H
#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
#define S5P6440_SPI_SRCCLK_PCLK 0
#define S5P6440_SPI_SRCCLK_SCLK 1
#endif /* __S5P6440_PLAT_SPI_CLKS_H */

24
arch/arm/mach-s5p6440/include/mach/uncompress.h
View file

@ -1,24 +0,0 @@
/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
#include <plat/uncompress.h>
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */

52
arch/arm/mach-s5p6440/init.c
View file

@ -1,52 +0,0 @@
/* linux/arch/arm/mach-s5p6440/init.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - Init support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s5p6440.h>
#include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = {
[0] = {
.name = "pclk_low",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
[1] = {
.name = "uclk1",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
};
/* uart registration process */
void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->clocks = s5p6440_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks);
}
}
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}

28
arch/arm/mach-s5p6442/cpu.c
View file

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5p6442/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -19,6 +19,7 @@
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -46,11 +47,31 @@ static struct map_desc s5p6442_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5P6442_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5P6442_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5P6442_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5P6442_PA_VIC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}
};
@ -62,10 +83,11 @@ static void s5p6442_idle(void)
local_irq_enable();
}
/* s5p6442_map_io
/*
* s5p6442_map_io
*
* register the standard cpu IO areas
*/
*/
void __init s5p6442_map_io(void)
{

6
arch/arm/mach-s5p6442/include/mach/map.h
View file

@ -23,16 +23,10 @@
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P6442_PA_GPIO (0xE0200000)
#define S5P_PA_GPIO S5P6442_PA_GPIO
#define S5P6442_PA_VIC0 (0xE4000000)
#define S5P_PA_VIC0 S5P6442_PA_VIC0
#define S5P6442_PA_VIC1 (0xE4100000)
#define S5P_PA_VIC1 S5P6442_PA_VIC1
#define S5P6442_PA_VIC2 (0xE4200000)
#define S5P_PA_VIC2 S5P6442_PA_VIC2
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000

57
arch/arm/mach-s5p64x0/Kconfig Normal file
View file

@ -0,0 +1,57 @@
# arch/arm/mach-s5p64x0/Kconfig
#
# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
if ARCH_S5P64X0
config CPU_S5P6440
bool
select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5P6440 CPU support
config CPU_S5P6450
bool
select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5P6450 CPU support
config S5P64X0_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
# machine support
config MACH_SMDK6440
bool "SMDK6440"
select CPU_S5P6440
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C64XX_DEV_SPI
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_I2C1
help
Machine support for the Samsung SMDK6440
config MACH_SMDK6450
bool "SMDK6450"
select CPU_S5P6450
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C64XX_DEV_SPI
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_I2C1
help
Machine support for the Samsung SMDK6450
endif

30
arch/arm/mach-s5p64x0/Makefile Normal file
View file

@ -0,0 +1,30 @@
# arch/arm/mach-s5p64x0/Makefile
#
# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S5P64X0 system
obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
# machine support
obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o

0
arch/arm/mach-s5p6440/Makefile.boot → arch/arm/mach-s5p64x0/Makefile.boot
View file

626
arch/arm/mach-s5p64x0/clock-s5p6440.c Normal file
View file

@ -0,0 +1,626 @@
/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6440.h>
static u32 epll_div[][5] = {
{ 36000000, 0, 48, 1, 4 },
{ 48000000, 0, 32, 1, 3 },
{ 60000000, 0, 40, 1, 3 },
{ 72000000, 0, 48, 1, 3 },
{ 84000000, 0, 28, 1, 2 },
{ 96000000, 0, 32, 1, 2 },
{ 32768000, 45264, 43, 1, 4 },
{ 45158000, 6903, 30, 1, 3 },
{ 49152000, 50332, 32, 1, 3 },
{ 67738000, 10398, 45, 1, 3 },
{ 73728000, 9961, 49, 1, 3 }
};
static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int epll_con, epll_con_k;
unsigned int i;
if (clk->rate == rate) /* Return if nothing changed */
return 0;
epll_con = __raw_readl(S5P64X0_EPLL_CON);
epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
epll_con_k &= ~(PLL90XX_KDIV_MASK);
epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
if (epll_div[i][0] == rate) {
epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
(epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
break;
}
}
if (i == ARRAY_SIZE(epll_div)) {
printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
return -EINVAL;
}
__raw_writel(epll_con, S5P64X0_EPLL_CON);
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
clk->rate = rate;
return 0;
}
static struct clk_ops s5p6440_epll_ops = {
.get_rate = s5p64x0_epll_get_rate,
.set_rate = s5p6440_epll_set_rate,
};
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
};
/*
* The following clocks will be disabled during clock initialization. It is
* recommended to keep the following clocks disabled until the driver requests
* for enabling the clock.
*/
static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_mem_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "post",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 5)
}, {
.name = "2d",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "otg",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20)
}, {
.name = "irom",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hclk_fimgvg",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "pcm",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "gps",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "i2s_v40",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "dsim",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "etm",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "pclk_fimgvg",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "sclk_spi_48",
.id = 0,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "sclk_spi_48",
.id = 1,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "mmc_48m",
.id = 0,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "mmc_48m",
.id = 1,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "mmc_48m",
.id = 2,
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 29),
},
};
/*
* The following clocks will be enabled during clock initialization.
*/
static struct clk init_clocks[] = {
{
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "dma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "uart",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 3,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
},
};
static struct clk clk_iis_cd_v40 = {
.name = "iis_cdclk_v40",
.id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
.id = -1,
};
static struct clk *clkset_group1_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
&clk_fin_epll,
};
static struct clksrc_sources clkset_group1 = {
.sources = clkset_group1_list,
.nr_sources = ARRAY_SIZE(clkset_group1_list),
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_audio_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
&clk_fin_epll,
&clk_iis_cd_v40,
&clk_pcm_cd,
};
static struct clksrc_sources clkset_audio = {
.sources = clkset_audio_list,
.nr_sources = ARRAY_SIZE(clkset_audio_list),
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "mmc_bus",
.id = 0,
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "mmc_bus",
.id = 1,
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "mmc_bus",
.id = 2,
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_post",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimgvg",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_audio2",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_audio,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
},
};
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_dout_mpll,
&clk_armclk,
&clk_hclk,
&clk_pclk,
&clk_hclk_low,
&clk_pclk_low,
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned int ptr;
/* Set S5P6440 functions for clk_fout_epll */
clk_fout_epll.enable = s5p64x0_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops;
clk_48m.enable = s5p64x0_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
__raw_readl(S5P64X0_EPLL_CON_K));
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
pclk_low = clk_get_rate(&clk_pclk_low.clk);
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_iis_cd_v40,
&clk_pcm_cd,
};
void __init s5p6440_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}

655
arch/arm/mach-s5p64x0/clock-s5p6450.c Normal file
View file

@ -0,0 +1,655 @@
/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6450 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6450.h>
static struct clksrc_clk clk_mout_dpll = {
.clk = {
.name = "mout_dpll",
.id = -1,
},
.sources = &clk_src_dpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
};
static u32 epll_div[][5] = {
{ 133000000, 27307, 55, 2, 2 },
{ 100000000, 43691, 41, 2, 2 },
{ 480000000, 0, 80, 2, 0 },
};
static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int epll_con, epll_con_k;
unsigned int i;
if (clk->rate == rate) /* Return if nothing changed */
return 0;
epll_con = __raw_readl(S5P64X0_EPLL_CON);
epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
epll_con_k &= ~(PLL90XX_KDIV_MASK);
epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
if (epll_div[i][0] == rate) {
epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
(epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
break;
}
}
if (i == ARRAY_SIZE(epll_div)) {
printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
return -EINVAL;
}
__raw_writel(epll_con, S5P64X0_EPLL_CON);
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
clk->rate = rate;
return 0;
}
static struct clk_ops s5p6450_epll_ops = {
.get_rate = s5p64x0_epll_get_rate,
.set_rate = s5p6450_epll_set_rate,
};
static struct clksrc_clk clk_dout_epll = {
.clk = {
.name = "dout_epll",
.id = -1,
.parent = &clk_mout_epll.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
};
static struct clksrc_clk clk_mout_hclk_sel = {
.clk = {
.name = "mout_hclk_sel",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
};
static struct clk *clkset_hclk_list[] = {
&clk_mout_hclk_sel.clk,
&clk_armclk.clk,
};
static struct clksrc_sources clkset_hclk = {
.sources = clkset_hclk_list,
.nr_sources = ARRAY_SIZE(clkset_hclk_list),
};
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
},
.sources = &clkset_hclk,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clksrc_clk clk_dout_pwm_ratio0 = {
.clk = {
.name = "clk_dout_pwm_ratio0",
.id = -1,
.parent = &clk_mout_hclk_sel.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
};
static struct clksrc_clk clk_pclk_to_wdt_pwm = {
.clk = {
.name = "clk_pclk_to_wdt_pwm",
.id = -1,
.parent = &clk_dout_pwm_ratio0.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
};
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
};
/*
* The following clocks will be disabled during clock initialization. It is
* recommended to keep the following clocks disabled until the driver requests
* for enabling the clock.
*/
static struct clk init_clocks_disable[] = {
{
.name = "usbhost",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "usbotg",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "i2c",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
}
};
/*
* The following clocks will be enabled during clock initialization.
*/
static struct clk init_clocks[] = {
{
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "dma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "uart",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 3,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_to_wdt_pwm.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
},
};
static struct clk *clkset_uart_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_mali_list[] = {
&clk_mout_epll.clk,
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};
static struct clksrc_sources clkset_mali = {
.sources = clkset_mali_list,
.nr_sources = ARRAY_SIZE(clkset_mali_list),
};
static struct clk *clkset_group2_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
&clk_ext_xtal_mux,
};
static struct clksrc_sources clkset_group2 = {
.sources = clkset_group2_list,
.nr_sources = ARRAY_SIZE(clkset_group2_list),
};
static struct clk *clkset_dispcon_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
&clk_ext_xtal_mux,
&clk_mout_dpll.clk,
};
static struct clksrc_sources clkset_dispcon = {
.sources = clkset_dispcon_list,
.nr_sources = ARRAY_SIZE(clkset_dispcon_list),
};
static struct clk *clkset_hsmmc44_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
&clk_ext_xtal_mux,
&s5p_clk_27m,
&clk_48m,
};
static struct clksrc_sources clkset_hsmmc44 = {
.sources = clkset_hsmmc44_list,
.nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
};
static struct clk *clkset_sclk_audio0_list[] = {
[0] = &clk_dout_epll.clk,
[1] = &clk_dout_mpll.clk,
[2] = &clk_ext_xtal_mux,
[3] = NULL,
[4] = NULL,
};
static struct clksrc_sources clkset_sclk_audio0 = {
.sources = clkset_sclk_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
};
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "audio-bus",
.id = -1,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk,
},
.sources = &clkset_sclk_audio0,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
.id = 0,
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "aclk_mali",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
.sources = &clkset_mali,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_2d",
.id = -1,
.ctrlbit = (1 << 12),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_mali,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_usi",
.id = -1,
.ctrlbit = (1 << 7),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_camif",
.id = -1,
.ctrlbit = (1 << 6),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
.sources = &clkset_dispcon,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_hsmmc44",
.id = -1,
.ctrlbit = (1 << 30),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_hsmmc44,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
},
};
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_dout_epll,
&clk_mout_mpll,
&clk_dout_mpll,
&clk_armclk,
&clk_mout_hclk_sel,
&clk_dout_pwm_ratio0,
&clk_pclk_to_wdt_pwm,
&clk_hclk,
&clk_pclk,
&clk_hclk_low,
&clk_pclk_low,
&clk_sclk_audio0,
};
void __init_or_cpufreq s5p6450_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned long dpll;
unsigned int ptr;
/* Set S5P6450 functions for clk_fout_epll */
clk_fout_epll.enable = s5p64x0_epll_enable;
clk_fout_epll.ops = &s5p6450_epll_ops;
clk_48m.enable = s5p64x0_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
__raw_readl(S5P64X0_EPLL_CON_K));
dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
__raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_dpll.rate = dpll;
printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll),
print_mhz(dpll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
pclk_low = clk_get_rate(&clk_pclk_low.clk);
printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
void __init s5p6450_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}

253
arch/arm/mach-s5p64x0/clock.c Normal file
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/* linux/arch/arm/mach-s5p64x0/clock.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6440.h>
#include <plat/s5p6450.h>
struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
};
struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
};
struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
};
enum perf_level {
L0 = 532*1000,
L1 = 266*1000,
L2 = 133*1000,
};
static const u32 clock_table[][3] = {
/*{ARM_CLK, DIVarm, DIVhclk}*/
{L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
{L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
};
int s5p64x0_epll_enable(struct clk *clk, int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
if (enable)
__raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
else
__raw_writel(epll_con, S5P64X0_EPLL_CON);
return 0;
}
unsigned long s5p64x0_epll_get_rate(struct clk *clk)
{
return clk->rate;
}
unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv;
/* divisor mask starts at bit0, so no need to shift */
clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
return rate / (clkdiv + 1);
}
unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
{
u32 iter;
for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
if (rate > clock_table[iter][0])
return clock_table[iter-1][0];
}
return clock_table[ARRAY_SIZE(clock_table) - 1][0];
}
int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
{
u32 round_tmp;
u32 iter;
u32 clk_div0_tmp;
u32 cur_rate = clk->ops->get_rate(clk);
unsigned long flags;
round_tmp = clk->ops->round_rate(clk, rate);
if (round_tmp == cur_rate)
return 0;
for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
if (round_tmp == clock_table[iter][0])
break;
}
if (iter >= ARRAY_SIZE(clock_table))
iter = ARRAY_SIZE(clock_table) - 1;
local_irq_save(flags);
if (cur_rate > round_tmp) {
/* Frequency Down */
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
clk_div0_tmp |= clock_table[iter][1];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
~(S5P64X0_CLKDIV0_HCLK_MASK);
clk_div0_tmp |= clock_table[iter][2];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
} else {
/* Frequency Up */
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
~(S5P64X0_CLKDIV0_HCLK_MASK);
clk_div0_tmp |= clock_table[iter][2];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
clk_div0_tmp |= clock_table[iter][1];
__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
}
local_irq_restore(flags);
clk->rate = clock_table[iter][0];
return 0;
}
struct clk_ops s5p64x0_clkarm_ops = {
.get_rate = s5p64x0_armclk_get_rate,
.set_rate = s5p64x0_armclk_set_rate,
.round_rate = s5p64x0_armclk_round_rate,
};
struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
.id = 1,
.parent = &clk_mout_apll.clk,
.ops = &s5p64x0_clkarm_ops,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
};
struct clksrc_clk clk_dout_mpll = {
.clk = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
};
struct clk *clkset_hclk_low_list[] = {
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};
struct clksrc_sources clkset_hclk_low = {
.sources = clkset_hclk_low_list,
.nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
};
int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
}
int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
}
int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
}
int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
}
int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
}
int s5p64x0_mem_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
}
int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S5P64X0_OTHERS);
if (enable)
val |= S5P64X0_OTHERS_USB_SIG_MASK;
else
val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
__raw_writel(val, S5P64X0_OTHERS);
local_irq_restore(flags);
return 0;
}

209
arch/arm/mach-s5p64x0/cpu.c Normal file
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/* linux/arch/arm/mach-s5p64x0/cpu.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s5p6440.h>
#include <plat/s5p6450.h>
#include <plat/adc-core.h>
/* Initial IO mappings */
static struct map_desc s5p64x0_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
},
};
static struct map_desc s5p6440_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static struct map_desc s5p6450_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART + SZ_512K,
.pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void s5p64x0_idle(void)
{
unsigned long val;
if (!need_resched()) {
val = __raw_readl(S5P64X0_PWR_CFG);
val &= ~(0x3 << 5);
val |= (0x1 << 5);
__raw_writel(val, S5P64X0_PWR_CFG);
cpu_do_idle();
}
local_irq_enable();
}
/*
* s5p64x0_map_io
*
* register the standard CPU IO areas
*/
void __init s5p6440_map_io(void)
{
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
}
void __init s5p6450_map_io(void)
{
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
}
/*
* s5p64x0_init_clocks
*
* register and setup the CPU clocks
*/
void __init s5p6440_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5p6440_register_clocks();
s5p6440_setup_clocks();
}
void __init s5p6450_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5p6450_register_clocks();
s5p6450_setup_clocks();
}
/*
* s5p64x0_init_irq
*
* register the CPU interrupts
*/
void __init s5p6440_init_irq(void)
{
/* S5P6440 supports 2 VIC */
u32 vic[2];
/*
* VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
* VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
*/
vic[0] = 0xff800ae7;
vic[1] = 0xffbf23e5;
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
void __init s5p6450_init_irq(void)
{
/* S5P6450 supports only 2 VIC */
u32 vic[2];
/*
* VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
* VIC1 is missing IRQ VIC1[12, 14, 23]
*/
vic[0] = 0xff9f1fff;
vic[1] = 0xff7fafff;
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
struct sysdev_class s5p64x0_sysclass = {
.name = "s5p64x0-core",
};
static struct sys_device s5p64x0_sysdev = {
.cls = &s5p64x0_sysclass,
};
static int __init s5p64x0_core_init(void)
{
return sysdev_class_register(&s5p64x0_sysclass);
}
core_initcall(s5p64x0_core_init);
int __init s5p64x0_init(void)
{
printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
/* set idle function */
pm_idle = s5p64x0_idle;
return sysdev_register(&s5p64x0_sysdev);
}

164
arch/arm/mach-s5p64x0/dev-audio.c Normal file
View file

@ -0,0 +1,164 @@
/* linux/arch/arm/mach-s5p64x0/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6440_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case -1:
s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static int s5p6450_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case -1:
s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s5p6440_i2s_pdata = {
.cfg_gpio = s5p6440_cfg_i2s,
};
static struct s3c_audio_pdata s5p6450_i2s_pdata = {
.cfg_gpio = s5p6450_cfg_i2s,
};
static struct resource s5p64x0_iis0_resource[] = {
[0] = {
.start = S5P64X0_PA_I2S,
.end = S5P64X0_PA_I2S + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_iis = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p64x0_iis0_resource),
.resource = s5p64x0_iis0_resource,
.dev = {
.platform_data = &s5p6440_i2s_pdata,
},
};
struct platform_device s5p6450_device_iis0 = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p64x0_iis0_resource),
.resource = s5p64x0_iis0_resource,
.dev = {
.platform_data = &s5p6450_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s5p6440_pcm_pdata = {
.cfg_gpio = s5p6440_pcm_cfg_gpio,
};
static struct resource s5p6440_pcm0_resource[] = {
[0] = {
.start = S5P64X0_PA_PCM,
.end = S5P64X0_PA_PCM + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_pcm = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
.resource = s5p6440_pcm0_resource,
.dev = {
.platform_data = &s5p6440_pcm_pdata,
},
};

232
arch/arm/mach-s5p64x0/dev-spi.c Normal file
View file

@ -0,0 +1,232 @@
/* linux/arch/arm/mach-s5p64x0/dev-spi.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/dma.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/regs-clock.h>
#include <mach/spi-clocks.h>
#include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h>
static char *s5p64x0_spi_src_clks[] = {
[S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
[S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
};
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
* The emulated CS is toggled by board specific mechanism, as it can
* be either some immediate GPIO or some signal out of some other
* chip in between ... or some yet another way.
* We simply do not assume anything about CS.
*/
static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
break;
case 1:
s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
return 0;
}
static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
break;
case 1:
s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
return 0;
}
static struct resource s5p64x0_spi0_resource[] = {
[0] = {
.start = S5P64X0_PA_SPI0,
.end = S5P64X0_PA_SPI0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_SPI0_TX,
.end = DMACH_SPI0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_SPI0_RX,
.end = DMACH_SPI0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_SPI0,
.end = IRQ_SPI0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
.cfg_gpio = s5p6440_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15,
};
static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
.cfg_gpio = s5p6450_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15,
};
static u64 spi_dmamask = DMA_BIT_MASK(32);
struct platform_device s5p64x0_device_spi0 = {
.name = "s3c64xx-spi",
.id = 0,
.num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
.resource = s5p64x0_spi0_resource,
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource s5p64x0_spi1_resource[] = {
[0] = {
.start = S5P64X0_PA_SPI1,
.end = S5P64X0_PA_SPI1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_SPI1_TX,
.end = DMACH_SPI1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_SPI1_RX,
.end = DMACH_SPI1_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_SPI1,
.end = IRQ_SPI1,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
.cfg_gpio = s5p6440_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 15,
};
static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
.cfg_gpio = s5p6450_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 15,
};
struct platform_device s5p64x0_device_spi1 = {
.name = "s3c64xx-spi",
.id = 1,
.num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
.resource = s5p64x0_spi1_resource,
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
{
unsigned int id;
struct s3c64xx_spi_info *pd;
id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0
|| src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
return;
}
switch (cntrlr) {
case 0:
if (id == 0x50000)
pd = &s5p6450_spi0_pdata;
else
pd = &s5p6440_spi0_pdata;
s5p64x0_device_spi0.dev.platform_data = pd;
break;
case 1:
if (id == 0x50000)
pd = &s5p6450_spi1_pdata;
else
pd = &s5p6440_spi1_pdata;
s5p64x0_device_spi1.dev.platform_data = pd;
break;
default:
printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
__func__, cntrlr);
return;
}
pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
}

90
arch/arm/mach-s5p6440/dma.c → arch/arm/mach-s5p64x0/dma.c
View file

@ -1,4 +1,8 @@
/*
/* linux/arch/arm/mach-s5p64x0/dma.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
@ -15,26 +19,25 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/regs-clock.h>
#include <plat/devs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6440_pdma_resource[] = {
static struct resource s5p64x0_pdma_resource[] = {
[0] = {
.start = S5P6440_PA_PDMA,
.end = S5P6440_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
.start = S5P64X0_PA_PDMA,
.end = S5P64X0_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DMA0,
@ -80,26 +83,67 @@ static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
},
};
static struct platform_device s5p6440_device_pdma = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6440_pdma_resource),
.resource = s5p6440_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6440_pdma_pdata,
static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_UART4_RX,
[9] = DMACH_UART4_TX,
[10] = DMACH_PCM0_TX,
[11] = DMACH_PCM0_RX,
[12] = DMACH_I2S0_TX,
[13] = DMACH_I2S0_RX,
[14] = DMACH_SPI0_TX,
[15] = DMACH_SPI0_RX,
[16] = DMACH_PCM1_TX,
[17] = DMACH_PCM1_RX,
[18] = DMACH_PCM2_TX,
[19] = DMACH_PCM2_RX,
[20] = DMACH_SPI1_TX,
[21] = DMACH_SPI1_RX,
[22] = DMACH_USI_TX,
[23] = DMACH_USI_RX,
[24] = DMACH_MAX,
[25] = DMACH_I2S1_TX,
[26] = DMACH_I2S1_RX,
[27] = DMACH_I2S2_TX,
[28] = DMACH_I2S2_RX,
[29] = DMACH_PWM,
[30] = DMACH_UART5_RX,
[31] = DMACH_UART5_TX,
},
};
static struct platform_device *s5p6440_dmacs[] __initdata = {
&s5p6440_device_pdma,
static struct platform_device s5p64x0_device_pdma = {
.name = "s3c-pl330",
.id = 0,
.num_resources = ARRAY_SIZE(s5p64x0_pdma_resource),
.resource = s5p64x0_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static int __init s5p6440_dma_init(void)
static int __init s5p64x0_dma_init(void)
{
platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
unsigned int id;
id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
if (id == 0x50000)
s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
else
s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
platform_device_register(&s5p64x0_device_pdma);
return 0;
}
arch_initcall(s5p6440_dma_init);
arch_initcall(s5p64x0_dma_init);

104
arch/arm/mach-s5p6440/gpio.c → arch/arm/mach-s5p64x0/gpio.c
View file

@ -1,14 +1,14 @@
/* arch/arm/mach-s5p6440/gpio.c
/* linux/arch/arm/mach-s5p64x0/gpio.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - GPIOlib support
* S5P64X0 - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#include <linux/kernel.h>
#include <linux/irq.h>
@ -22,26 +22,29 @@
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
/* GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 6 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* F 2 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* N 16 2Bit No IRQ_EINT
* P 8 2Bit Yes 8
* R 15 4Bit[2] Yes 8
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
/* To be implemented S5P6450 GPIO */
static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
/*
* S5P6440 GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 6 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* F 2 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* N 16 2Bit No IRQ_EINT
* P 8 2Bit Yes 8
* R 15 4Bit[2] Yes 8
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
unsigned int offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
return 0;
}
static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@ -124,12 +127,11 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
return 0;
}
int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift;
unsigned long flags;
u32 con;
switch (off) {
@ -155,26 +157,22 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
cfg <<= shift;
}
s3c_gpio_lock(chip, flags);
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
s3c_gpio_unlock(chip, flags);
return 0;
}
static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
{
.cfg_eint = 0,
}, {
.cfg_eint = 7,
}, {
.cfg_eint = 3,
.set_config = s5p6440_gpio_setcfg_4bit_rbank,
.set_config = s5p64x0_gpio_setcfg_4bit_rbank,
}, {
.cfg_eint = 0,
.set_config = s3c_gpio_setcfg_s3c24xx,
@ -193,7 +191,7 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
{
.base = S5P6440_GPA_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPA(0),
.ngpio = S5P6440_GPIO_A_NR,
@ -201,7 +199,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
},
}, {
.base = S5P6440_GPB_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPB(0),
.ngpio = S5P6440_GPIO_B_NR,
@ -209,7 +207,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
},
}, {
.base = S5P6440_GPC_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPC(0),
.ngpio = S5P6440_GPIO_C_NR,
@ -217,7 +215,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
},
}, {
.base = S5P6440_GPG_BASE,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPG(0),
.ngpio = S5P6440_GPIO_G_NR,
@ -229,7 +227,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
{
.base = S5P6440_GPH_BASE + 0x4,
.config = &s5p6440_gpio_cfgs[1],
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPH(0),
.ngpio = S5P6440_GPIO_H_NR,
@ -238,10 +236,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
},
};
static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
{
.base = S5P6440_GPR_BASE + 0x4,
.config = &s5p6440_gpio_cfgs[2],
.config = &s5p64x0_gpio_cfgs[2],
.chip = {
.base = S5P6440_GPR(0),
.ngpio = S5P6440_GPIO_R_NR,
@ -253,7 +251,7 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
{
.base = S5P6440_GPF_BASE,
.config = &s5p6440_gpio_cfgs[5],
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6440_GPF(0),
.ngpio = S5P6440_GPIO_F_NR,
@ -261,7 +259,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
},
}, {
.base = S5P6440_GPI_BASE,
.config = &s5p6440_gpio_cfgs[3],
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6440_GPI(0),
.ngpio = S5P6440_GPIO_I_NR,
@ -269,7 +267,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
},
}, {
.base = S5P6440_GPJ_BASE,
.config = &s5p6440_gpio_cfgs[3],
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6440_GPJ(0),
.ngpio = S5P6440_GPIO_J_NR,
@ -277,7 +275,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
},
}, {
.base = S5P6440_GPN_BASE,
.config = &s5p6440_gpio_cfgs[4],
.config = &s5p64x0_gpio_cfgs[4],
.chip = {
.base = S5P6440_GPN(0),
.ngpio = S5P6440_GPIO_N_NR,
@ -285,7 +283,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
},
}, {
.base = S5P6440_GPP_BASE,
.config = &s5p6440_gpio_cfgs[5],
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6440_GPP(0),
.ngpio = S5P6440_GPIO_P_NR,
@ -294,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
},
};
void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chipcfg++) {
if (!chipcfg->set_config)
@ -308,13 +306,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
}
}
static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chip++) {
chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
chip->chip.direction_output =
s5p6440_gpiolib_rbank_4bit2_output;
s5p64x0_gpiolib_rbank_4bit2_output;
s3c_gpiolib_add(chip);
}
}
@ -324,8 +322,8 @@ static int __init s5p6440_gpiolib_init(void)
struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
ARRAY_SIZE(s5p6440_gpio_cfgs));
s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
ARRAY_SIZE(s5p64x0_gpio_cfgs));
for (; nr_chips > 0; nr_chips--, chips++)
s3c_gpiolib_add(chips);
@ -336,8 +334,8 @@ static int __init s5p6440_gpiolib_init(void)
samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
ARRAY_SIZE(s5p6440_gpio_4bit2));
s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
ARRAY_SIZE(gpio_rbank_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
return 0;
}

33
arch/arm/mach-s5p64x0/include/mach/debug-macro.S Normal file
View file

@ -0,0 +1,33 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#include <plat/regs-serial.h>
.macro addruart, rp, rv
mov \rp, #0xE0000000
orr \rp, \rp, #0x00100000
ldr \rp, [\rp, #0x118 ]
and \rp, \rp, #0xff000
teq \rp, #0x50000 @@ S5P6450
ldreq \rp, =0xEC800000
movne \rp, #0xEC000000 @@ S5P6440
ldrne \rv, = S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
#include <plat/debug-macro.S>

0
arch/arm/mach-s5p6440/include/mach/dma.h → arch/arm/mach-s5p64x0/include/mach/dma.h
View file

8
arch/arm/mach-s5p6440/include/mach/entry-macro.S → arch/arm/mach-s5p64x0/include/mach/entry-macro.S
View file

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S
/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Low-level IRQ helper macros for the Samsung S5P6440
* Low-level IRQ helper macros for the Samsung S5P64X0
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

139
arch/arm/mach-s5p64x0/include/mach/gpio.h Normal file
View file

@ -0,0 +1,139 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S5P6440_GPIO_A_NR (6)
#define S5P6440_GPIO_B_NR (7)
#define S5P6440_GPIO_C_NR (8)
#define S5P6440_GPIO_F_NR (2)
#define S5P6440_GPIO_G_NR (7)
#define S5P6440_GPIO_H_NR (10)
#define S5P6440_GPIO_I_NR (16)
#define S5P6440_GPIO_J_NR (12)
#define S5P6440_GPIO_N_NR (16)
#define S5P6440_GPIO_P_NR (8)
#define S5P6440_GPIO_R_NR (15)
#define S5P6450_GPIO_A_NR (6)
#define S5P6450_GPIO_B_NR (7)
#define S5P6450_GPIO_C_NR (8)
#define S5P6450_GPIO_D_NR (8)
#define S5P6450_GPIO_F_NR (2)
#define S5P6450_GPIO_G_NR (14)
#define S5P6450_GPIO_H_NR (10)
#define S5P6450_GPIO_I_NR (16)
#define S5P6450_GPIO_J_NR (12)
#define S5P6450_GPIO_K_NR (5)
#define S5P6450_GPIO_N_NR (16)
#define S5P6450_GPIO_P_NR (11)
#define S5P6450_GPIO_Q_NR (14)
#define S5P6450_GPIO_R_NR (15)
#define S5P6450_GPIO_S_NR (8)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5P64X0_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p6440_gpio_number {
S5P6440_GPIO_A_START = 0,
S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
};
enum s5p6450_gpio_number {
S5P6450_GPIO_A_START = 0,
S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
};
/* GPIO number definitions */
#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
/* the end of the S5P64X0 specific gpios */
#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
S5P6440_GPIO_END : S5P6450_GPIO_END)
#define S3C_GPIO_END S5P64X0_GPIO_END
/* define the number of gpios we need to the one after the last GPIO range */
#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */

8
arch/arm/mach-s5p6440/include/mach/hardware.h → arch/arm/mach-s5p64x0/include/mach/hardware.h
View file

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h
/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - Hardware support
* S5P64X0 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

17
arch/arm/mach-s5p64x0/include/mach/i2c.h Normal file
View file

@ -0,0 +1,17 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 I2C configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);

25
arch/arm/mach-s5p64x0/include/mach/io.h Normal file
View file

@ -0,0 +1,25 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for S5P64X0 based
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif

48
arch/arm/mach-s5p6440/include/mach/irqs.h → arch/arm/mach-s5p64x0/include/mach/irqs.h
View file

@ -1,17 +1,17 @@
/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h
/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
*
* Copyright 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - IRQ definitions
* S5P64X0 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_S5P_IRQS_H
#define __ASM_ARCH_S5P_IRQS_H __FILE__
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
@ -20,10 +20,12 @@
#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
#define IRQ_IIC1 S5P_IRQ_VIC0(5)
#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
#define IRQ_GPS S5P_IRQ_VIC0(7)
#define IRQ_POST0 S5P_IRQ_VIC0(9)
#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
#define IRQ_2D S5P_IRQ_VIC0(11)
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
@ -39,22 +41,26 @@
#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
#define IRQ_PCM0 S5P_IRQ_VIC1(2)
#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
#define IRQ_UART0 S5P_IRQ_VIC1(5)
#define IRQ_UART1 S5P_IRQ_VIC1(6)
#define IRQ_UART2 S5P_IRQ_VIC1(7)
#define IRQ_UART3 S5P_IRQ_VIC1(8)
#define IRQ_DMA0 S5P_IRQ_VIC1(9)
#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
#define IRQ_NFC S5P_IRQ_VIC1(13)
#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
#define IRQ_SPI0 S5P_IRQ_VIC1(16)
#define IRQ_SPI1 S5P_IRQ_VIC1(17)
#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
#define IRQ_IIC S5P_IRQ_VIC1(18)
#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
#define IRQ_PMU S5P_IRQ_VIC1(23)
#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
#define IRQ_OTG S5P_IRQ_VIC1(26)
#define IRQ_DSI S5P_IRQ_VIC1(27)
#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
@ -63,6 +69,24 @@
#define IRQ_TC IRQ_PENDN
#define IRQ_ADC S5P_IRQ_VIC1(31)
/* UART interrupts, S5P6450 has 5 UARTs */
#define IRQ_S5P_UART_BASE4 (96)
#define IRQ_S5P_UART_BASE5 (100)
#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
/* S3C compatibilty defines */
#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
/* S5P6450 EINT feature will be added */
/*
* Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
* them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
@ -115,4 +139,4 @@
#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
#endif /* __ASM_ARCH_S5P_IRQS_H */
#endif /* __ASM_ARCH_IRQS_H */

83
arch/arm/mach-s5p64x0/include/mach/map.h Normal file
View file

@ -0,0 +1,83 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P64X0_PA_SDRAM (0x20000000)
#define S5P64X0_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
#define S5P64X0_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
#define S5P64X0_PA_GPIO (0xE0308000)
#define S5P64X0_PA_VIC0 (0xE4000000)
#define S5P64X0_PA_VIC1 (0xE4100000)
#define S5P64X0_PA_PDMA (0xE9000000)
#define S5P64X0_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5P64X0_PA_TIMER
#define S5P64X0_PA_RTC (0xEA100000)
#define S5P64X0_PA_WDT (0xEA200000)
#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
#define S5P_PA_UART0 S5P6450_PA_UART(0)
#define S5P_PA_UART1 S5P6450_PA_UART(1)
#define S5P_PA_UART2 S5P6450_PA_UART(2)
#define S5P_PA_UART3 S5P6450_PA_UART(3)
#define S5P_PA_UART4 S5P6450_PA_UART(4)
#define S5P_PA_UART5 S5P6450_PA_UART(5)
#define S5P_SZ_UART SZ_256
#define S5P6440_PA_IIC0 (0xEC104000)
#define S5P6440_PA_IIC1 (0xEC20F000)
#define S5P6450_PA_IIC0 (0xEC100000)
#define S5P6450_PA_IIC1 (0xEC200000)
#define S5P64X0_PA_SPI0 (0xEC400000)
#define S5P64X0_PA_SPI1 (0xEC500000)
#define S5P64X0_PA_HSOTG (0xED100000)
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_I2S (0xF2000000)
#define S5P64X0_PA_PCM (0xF2100000)
#define S5P64X0_PA_ADC (0xF3000000)
/* compatibiltiy defines. */
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
#endif /* __ASM_ARCH_MAP_H */

12
arch/arm/mach-s5p6440/include/mach/memory.h → arch/arm/mach-s5p64x0/include/mach/memory.h
View file

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5p6440/include/mach/memory.h
/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - Memory definitions
* S5P64X0 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -11,9 +11,9 @@
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H __FILE__
#define PHYS_OFFSET UL(0x20000000)
#define PHYS_OFFSET UL(0x20000000)
#define CONSISTENT_DMA_SIZE SZ_8M
#endif /* __ASM_ARCH_MEMORY_H */

10
arch/arm/mach-s5p6440/include/mach/pwm-clock.h → arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
View file

@ -1,16 +1,14 @@
/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5P6440 - pwm clock and timer support
* S5P64X0 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

63
arch/arm/mach-s5p64x0/include/mach/regs-clock.h Normal file
View file

@ -0,0 +1,63 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
#define S5P64X0_OTHERS S5P_CLKREG(0x900)
#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
/* Compatibility defines */
#define ARM_CLK_DIV S5P64X0_CLK_DIV0
#define ARM_DIV_RATIO_SHIFT 0
#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
#endif /* __ASM_ARCH_REGS_CLOCK_H */

28
arch/arm/mach-s5p6440/include/mach/regs-gpio.h → arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
View file

@ -1,21 +1,24 @@
/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - GPIO register definitions
* S5P64X0 - GPIO register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H __FILE__
#include <mach/map.h>
/* Will be implemented S5P6442 GPIOlib */
/* Base addresses for each of the banks */
#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000)
#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020)
#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040)
@ -27,6 +30,7 @@
#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830)
#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160)
#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290)
#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900)
#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910)
#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914)
@ -34,19 +38,23 @@
#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
/* for LCD */
#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
/* These set of macros are not really useful for the
* GPF/GPI/GPJ/GPN/GPP,
* useful for others set of GPIO's (4 bit)
/*
* These set of macros are not really useful for the
* GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
*/
#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
* */
/*
* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
*/
#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))

8
arch/arm/mach-s5p6440/include/mach/regs-irq.h → arch/arm/mach-s5p64x0/include/mach/regs-irq.h
View file

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h
/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - IRQ register definitions
* S5P64X0 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

46
arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h Normal file
View file

@ -0,0 +1,46 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for s5p64x0 clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#include <linux/clk.h>
extern struct clksrc_clk clk_mout_apll;
extern struct clksrc_clk clk_mout_mpll;
extern struct clksrc_clk clk_mout_epll;
extern int s5p64x0_epll_enable(struct clk *clk, int enable);
extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
extern struct clk_ops s5p64x0_clkarm_ops;
extern struct clksrc_clk clk_armclk;
extern struct clksrc_clk clk_dout_mpll;
extern struct clk *clkset_hclk_low_list[];
extern struct clksrc_sources clkset_hclk_low;
extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */

20
arch/arm/mach-s5p64x0/include/mach/spi-clocks.h Normal file
View file

@ -0,0 +1,20 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SPI_CLKS_H
#define __ASM_ARCH_SPI_CLKS_H __FILE__
#define S5P64X0_SPI_SRCCLK_PCLK 0
#define S5P64X0_SPI_SRCCLK_SCLK 1
#endif /* __ASM_ARCH_SPI_CLKS_H */

8
arch/arm/mach-s5p6440/include/mach/system.h → arch/arm/mach-s5p64x0/include/mach/system.h
View file

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5p6440/include/mach/system.h
/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - system support header
* S5P64X0 - system support header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

13
arch/arm/mach-s5p6440/include/mach/tick.h → arch/arm/mach-s5p64x0/include/mach/tick.h
View file

@ -1,9 +1,14 @@
/* linux/arch/arm/mach-s5p6440/include/mach/tick.h
/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6440 - Timer tick support definitions
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S5P64X0 - Timer tick support definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

7
arch/arm/mach-s5p6440/include/mach/timex.h → arch/arm/mach-s5p64x0/include/mach/timex.h
View file

@ -1,9 +1,12 @@
/* arch/arm/mach-s3c64xx/include/mach/timex.h
/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C6400 - time parameters
* S5P64X0 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

212
arch/arm/mach-s5p64x0/include/mach/uncompress.h Normal file
View file

@ -0,0 +1,212 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
/*
* cannot use commonly <plat/uncompress.h>
* because uart base of S5P6440 and S5P6450 is different
*/
typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
/* uart setup */
static unsigned int fifo_mask;
static unsigned int fifo_max;
/* forward declerations */
static void arch_detect_cpu(void);
/* defines for UART registers */
#include <plat/regs-serial.h>
#include <plat/regs-watchdog.h>
/* working in physical space... */
#undef S3C2410_WDOGREG
#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
static unsigned long uart_base;
static __inline__ void get_uart_base(void)
{
unsigned int chipid;
chipid = *(const volatile unsigned int __force *) 0xE0100118;
uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
if ((chipid & 0xff000) == 0x50000)
uart_base += 0xEC800000;
else
uart_base += 0xEC000000;
}
static __inline__ void uart_wr(unsigned int reg, unsigned int val)
{
volatile unsigned int *ptr;
get_uart_base();
ptr = (volatile unsigned int *)(reg + uart_base);
*ptr = val;
}
static __inline__ unsigned int uart_rd(unsigned int reg)
{
volatile unsigned int *ptr;
get_uart_base();
ptr = (volatile unsigned int *)(reg + uart_base);
return *ptr;
}
/*
* we can deal with the case the UARTs are being run
* in FIFO mode, so that we don't hold up our execution
* waiting for tx to happen...
*/
static void putc(int ch)
{
if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
int level;
while (1) {
level = uart_rd(S3C2410_UFSTAT);
level &= fifo_mask;
if (level < fifo_max)
break;
}
} else {
/* not using fifos */
while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
barrier();
}
/* write byte to transmission register */
uart_wr(S3C2410_UTXH, ch);
}
static inline void flush(void)
{
}
#define __raw_writel(d, ad) \
do { \
*((volatile unsigned int __force *)(ad)) = (d); \
} while (0)
/*
* CONFIG_S3C_BOOT_WATCHDOG
*
* Simple boot-time watchdog setup, to reboot the system if there is
* any problem with the boot process
*/
#ifdef CONFIG_S3C_BOOT_WATCHDOG
#define WDOG_COUNT (0xff00)
static inline void arch_decomp_wdog(void)
{
__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
}
static void arch_decomp_wdog_start(void)
{
__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
}
#else
#define arch_decomp_wdog_start()
#define arch_decomp_wdog()
#endif
#ifdef CONFIG_S3C_BOOT_ERROR_RESET
static void arch_decomp_error(const char *x)
{
putstr("\n\n");
putstr(x);
putstr("\n\n -- System resetting\n");
__raw_writel(0x4000, S3C2410_WTDAT);
__raw_writel(0x4000, S3C2410_WTCNT);
__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
while(1);
}
#define arch_error arch_decomp_error
#endif
#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
static inline void arch_enable_uart_fifo(void)
{
u32 fifocon = uart_rd(S3C2410_UFCON);
if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
fifocon |= S3C2410_UFCON_RESETBOTH;
uart_wr(S3C2410_UFCON, fifocon);
/* wait for fifo reset to complete */
while (1) {
fifocon = uart_rd(S3C2410_UFCON);
if (!(fifocon & S3C2410_UFCON_RESETBOTH))
break;
}
}
}
#else
#define arch_enable_uart_fifo() do { } while(0)
#endif
static void arch_decomp_setup(void)
{
/*
* we may need to setup the uart(s) here if we are not running
* on an BAST... the BAST will have left the uarts configured
* after calling linux.
*/
arch_detect_cpu();
arch_decomp_wdog_start();
/*
* Enable the UART FIFOs if they where not enabled and our
* configuration says we should turn them on.
*/
arch_enable_uart_fifo();
}
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */

5
arch/arm/mach-s5p6440/include/mach/vmalloc.h → arch/arm/mach-s5p64x0/include/mach/vmalloc.h
View file

@ -1,4 +1,7 @@
/* arch/arm/mach-s5p6440/include/mach/vmalloc.h
/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2010 Ben Dooks <ben-linux@fluff.org>
*

73
arch/arm/mach-s5p64x0/init.c Normal file
View file

@ -0,0 +1,73 @@
/* linux/arch/arm/mach-s5p64x0/init.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Init support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s5p6440.h>
#include <plat/s5p6450.h>
#include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
[0] = {
.name = "pclk_low",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
[1] = {
.name = "uclk1",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
};
/* uart registration process */
void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->clocks = s5p64x0_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
}
}
}
void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
int uart;
for (uart = 0; uart < no; uart++) {
s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
}
s5p64x0_common_init_uarts(cfg, no);
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}
void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s5p64x0_common_init_uarts(cfg, no);
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}

89
arch/arm/mach-s5p6440/mach-smdk6440.c → arch/arm/mach-s5p64x0/mach-smdk6440.c
View file

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c
/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -21,21 +21,22 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/i2c.h>
#include <plat/regs-serial.h>
#include <plat/gpio-cfg.h>
#include <plat/s5p6440.h>
#include <plat/clock.h>
#include <mach/regs-clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
@ -58,43 +59,60 @@
static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
.hwport = 0,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
.hwport = 1,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
.hwport = 2,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
.hwport = 3,
.flags = 0,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
};
static struct platform_device *smdk6440_devices[] __initdata = {
&s5p6440_device_iis,
&s3c_device_adc,
&s3c_device_rtc,
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_ts,
&s3c_device_wdt,
&s5p6440_device_iis,
};
static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
.flags = 0,
.slave_addr = 0x10,
.frequency = 100*1000,
.sda_delay = 100,
.cfg_gpio = s5p6440_i2c0_cfg_gpio,
};
static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
.flags = 0,
.bus_num = 1,
.slave_addr = 0x10,
.frequency = 100*1000,
.sda_delay = 100,
.cfg_gpio = s5p6440_i2c1_cfg_gpio,
};
static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
@ -113,7 +131,7 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
static void __init smdk6440_map_io(void)
{
s5p_init_io(NULL, 0, S5P_SYS_ID);
s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
}
@ -122,9 +140,8 @@ static void __init smdk6440_machine_init(void)
{
s3c24xx_ts_set_platdata(&s3c_ts_platform);
/* I2C */
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
i2c_register_board_info(0, smdk6440_i2c_devs0,
ARRAY_SIZE(smdk6440_i2c_devs0));
i2c_register_board_info(1, smdk6440_i2c_devs1,
@ -135,9 +152,9 @@ static void __init smdk6440_machine_init(void)
MACHINE_START(SMDK6440, "SMDK6440")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.phys_io = S3C_PA_UART & 0xfff00000,
.phys_io = S5P6440_PA_UART(0) & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S5P_PA_SDRAM + 0x100,
.boot_params = S5P64X0_PA_SDRAM + 0x100,
.init_irq = s5p6440_init_irq,
.map_io = smdk6440_map_io,

182
arch/arm/mach-s5p64x0/mach-smdk6450.c Normal file
View file

@ -0,0 +1,182 @@
/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/i2c.h>
#include <plat/regs-serial.h>
#include <plat/gpio-cfg.h>
#include <plat/s5p6450.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
#include <plat/pll.h>
#include <plat/adc.h>
#include <plat/ts.h>
#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define SMDK6450_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDK6450_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S3C2440_UFCON_TXTRIG16 | \
S3C2410_UFCON_RXTRIG8)
static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = SMDK6450_UCON_DEFAULT,
.ulcon = SMDK6450_ULCON_DEFAULT,
.ufcon = SMDK6450_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = SMDK6450_UCON_DEFAULT,
.ulcon = SMDK6450_ULCON_DEFAULT,
.ufcon = SMDK6450_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = SMDK6450_UCON_DEFAULT,
.ulcon = SMDK6450_ULCON_DEFAULT,
.ufcon = SMDK6450_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = SMDK6450_UCON_DEFAULT,
.ulcon = SMDK6450_ULCON_DEFAULT,
.ufcon = SMDK6450_UFCON_DEFAULT,
},
#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
[4] = {
.hwport = 4,
.flags = 0,
.ucon = SMDK6450_UCON_DEFAULT,
.ulcon = SMDK6450_ULCON_DEFAULT,
.ufcon = SMDK6450_UFCON_DEFAULT,
},
#endif
#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
[5] = {
.hwport = 5,
.flags = 0,
.ucon = SMDK6450_UCON_DEFAULT,
.ulcon = SMDK6450_ULCON_DEFAULT,
.ufcon = SMDK6450_UFCON_DEFAULT,
},
#endif
};
static struct platform_device *smdk6450_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_rtc,
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_ts,
&s3c_device_wdt,
&s5p6450_device_iis0,
/* s5p6450_device_spi0 will be added */
};
static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
.flags = 0,
.slave_addr = 0x10,
.frequency = 100*1000,
.sda_delay = 100,
.cfg_gpio = s5p6450_i2c0_cfg_gpio,
};
static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
.flags = 0,
.bus_num = 1,
.slave_addr = 0x10,
.frequency = 100*1000,
.sda_delay = 100,
.cfg_gpio = s5p6450_i2c1_cfg_gpio,
};
static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */
};
static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
};
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.delay = 10000,
.presc = 49,
.oversampling_shift = 2,
};
static void __init smdk6450_map_io(void)
{
s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
s3c24xx_init_clocks(19200000);
s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
}
static void __init smdk6450_machine_init(void)
{
s3c24xx_ts_set_platdata(&s3c_ts_platform);
s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
i2c_register_board_info(0, smdk6450_i2c_devs0,
ARRAY_SIZE(smdk6450_i2c_devs0));
i2c_register_board_info(1, smdk6450_i2c_devs1,
ARRAY_SIZE(smdk6450_i2c_devs1));
platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
}
MACHINE_START(SMDK6450, "SMDK6450")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.phys_io = S5P6450_PA_UART(0) & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S5P64X0_PA_SDRAM + 0x100,
.init_irq = s5p6450_init_irq,
.map_io = smdk6450_map_io,
.init_machine = smdk6450_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END

24
arch/arm/mach-s5p6440/setup-i2c0.c → arch/arm/mach-s5p64x0/setup-i2c0.c
View file

@ -1,11 +1,11 @@
/* linux/arch/arm/mach-s5p6440/setup-i2c0.c
/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
* Based on plat-s3c64x0/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -14,17 +14,29 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
#include <mach/i2c.h>
void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
}
void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
}
void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }

20
arch/arm/mach-s5p6440/setup-i2c1.c → arch/arm/mach-s5p64x0/setup-i2c1.c
View file

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5p6440/setup-i2c1.c
/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* I2C1 GPIO configuration.
*
@ -21,10 +21,22 @@ struct platform_device; /* don't need the contents */
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
#include <mach/i2c.h>
void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
}
void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
}
void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }

28
arch/arm/mach-s5pc100/cpu.c
View file

@ -1,4 +1,7 @@
/* linux/arch/arm/mach-s5pc100/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
@ -21,6 +24,7 @@
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -56,10 +60,30 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5P_PA_VIC2),
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5PC100_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5PC100_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5PC100_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5PC100_PA_VIC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC100_VA_OTHERS,
.pfn = __phys_to_pfn(S5PC100_PA_OTHERS),

11
arch/arm/mach-s5pc100/include/mach/map.h
View file

@ -44,19 +44,16 @@
#define S5PC100_PA_OTHERS (0xE0200000)
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
#define S5P_PA_GPIO (0xE0300000)
#define S5PC100_PA_GPIO (0xE0300000)
#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
/* Interrupt */
#define S5PC100_PA_VIC (0xE4000000)
#define S5PC100_PA_VIC0 (0xE4000000)
#define S5PC100_PA_VIC1 (0xE4100000)
#define S5PC100_PA_VIC2 (0xE4200000)
#define S5PC100_VA_VIC S3C_VA_IRQ
#define S5PC100_PA_VIC_OFFSET 0x100000
#define S5PC100_VA_VIC_OFFSET 0x10000
#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0)
#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1)
#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2)
#define S5PC100_PA_ONENAND (0xE7100000)

9
arch/arm/mach-s5pv210/Kconfig
View file

@ -53,11 +53,6 @@ config S5PV210_SETUP_SDHCI_GPIO
help
Common setup code for SDHCI gpio.
config S5PC110_DEV_ONENAND
bool
help
Compile in platform device definition for OneNAND1 controller
menu "S5PC110 Machines"
config MACH_AQUILA
@ -71,7 +66,7 @@ config MACH_AQUILA
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S5PC110_DEV_ONENAND
select S5P_DEV_ONENAND
select S5PV210_SETUP_FB_24BPP
select S5PV210_SETUP_SDHCI
help
@ -88,7 +83,7 @@ config MACH_GONI
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S5PC110_DEV_ONENAND
select S5P_DEV_ONENAND
select S5PV210_SETUP_FB_24BPP
select S5PV210_SETUP_SDHCI
help

1
arch/arm/mach-s5pv210/Makefile
View file

@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_GONI) += mach-goni.o
obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o

5
arch/arm/mach-s5pv210/clock.c
View file

@ -173,11 +173,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
}
static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
}
static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);

23
arch/arm/mach-s5pv210/cpu.c
View file

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv210/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -49,6 +50,21 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5PV210_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5PV210_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5PV210_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5PV210_PA_VIC2),
@ -59,6 +75,11 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5PV210_PA_VIC3),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(S5PV210_PA_SROMC),

11
arch/arm/mach-s5pv210/include/mach/map.h
View file

@ -17,7 +17,10 @@
#include <plat/map-s5p.h>
#define S5PC110_PA_ONENAND (0xB0000000)
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5PC110_PA_ONENAND_DMA (0xB0600000)
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5PV210_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
@ -26,7 +29,6 @@
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
#define S5PV210_PA_GPIO (0xE0200000)
#define S5P_PA_GPIO S5PV210_PA_GPIO
/* SPI */
#define S5PV210_PA_SPI0 0xE1300000
@ -72,16 +74,9 @@
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_VIC0 (0xF2000000)
#define S5P_PA_VIC0 S5PV210_PA_VIC0
#define S5PV210_PA_VIC1 (0xF2100000)
#define S5P_PA_VIC1 S5PV210_PA_VIC1
#define S5PV210_PA_VIC2 (0xF2200000)
#define S5P_PA_VIC2 S5PV210_PA_VIC2
#define S5PV210_PA_VIC3 (0xF2300000)
#define S5P_PA_VIC3 S5PV210_PA_VIC3
#define S5PV210_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PV210_PA_SDRAM

2
arch/arm/mach-s5pv210/mach-aquila.c
View file

@ -477,7 +477,7 @@ static struct platform_device *aquila_devices[] __initdata = {
&aquila_i2c_gpio_pmic,
&aquila_device_gpiokeys,
&s3c_device_fb,
&s5pc110_device_onenand,
&s5p_device_onenand,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,

2
arch/arm/mach-s5pv210/mach-goni.c
View file

@ -456,7 +456,7 @@ static void goni_setup_sdhci(void)
static struct platform_device *goni_devices[] __initdata = {
&s3c_device_fb,
&s5pc110_device_onenand,
&s5p_device_onenand,
&goni_i2c_gpio_pmic,
&goni_device_gpiokeys,
&s5p_device_fimc0,

40
arch/arm/mach-s5pv310/cpu.c
View file

@ -31,21 +31,6 @@ extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
/* Initial IO mappings */
static struct map_desc s5pv310_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
.length = SZ_4K,
@ -55,6 +40,31 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
},
};

2
arch/arm/mach-s5pv310/include/mach/irqs.h
View file

@ -68,6 +68,8 @@
#define IRQ_IIC COMBINER_IRQ(27, 0)
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
/* Set the default NR_IRQS */
#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)

7
arch/arm/mach-s5pv310/include/mach/map.h
View file

@ -25,6 +25,12 @@
#define S5PV310_PA_SYSRAM (0x02025000)
#define S5PC210_PA_ONENAND (0x0C000000)
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5PC210_PA_ONENAND_DMA (0x0C600000)
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
#define S5PV310_PA_CHIPID (0x10000000)
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
@ -46,7 +52,6 @@
#define S5PV310_PA_GPIO1 (0x11400000)
#define S5PV310_PA_GPIO2 (0x11000000)
#define S5PV310_PA_GPIO3 (0x03860000)
#define S5P_PA_GPIO S5PV310_PA_GPIO1
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))

4
arch/arm/mach-vexpress/ct-ca9x4.c
View file

@ -68,7 +68,7 @@ static void __init ct_ca9x4_init_irq(void)
}
#if 0
static void ct_ca9x4_timer_init(void)
static void __init ct_ca9x4_timer_init(void)
{
writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
@ -222,7 +222,7 @@ static struct platform_device pmu_device = {
.resource = pmu_resources,
};
static void ct_ca9x4_init(void)
static void __init ct_ca9x4_init(void)
{
int i;

2
arch/arm/mach-vexpress/v2m.c
View file

@ -48,7 +48,7 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
}
static void v2m_timer_init(void)
static void __init v2m_timer_init(void)
{
writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);

8
arch/arm/mm/ioremap.c
View file

@ -204,8 +204,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
/*
* Don't allow RAM to be mapped - this causes problems with ARMv6+
*/
if (WARN_ON(pfn_valid(pfn)))
return NULL;
if (pfn_valid(pfn)) {
printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory. This leads\n"
KERN_WARNING "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n"
KERN_WARNING "will fail in the next kernel release. Please fix your driver.\n");
WARN_ON(1);
}
type = get_mem_type(mtype);
if (!type)

4
arch/arm/mm/mmu.c
View file

@ -248,7 +248,7 @@ static struct mem_type mem_types[] = {
},
[MT_MEMORY] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_USER | L_PTE_EXEC,
L_PTE_WRITE | L_PTE_EXEC,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
.domain = DOMAIN_KERNEL,
@ -259,7 +259,7 @@ static struct mem_type mem_types[] = {
},
[MT_MEMORY_NONCACHED] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
.domain = DOMAIN_KERNEL,

10
arch/arm/mm/proc-v7.S
View file

@ -253,6 +253,14 @@ __v7_setup:
orreq r10, r10, #1 << 22 @ set bit #22
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r6, #0x20 @ present in r2p0
teqne r6, #0x21 @ present in r2p1
teqne r6, #0x22 @ present in r2p2
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
orreq r10, r10, #1 << 6 @ set bit #6
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
3: mov r10, #0
#ifdef HARVARD_CACHE
@ -365,7 +373,7 @@ __v7_ca9mp_proc_info:
b __v7_ca9mp_setup
.long cpu_arch_name
.long cpu_elf_name
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
.long cpu_v7_name
.long v7_processor_functions
.long v7wbi_tlb_fns

1
arch/arm/plat-omap/iommu.c
View file

@ -320,6 +320,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
if ((start <= da) && (da < start + bytes)) {
dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
__func__, start, da, bytes);
iotlb_load_cr(obj, &cr);
iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
}
}

9
arch/arm/plat-s5p/Kconfig
View file

@ -7,7 +7,7 @@
config PLAT_S5P
bool
depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
default y
select ARM_VIC if !ARCH_S5PV310
select ARM_GIC if ARCH_S5PV310
@ -30,7 +30,7 @@ config S5P_EXT_INT
bool
help
Use the external interrupts (other than GPIO interrupts.)
Note: Do not choose this for S5P6440.
Note: Do not choose this for S5P6440 and S5P6450.
config S5P_DEV_FIMC0
bool
@ -46,3 +46,8 @@ config S5P_DEV_FIMC2
bool
help
Compile in platform device definitions for FIMC controller 2
config S5P_DEV_ONENAND
bool
help
Compile in platform device definition for OneNAND controller

1
arch/arm/plat-s5p/Makefile
View file

@ -24,3 +24,4 @@ obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o

19
arch/arm/plat-s5p/clock.c
View file

@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
.ctrlbit = (1 << 31),
};
/* DPLL clock output */
struct clk clk_fout_dpll = {
.name = "fout_dpll",
.id = -1,
.ctrlbit = (1 << 31),
};
/* VPLL clock output */
struct clk clk_fout_vpll = {
.name = "fout_vpll",
@ -122,6 +129,17 @@ struct clksrc_sources clk_src_epll = {
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
/* Possible clock sources for DPLL Mux */
static struct clk *clk_src_dpll_list[] = {
[0] = &clk_fin_dpll,
[1] = &clk_fout_dpll,
};
struct clksrc_sources clk_src_dpll = {
.sources = clk_src_dpll_list,
.nr_sources = ARRAY_SIZE(clk_src_dpll_list),
};
struct clk clk_vpll = {
.name = "vpll",
.id = -1,
@ -145,6 +163,7 @@ static struct clk *s5p_clks[] __initdata = {
&clk_fout_apll,
&clk_fout_mpll,
&clk_fout_epll,
&clk_fout_dpll,
&clk_fout_vpll,
&clk_arm,
&clk_vpll,

34
arch/arm/plat-s5p/cpu.c
View file

@ -19,6 +19,7 @@
#include <plat/cpu.h>
#include <plat/s5p6440.h>
#include <plat/s5p6442.h>
#include <plat/s5p6450.h>
#include <plat/s5pc100.h>
#include <plat/s5pv210.h>
#include <plat/s5pv310.h>
@ -27,6 +28,7 @@
static const char name_s5p6440[] = "S5P6440";
static const char name_s5p6442[] = "S5P6442";
static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
static const char name_s5pv310[] = "S5PV310";
@ -38,7 +40,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.map_io = s5p6440_map_io,
.init_clocks = s5p6440_init_clocks,
.init_uarts = s5p6440_init_uarts,
.init = s5p6440_init,
.init = s5p64x0_init,
.name = name_s5p6440,
}, {
.idcode = 0x36442000,
@ -48,6 +50,14 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = s5p6442_init_uarts,
.init = s5p6442_init,
.name = name_s5p6442,
}, {
.idcode = 0x36450000,
.idmask = 0xffffff00,
.map_io = s5p6450_map_io,
.init_clocks = s5p6450_init_clocks,
.init_uarts = s5p6450_init_uarts,
.init = s5p64x0_init,
.name = name_s5p6450,
}, {
.idcode = 0x43100000,
.idmask = 0xfffff000,
@ -88,33 +98,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5P_PA_SYSCON),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
#ifdef CONFIG_ARM_VIC
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5P_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5P_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
#endif
}, {
.virtual = (unsigned long)S3C_VA_TIMER,
.pfn = __phys_to_pfn(S5P_PA_TIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5P_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_WATCHDOG,
.pfn = __phys_to_pfn(S3C_PA_WDT),

28
arch/arm/mach-s5pv210/dev-onenand.c → arch/arm/plat-s5p/dev-onenand.c
View file

@ -1,10 +1,12 @@
/*
* linux/arch/arm/mach-s5pv210/dev-onenand.c
/* linux/arch/arm/plat-s5p/dev-onenand.c
*
* Copyright 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2008-2010 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* S5PC110 series device definition for OneNAND devices
* S5P series device definition for OneNAND devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -19,15 +21,15 @@
#include <mach/irqs.h>
#include <mach/map.h>
static struct resource s5pc110_onenand_resources[] = {
static struct resource s5p_onenand_resources[] = {
[0] = {
.start = S5PC110_PA_ONENAND,
.end = S5PC110_PA_ONENAND + SZ_128K - 1,
.start = S5P_PA_ONENAND,
.end = S5P_PA_ONENAND + SZ_128K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = S5PC110_PA_ONENAND_DMA,
.end = S5PC110_PA_ONENAND_DMA + SZ_8K - 1,
.start = S5P_PA_ONENAND_DMA,
.end = S5P_PA_ONENAND_DMA + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
@ -37,19 +39,19 @@ static struct resource s5pc110_onenand_resources[] = {
},
};
struct platform_device s5pc110_device_onenand = {
struct platform_device s5p_device_onenand = {
.name = "s5pc110-onenand",
.id = -1,
.num_resources = ARRAY_SIZE(s5pc110_onenand_resources),
.resource = s5pc110_onenand_resources,
.num_resources = ARRAY_SIZE(s5p_onenand_resources),
.resource = s5p_onenand_resources,
};
void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata)
void s5p_onenand_set_platdata(struct onenand_platform_data *pdata)
{
struct onenand_platform_data *pd;
pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
if (!pd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s5pc110_device_onenand.dev.platform_data = pd;
s5p_device_onenand.dev.platform_data = pd;
}

58
arch/arm/plat-s5p/dev-uart.c
View file

@ -119,6 +119,56 @@ static struct resource s5p_uart3_resource[] = {
#endif
};
static struct resource s5p_uart4_resource[] = {
#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
[0] = {
.start = S5P_PA_UART4,
.end = S5P_PA_UART4 + S5P_SZ_UART,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S5P_UART_RX4,
.end = IRQ_S5P_UART_RX4,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S5P_UART_TX4,
.end = IRQ_S5P_UART_TX4,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S5P_UART_ERR4,
.end = IRQ_S5P_UART_ERR4,
.flags = IORESOURCE_IRQ,
},
#endif
};
static struct resource s5p_uart5_resource[] = {
#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
[0] = {
.start = S5P_PA_UART5,
.end = S5P_PA_UART5 + S5P_SZ_UART,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S5P_UART_RX5,
.end = IRQ_S5P_UART_RX5,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S5P_UART_TX5,
.end = IRQ_S5P_UART_TX5,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S5P_UART_ERR5,
.end = IRQ_S5P_UART_ERR5,
.flags = IORESOURCE_IRQ,
},
#endif
};
struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
[0] = {
.resources = s5p_uart0_resource,
@ -136,4 +186,12 @@ struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
.resources = s5p_uart3_resource,
.nr_resources = ARRAY_SIZE(s5p_uart3_resource),
},
[4] = {
.resources = s5p_uart4_resource,
.nr_resources = ARRAY_SIZE(s5p_uart4_resource),
},
[5] = {
.resources = s5p_uart5_resource,
.nr_resources = ARRAY_SIZE(s5p_uart5_resource),
},
};

7
arch/arm/plat-s5p/include/plat/pll.h
View file

@ -47,6 +47,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
}
#define PLL46XX_KDIV_MASK (0xFFFF)
#define PLL4650C_KDIV_MASK (0xFFF)
#define PLL46XX_MDIV_MASK (0x1FF)
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
@ -57,6 +58,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
enum pll46xx_type_t {
pll_4600,
pll_4650,
pll_4650c,
};
static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
@ -72,6 +74,11 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
kdiv = pll_con1 & PLL46XX_KDIV_MASK;
if (pll_type == pll_4650c)
kdiv = pll_con1 & PLL4650C_KDIV_MASK;
else
kdiv = pll_con1 & PLL46XX_KDIV_MASK;
tmp = baseclk;
if (pll_type == pll_4600) {

8
arch/arm/plat-s5p/include/plat/s5p-clock.h
View file

@ -1,7 +1,7 @@
/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
*
* Copyright 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for s5p clock support
*
@ -20,6 +20,7 @@
#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fin_dpll clk_ext_xtal_mux
#define clk_fin_vpll clk_ext_xtal_mux
#define clk_fin_hpll clk_ext_xtal_mux
@ -30,6 +31,7 @@ extern struct clk s5p_clk_27m;
extern struct clk clk_fout_apll;
extern struct clk clk_fout_mpll;
extern struct clk clk_fout_epll;
extern struct clk clk_fout_dpll;
extern struct clk clk_fout_vpll;
extern struct clk clk_arm;
extern struct clk clk_vpll;
@ -37,8 +39,8 @@ extern struct clk clk_vpll;
extern struct clksrc_sources clk_src_apll;
extern struct clksrc_sources clk_src_mpll;
extern struct clksrc_sources clk_src_epll;
extern struct clksrc_sources clk_src_dpll;
extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable);
extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
#endif /* __ASM_PLAT_S5P_CLOCK_H */

7
arch/arm/plat-s5p/include/plat/s5p6440.h
View file

@ -12,24 +12,23 @@
/* Common init code for S5P6440 related SoCs */
extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s5p6440_register_clocks(void);
extern void s5p6440_setup_clocks(void);
#ifdef CONFIG_CPU_S5P6440
extern int s5p6440_init(void);
extern int s5p64x0_init(void);
extern void s5p6440_init_irq(void);
extern void s5p6440_map_io(void);
extern void s5p6440_init_clocks(int xtal);
#define s5p6440_init_uarts s5p6440_common_init_uarts
extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#else
#define s5p6440_init_clocks NULL
#define s5p6440_init_uarts NULL
#define s5p6440_map_io NULL
#define s5p6440_init NULL
#define s5p64x0_init NULL
#endif
/* S5P6440 timer */

36
arch/arm/plat-s5p/include/plat/s5p6450.h Normal file
View file

@ -0,0 +1,36 @@
/* arch/arm/plat-s5p/include/plat/s5p6450.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for s5p6450 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for S5P6450 related SoCs */
extern void s5p6450_register_clocks(void);
extern void s5p6450_setup_clocks(void);
#ifdef CONFIG_CPU_S5P6450
extern int s5p64x0_init(void);
extern void s5p6450_init_irq(void);
extern void s5p6450_map_io(void);
extern void s5p6450_init_clocks(int xtal);
extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#else
#define s5p6450_init_clocks NULL
#define s5p6450_init_uarts NULL
#define s5p6450_map_io NULL
#define s5p64x0_init NULL
#endif
/* S5P6450 timer */
extern struct sys_timer s5p6450_timer;

1
arch/arm/plat-samsung/adc.c
View file

@ -435,7 +435,6 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
static int s3c_adc_resume(struct platform_device *pdev)
{
struct adc_device *adc = platform_get_drvdata(pdev);
unsigned long flags;
clk_enable(adc->clk);
enable_irq(adc->irq);

27
arch/arm/plat-samsung/clock.c
View file

@ -48,6 +48,9 @@
#include <plat/clock.h>
#include <plat/cpu.h>
#include <linux/serial_core.h>
#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
/* clock information */
static LIST_HEAD(clocks);
@ -65,6 +68,28 @@ static int clk_null_enable(struct clk *clk, int enable)
return 0;
}
static int dev_is_s3c_uart(struct device *dev)
{
struct platform_device **pdev = s3c24xx_uart_devs;
int i;
for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
if (*pdev && dev == &(*pdev)->dev)
return 1;
return 0;
}
/*
* Serial drivers call get_clock() very early, before platform bus
* has been set up, this requires a special check to let them get
* a proper clock
*/
static int dev_is_platform_device(struct device *dev)
{
return dev->bus == &platform_bus_type ||
(dev->bus == NULL && dev_is_s3c_uart(dev));
}
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)
@ -73,7 +98,7 @@ struct clk *clk_get(struct device *dev, const char *id)
struct clk *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || dev->bus != &platform_bus_type)
if (dev == NULL || !dev_is_platform_device(dev))
idno = -1;
else
idno = to_platform_device(dev)->id;

2
arch/arm/plat-samsung/include/plat/cpu.h
View file

@ -79,7 +79,7 @@ extern struct sysdev_class s3c2442_sysclass;
extern struct sysdev_class s3c2443_sysclass;
extern struct sysdev_class s3c6410_sysclass;
extern struct sysdev_class s3c64xx_sysclass;
extern struct sysdev_class s5p6440_sysclass;
extern struct sysdev_class s5p64x0_sysclass;
extern struct sysdev_class s5p6442_sysclass;
extern struct sysdev_class s5pv210_sysclass;

7
arch/arm/plat-samsung/include/plat/devs.h
View file

@ -67,13 +67,15 @@ extern struct platform_device s5pv210_device_spi0;
extern struct platform_device s5pv210_device_spi1;
extern struct platform_device s5p6440_device_spi0;
extern struct platform_device s5p6440_device_spi1;
extern struct platform_device s5p6450_device_spi0;
extern struct platform_device s5p6450_device_spi1;
extern struct platform_device s3c_device_hwmon;
extern struct platform_device s3c_device_nand;
extern struct platform_device s3c_device_onenand;
extern struct platform_device s3c64xx_device_onenand1;
extern struct platform_device s5pc110_device_onenand;
extern struct platform_device s5p_device_onenand;
extern struct platform_device s3c_device_usbgadget;
extern struct platform_device s3c_device_usb_hsotg;
@ -95,6 +97,9 @@ extern struct platform_device s5p6442_device_spi;
extern struct platform_device s5p6440_device_pcm;
extern struct platform_device s5p6440_device_iis;
extern struct platform_device s5p6450_device_iis0;
extern struct platform_device s5p6450_device_pcm0;
extern struct platform_device s5pc100_device_ac97;
extern struct platform_device s5pc100_device_pcm0;
extern struct platform_device s5pc100_device_pcm1;

20
arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
View file

@ -32,6 +32,12 @@ enum dma_ch {
DMACH_UART2_TX,
DMACH_UART3_RX,
DMACH_UART3_TX,
DMACH_UART4_RX,
DMACH_UART4_TX,
DMACH_UART5_RX,
DMACH_UART5_TX,
DMACH_USI_RX,
DMACH_USI_TX,
DMACH_IRDA,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
@ -64,6 +70,20 @@ enum dma_ch {
DMACH_MSM_REQ2,
DMACH_MSM_REQ1,
DMACH_MSM_REQ0,
DMACH_SLIMBUS0_RX,
DMACH_SLIMBUS0_TX,
DMACH_SLIMBUS0AUX_RX,
DMACH_SLIMBUS0AUX_TX,
DMACH_SLIMBUS1_RX,
DMACH_SLIMBUS1_TX,
DMACH_SLIMBUS2_RX,
DMACH_SLIMBUS2_TX,
DMACH_SLIMBUS3_RX,
DMACH_SLIMBUS3_TX,
DMACH_SLIMBUS4_RX,
DMACH_SLIMBUS4_TX,
DMACH_SLIMBUS5_RX,
DMACH_SLIMBUS5_TX,
/* END Marker, also used to denote a reserved channel */
DMACH_MAX,
};

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