V4L/DVB (9513): cx18: Reduce number of mmio read retries

cx18: Reduce number of mmio read retries to improve performance.  Experiments
have shown 2 things: read retries never improve the result of a suspect mmio
read from the CX23418 (the result stays all 0xff's), and that most of the
suspected read failures are actually proper reads of values that should be
all 0xff's.  This change reduces the number of read retries and keeps the
count separate from write retries.

Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Andy Walls 2008-11-02 18:15:28 -03:00 committed by Mauro Carvalho Chehab
parent f2e52cd176
commit f7823f8f43
4 changed files with 22 additions and 21 deletions

View file

@ -63,7 +63,7 @@ int cx18_av_loadfw(struct cx18 *cx)
int retries2;
int unrec_err = 0;
for (retries2 = 0; retries2 < CX18_MAX_MMIO_RETRIES;
for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
retries2++) {
cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
dl_control);
@ -82,7 +82,7 @@ int cx18_av_loadfw(struct cx18 *cx)
}
cx18_log_write_retries(cx, retries2,
cx->reg_mem + 0xc40000 + CXADEC_DL_CTL);
if (unrec_err || retries2 >= CX18_MAX_MMIO_RETRIES)
if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
break;
}
if (i == size)

View file

@ -353,11 +353,12 @@ struct cx18_i2c_algo_callback_data {
int bus_index; /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
};
#define CX18_MAX_MMIO_RETRIES 10
#define CX18_MAX_MMIO_WR_RETRIES 10
#define CX18_MAX_MMIO_RD_RETRIES 2
struct cx18_mmio_stats {
atomic_t retried_write[CX18_MAX_MMIO_RETRIES+1];
atomic_t retried_read[CX18_MAX_MMIO_RETRIES+1];
atomic_t retried_write[CX18_MAX_MMIO_WR_RETRIES+1];
atomic_t retried_read[CX18_MAX_MMIO_RD_RETRIES+1];
};
/* Struct to hold info about cx18 cards */

View file

@ -31,10 +31,10 @@ void cx18_log_statistics(struct cx18 *cx)
if (!(cx18_debug & CX18_DBGFLG_INFO))
return;
for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++)
CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
atomic_read(&cx->mmio_stats.retried_write[i]));
for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++)
CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
atomic_read(&cx->mmio_stats.retried_read[i]));
return;
@ -43,7 +43,7 @@ void cx18_log_statistics(struct cx18 *cx)
void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_raw_writel_noretry(cx, val, addr);
if (val == cx18_raw_readl_noretry(cx, addr))
break;
@ -55,7 +55,7 @@ u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
{
int i;
u32 val;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_raw_readl_noretry(cx, addr);
if (val != 0xffffffff) /* PCI bus read error */
break;
@ -68,7 +68,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
{
int i;
u16 val;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_raw_readw_noretry(cx, addr);
if (val != 0xffff) /* PCI bus read error */
break;
@ -80,7 +80,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writel_noretry(cx, val, addr);
if (val == cx18_readl_noretry(cx, addr))
break;
@ -93,7 +93,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
{
int i;
eval &= mask;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writel_noretry(cx, val, addr);
if (eval == (cx18_readl_noretry(cx, addr) & mask))
break;
@ -104,7 +104,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writew_noretry(cx, val, addr);
if (val == cx18_readw_noretry(cx, addr))
break;
@ -115,7 +115,7 @@ void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writeb_noretry(cx, val, addr);
if (val == cx18_readb_noretry(cx, addr))
break;
@ -127,7 +127,7 @@ u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
{
int i;
u32 val;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_readl_noretry(cx, addr);
if (val != 0xffffffff) /* PCI bus read error */
break;
@ -140,7 +140,7 @@ u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
{
int i;
u16 val;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_readw_noretry(cx, addr);
if (val != 0xffff) /* PCI bus read error */
break;
@ -153,7 +153,7 @@ u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
{
int i;
u8 val;
for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_readb_noretry(cx, addr);
if (val != 0xff) /* PCI bus read error */
break;

View file

@ -41,8 +41,8 @@ static inline void cx18_io_delay(struct cx18 *cx)
static inline
void cx18_log_write_retries(struct cx18 *cx, int i, const void __iomem *addr)
{
if (i > CX18_MAX_MMIO_RETRIES)
i = CX18_MAX_MMIO_RETRIES;
if (i > CX18_MAX_MMIO_WR_RETRIES)
i = CX18_MAX_MMIO_WR_RETRIES;
atomic_inc(&cx->mmio_stats.retried_write[i]);
return;
}
@ -50,8 +50,8 @@ void cx18_log_write_retries(struct cx18 *cx, int i, const void __iomem *addr)
static inline
void cx18_log_read_retries(struct cx18 *cx, int i, const void __iomem *addr)
{
if (i > CX18_MAX_MMIO_RETRIES)
i = CX18_MAX_MMIO_RETRIES;
if (i > CX18_MAX_MMIO_RD_RETRIES)
i = CX18_MAX_MMIO_RD_RETRIES;
atomic_inc(&cx->mmio_stats.retried_read[i]);
return;
}