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iommu/msm: Add support for generic master bindings
This adds the xlate callback which gets invoked during device registration from DT. The master devices gets added through this. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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commit
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1 changed files with 59 additions and 2 deletions
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@ -28,6 +28,7 @@
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#include <linux/iommu.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/of_iommu.h>
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#include <asm/cacheflush.h>
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#include <asm/sizes.h>
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@ -702,6 +703,54 @@ static void print_ctx_regs(void __iomem *base, int ctx)
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GET_PRRR(base, ctx), GET_NMRR(base, ctx));
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}
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static void insert_iommu_master(struct device *dev,
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struct msm_iommu_dev **iommu,
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struct of_phandle_args *spec)
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{
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struct msm_iommu_ctx_dev *master = dev->archdata.iommu;
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int sid;
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if (list_empty(&(*iommu)->ctx_list)) {
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master = kzalloc(sizeof(*master), GFP_ATOMIC);
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master->of_node = dev->of_node;
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list_add(&master->list, &(*iommu)->ctx_list);
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dev->archdata.iommu = master;
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}
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for (sid = 0; sid < master->num_mids; sid++)
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if (master->mids[sid] == spec->args[0]) {
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dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n",
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sid);
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return;
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}
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master->mids[master->num_mids++] = spec->args[0];
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}
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static int qcom_iommu_of_xlate(struct device *dev,
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struct of_phandle_args *spec)
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{
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struct msm_iommu_dev *iommu;
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&msm_iommu_lock, flags);
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list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)
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if (iommu->dev->of_node == spec->np)
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break;
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if (!iommu || iommu->dev->of_node != spec->np) {
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ret = -ENODEV;
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goto fail;
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}
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insert_iommu_master(dev, &iommu, spec);
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fail:
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spin_unlock_irqrestore(&msm_iommu_lock, flags);
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return ret;
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}
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irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
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{
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struct msm_iommu_dev *iommu = dev_id;
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@ -737,7 +786,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
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return 0;
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}
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static const struct iommu_ops msm_iommu_ops = {
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static struct iommu_ops msm_iommu_ops = {
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.capable = msm_iommu_capable,
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.domain_alloc = msm_iommu_domain_alloc,
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.domain_free = msm_iommu_domain_free,
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@ -748,6 +797,7 @@ static const struct iommu_ops msm_iommu_ops = {
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.map_sg = default_iommu_map_sg,
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.iova_to_phys = msm_iommu_iova_to_phys,
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.pgsize_bitmap = MSM_IOMMU_PGSIZES,
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.of_xlate = qcom_iommu_of_xlate,
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};
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static int msm_iommu_probe(struct platform_device *pdev)
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@ -837,6 +887,7 @@ static int msm_iommu_probe(struct platform_device *pdev)
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}
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list_add(&iommu->dev_node, &qcom_iommu_devices);
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of_iommu_set_ops(pdev->dev.of_node, &msm_iommu_ops);
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pr_info("device mapped at %p, irq %d with %d ctx banks\n",
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iommu->base, iommu->irq, iommu->ncb);
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@ -935,7 +986,13 @@ static int __init msm_iommu_init(void)
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return 0;
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}
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subsys_initcall(msm_iommu_init);
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static int __init msm_iommu_of_setup(struct device_node *np)
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{
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msm_iommu_init();
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return 0;
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}
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IOMMU_OF_DECLARE(msm_iommu_of, "qcom,apq8064-iommu", msm_iommu_of_setup);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
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