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synced 2024-08-27 19:29:37 +00:00
staging: r8188eu: remove NumTotalRFPath from struct hal_data_8188e
NumTotalRFPath is 1 in this driver and it is only used as exit condition in for loops. Since NumTotalRFPath is always 1, all the loops have only a single iteration. So we can remove the for loops and the NumTotalRFPath variable. Signed-off-by: Michael Straube <straube.linux@gmail.com> Link: https://lore.kernel.org/r/20210917080615.25819-4-straube.linux@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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17be217613
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f7b687d6b6
5 changed files with 95 additions and 106 deletions
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@ -1691,7 +1691,6 @@ void rtl8188e_read_chip_version(struct adapter *padapter)
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pHalData->VersionID = ChipVersion;
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pHalData->rf_type = RF_1T1R;
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pHalData->NumTotalRFPath = 1;
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MSG_88E("RF_Type is %x!!\n", pHalData->rf_type);
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}
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@ -1999,7 +1998,8 @@ void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool Auto
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
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struct txpowerinfo24g pwrInfo24G;
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u8 rfPath, ch, group;
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u8 rfPath = 0;
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u8 ch, group;
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u8 TxCount;
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Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
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@ -2007,31 +2007,29 @@ void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool Auto
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if (!AutoLoadFail)
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pHalData->bTXPowerDataReadFromEEPORM = true;
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for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) {
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for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
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hal_get_chnl_group_88e(ch, &group);
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for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
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hal_get_chnl_group_88e(ch, &group);
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pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
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if (ch == 14)
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pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4];
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else
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pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
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pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
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if (ch == 14)
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pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4];
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else
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pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
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DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch);
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DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch]);
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DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch]);
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}
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for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
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pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
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pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
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pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
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pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
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DBG_88E("======= TxCount %d =======\n", TxCount);
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DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]);
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DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]);
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DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]);
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DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]);
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}
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DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch);
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DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch]);
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DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch]);
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}
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for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
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pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
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pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
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pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
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pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
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DBG_88E("======= TxCount %d =======\n", TxCount);
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DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]);
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DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]);
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DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]);
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DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]);
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}
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/* 2010/10/19 MH Add Regulator recognize for CU. */
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@ -143,12 +143,11 @@ void Hal_SetChannel(struct adapter *pAdapter)
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struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
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struct mp_priv *pmp = &pAdapter->mppriv;
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struct odm_dm_struct *pDM_Odm = &pHalData->odmpriv;
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u8 eRFPath;
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u8 eRFPath = 0;
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u8 channel = pmp->channel;
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/* set RF channel register */
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for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
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_write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
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_write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
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Hal_mpt_SwitchRfSetting(pAdapter);
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SelectChannel(pAdapter, channel);
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@ -863,7 +863,7 @@ void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth
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static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
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{
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u8 eRFPath;
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u8 eRFPath = 0;
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u32 param1, param2;
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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@ -876,10 +876,8 @@ static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
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/* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
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param1 = RF_CHNLBW;
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param2 = channel;
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for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
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pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
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PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
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}
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pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
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PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
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}
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void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
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@ -235,17 +235,17 @@ static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
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powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0;
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*(OfdmBase + i) = powerBase0;
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}
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for (i = 0; i < pHalData->NumTotalRFPath; i++) {
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/* Check HT20 to HT40 diff */
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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powerlevel[i] = pPowerLevelBW20[i];
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else
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powerlevel[i] = pPowerLevelBW40[i];
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
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*(MCSBase + i) = powerBase1;
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}
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/* Check HT20 to HT40 diff */
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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powerlevel[i] = pPowerLevelBW20[i];
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else
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powerlevel[i] = pPowerLevelBW40[i];
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
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*(MCSBase + i) = powerBase1;
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}
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static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
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u8 index, u32 *powerBase0, u32 *powerBase1,
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u32 *pOutWriteVal)
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@ -458,70 +458,68 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
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struct bb_reg_def *pPhyReg;
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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u32 u4RegValue = 0;
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u8 eRFPath;
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u8 eRFPath = 0;
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int rtStatus = _SUCCESS;
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/* 3----------------------------------------------------------------- */
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/* 3 <2> Initialize RF */
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/* 3----------------------------------------------------------------- */
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for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
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pPhyReg = &pHalData->PHYRegDef[eRFPath];
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/* Initialize RF */
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/*----Store original RFENV control type----*/
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switch (eRFPath) {
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case RF_PATH_A:
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case RF_PATH_C:
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u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
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break;
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case RF_PATH_B:
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case RF_PATH_D:
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u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16);
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break;
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}
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/*----Set RF_ENV enable----*/
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PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
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udelay(1);/* PlatformStallExecution(1); */
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pPhyReg = &pHalData->PHYRegDef[eRFPath];
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/*----Set RF_ENV output high----*/
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PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
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udelay(1);/* PlatformStallExecution(1); */
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/* Set bit number of Address and Data for RF register */
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PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
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udelay(1);/* PlatformStallExecution(1); */
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PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
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udelay(1);/* PlatformStallExecution(1); */
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/*----Initialize RF fom connfiguration file----*/
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switch (eRFPath) {
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case RF_PATH_A:
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if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
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rtStatus = _FAIL;
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break;
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case RF_PATH_B:
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if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
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rtStatus = _FAIL;
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break;
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case RF_PATH_C:
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break;
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case RF_PATH_D:
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break;
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}
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/*----Restore RFENV control type----*/;
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switch (eRFPath) {
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case RF_PATH_A:
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case RF_PATH_C:
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PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
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break;
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case RF_PATH_B:
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case RF_PATH_D:
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PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
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break;
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}
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if (rtStatus != _SUCCESS)
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goto phy_RF6052_Config_ParaFile_Fail;
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/*----Store original RFENV control type----*/
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switch (eRFPath) {
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case RF_PATH_A:
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case RF_PATH_C:
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u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
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break;
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case RF_PATH_B:
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case RF_PATH_D:
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u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16);
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break;
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}
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/*----Set RF_ENV enable----*/
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PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
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udelay(1);/* PlatformStallExecution(1); */
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/*----Set RF_ENV output high----*/
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PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
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udelay(1);/* PlatformStallExecution(1); */
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/* Set bit number of Address and Data for RF register */
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PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
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udelay(1);/* PlatformStallExecution(1); */
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PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
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udelay(1);/* PlatformStallExecution(1); */
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/*----Initialize RF fom connfiguration file----*/
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switch (eRFPath) {
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case RF_PATH_A:
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if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
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rtStatus = _FAIL;
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break;
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case RF_PATH_B:
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if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
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rtStatus = _FAIL;
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break;
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case RF_PATH_C:
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break;
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case RF_PATH_D:
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break;
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}
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/*----Restore RFENV control type----*/;
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switch (eRFPath) {
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case RF_PATH_A:
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case RF_PATH_C:
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PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
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break;
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case RF_PATH_B:
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case RF_PATH_D:
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PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
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break;
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}
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if (rtStatus != _SUCCESS)
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goto phy_RF6052_Config_ParaFile_Fail;
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return rtStatus;
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phy_RF6052_Config_ParaFile_Fail:
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@ -530,11 +528,8 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
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int PHY_RF6052_Config8188E(struct adapter *Adapter)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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int rtStatus = _SUCCESS;
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pHalData->NumTotalRFPath = 1;
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/* */
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/* Config BB and RF */
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/* */
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@ -228,7 +228,6 @@ struct hal_data_8188e {
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/* rf_ctrl */
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u8 rf_chip;
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u8 rf_type;
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u8 NumTotalRFPath;
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u8 BoardType;
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