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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'exynos-drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes
Summary: - Use generic function to get buffer count instead of specific one. In case of Exynos DRM, There was a special case which decides pixel format of a given buffer according to planer types, which is NV12M and NV12. However, NV12M doesn't exist in drm fourcc so it removes exynos_drm_format_num_buffers() specific to Exynos DRM and use a generic function, drm_format_num_planes() instead. - Allow mixer driver to support NV21 format for Video processor. This format was already supported but we just missed DRM_FORMAT_NV21 case so this patch considers the case so that Mixer driver can handle it correctly. - Add regression fix and some code cleanups. * 'exynos-drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: drm/exynos: dp: Lower level of EDID read success message drm/exynos: cleanup exynos_drm_plane drm/exynos: 'win' is always unsigned drm/exynos: mixer: don't dump registers under spinlock drm/exynos: Consolidate return statements in fimd_bind() drm/exynos: Constify exynos_drm_crtc_ops drm/exynos: Fix build breakage on !DRM_EXYNOS_FIMD drm/exynos: mixer: Constify platform_device_id drm/exynos: mixer: cleanup pixelformat handling drm/exynos: mixer: also allow NV21 for the video processor drm/exynos: mixer: remove buffer count handling in vp_video_buffer() drm/exynos: plane: honor buffer offset for dma_addr drm/exynos: fb: use drm_format_num_planes to get buffer count
This commit is contained in:
Dave Airlie
commit
f7c125a198
11 changed files with 92 additions and 148 deletions
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@ -91,7 +91,7 @@ static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
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static void decon_clear_channel(struct decon_context *ctx)
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{
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int win, ch_enabled = 0;
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unsigned int win, ch_enabled = 0;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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@ -710,7 +710,7 @@ static void decon_dpms(struct exynos_drm_crtc *crtc, int mode)
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}
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}
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static struct exynos_drm_crtc_ops decon_crtc_ops = {
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static const struct exynos_drm_crtc_ops decon_crtc_ops = {
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.dpms = decon_dpms,
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.mode_fixup = decon_mode_fixup,
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.commit = decon_commit,
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@ -32,7 +32,6 @@
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#include <drm/bridge/ptn3460.h>
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#include "exynos_dp_core.h"
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#include "exynos_drm_fimd.h"
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#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
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connector)
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@ -196,7 +195,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
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}
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}
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dev_err(dp->dev, "EDID Read success!\n");
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dev_dbg(dp->dev, "EDID Read success!\n");
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return 0;
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}
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@ -1066,6 +1065,8 @@ static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
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static void exynos_dp_poweron(struct exynos_dp_device *dp)
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{
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struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
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if (dp->dpms_mode == DRM_MODE_DPMS_ON)
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return;
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@ -1076,7 +1077,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
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}
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}
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fimd_dp_clock_enable(dp_to_crtc(dp), true);
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if (crtc->ops->clock_enable)
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crtc->ops->clock_enable(dp_to_crtc(dp), true);
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clk_prepare_enable(dp->clock);
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exynos_dp_phy_init(dp);
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@ -1087,6 +1089,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
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static void exynos_dp_poweroff(struct exynos_dp_device *dp)
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{
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struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
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if (dp->dpms_mode != DRM_MODE_DPMS_ON)
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return;
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@ -1102,7 +1106,8 @@ static void exynos_dp_poweroff(struct exynos_dp_device *dp)
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exynos_dp_phy_exit(dp);
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clk_disable_unprepare(dp->clock);
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fimd_dp_clock_enable(dp_to_crtc(dp), false);
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if (crtc->ops->clock_enable)
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crtc->ops->clock_enable(dp_to_crtc(dp), false);
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if (dp->panel) {
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if (drm_panel_unprepare(dp->panel))
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@ -238,11 +238,11 @@ static struct drm_crtc_funcs exynos_crtc_funcs = {
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};
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struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
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struct drm_plane *plane,
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int pipe,
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enum exynos_drm_output_type type,
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struct exynos_drm_crtc_ops *ops,
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void *ctx)
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struct drm_plane *plane,
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int pipe,
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enum exynos_drm_output_type type,
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const struct exynos_drm_crtc_ops *ops,
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void *ctx)
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{
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struct exynos_drm_crtc *exynos_crtc;
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struct exynos_drm_private *private = drm_dev->dev_private;
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@ -18,11 +18,11 @@
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#include "exynos_drm_drv.h"
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struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
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struct drm_plane *plane,
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int pipe,
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enum exynos_drm_output_type type,
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struct exynos_drm_crtc_ops *ops,
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void *context);
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struct drm_plane *plane,
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int pipe,
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enum exynos_drm_output_type type,
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const struct exynos_drm_crtc_ops *ops,
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void *context);
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int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe);
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void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe);
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void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int pipe);
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@ -71,13 +71,6 @@ enum exynos_drm_output_type {
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* @dma_addr: array of bus(accessed by dma) address to the memory region
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* allocated for a overlay.
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* @zpos: order of overlay layer(z position).
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* @index_color: if using color key feature then this value would be used
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* as index color.
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* @default_win: a window to be enabled.
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* @color_key: color key on or off.
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* @local_path: in case of lcd type, local path mode on or off.
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* @transparency: transparency on or off.
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* @activated: activated or not.
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* @enabled: enabled or not.
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* @resume: to resume or not.
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*
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@ -108,13 +101,7 @@ struct exynos_drm_plane {
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uint32_t pixel_format;
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dma_addr_t dma_addr[MAX_FB_BUFFER];
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unsigned int zpos;
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unsigned int index_color;
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bool default_win:1;
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bool color_key:1;
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bool local_path:1;
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bool transparency:1;
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bool activated:1;
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bool enabled:1;
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bool resume:1;
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};
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@ -181,6 +168,10 @@ struct exynos_drm_display {
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* @win_disable: disable hardware specific overlay.
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* @te_handler: trigger to transfer video image at the tearing effect
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* synchronization signal if there is a page flip request.
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* @clock_enable: optional function enabling/disabling display domain clock,
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* called from exynos-dp driver before powering up (with
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* 'enable' argument as true) and after powering down (with
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* 'enable' as false).
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*/
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struct exynos_drm_crtc;
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struct exynos_drm_crtc_ops {
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@ -195,6 +186,7 @@ struct exynos_drm_crtc_ops {
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void (*win_commit)(struct exynos_drm_crtc *crtc, unsigned int zpos);
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void (*win_disable)(struct exynos_drm_crtc *crtc, unsigned int zpos);
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void (*te_handler)(struct exynos_drm_crtc *crtc);
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void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable);
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};
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/*
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@ -221,7 +213,7 @@ struct exynos_drm_crtc {
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unsigned int dpms;
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wait_queue_head_t pending_flip_queue;
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struct drm_pending_vblank_event *event;
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struct exynos_drm_crtc_ops *ops;
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const struct exynos_drm_crtc_ops *ops;
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void *ctx;
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};
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@ -171,43 +171,6 @@ exynos_drm_framebuffer_init(struct drm_device *dev,
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return &exynos_fb->fb;
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}
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static u32 exynos_drm_format_num_buffers(struct drm_mode_fb_cmd2 *mode_cmd)
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{
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unsigned int cnt = 0;
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if (mode_cmd->pixel_format != DRM_FORMAT_NV12)
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return drm_format_num_planes(mode_cmd->pixel_format);
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while (cnt != MAX_FB_BUFFER) {
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if (!mode_cmd->handles[cnt])
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break;
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cnt++;
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}
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/*
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* check if NV12 or NV12M.
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*
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* NV12
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* handles[0] = base1, offsets[0] = 0
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* handles[1] = base1, offsets[1] = Y_size
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*
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* NV12M
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* handles[0] = base1, offsets[0] = 0
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* handles[1] = base2, offsets[1] = 0
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*/
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if (cnt == 2) {
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/*
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* in case of NV12 format, offsets[1] is not 0 and
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* handles[0] is same as handles[1].
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*/
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if (mode_cmd->offsets[1] &&
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mode_cmd->handles[0] == mode_cmd->handles[1])
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cnt = 1;
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}
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return cnt;
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}
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static struct drm_framebuffer *
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exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
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struct drm_mode_fb_cmd2 *mode_cmd)
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@ -230,7 +193,7 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
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drm_helper_mode_fill_fb_struct(&exynos_fb->fb, mode_cmd);
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exynos_fb->exynos_gem_obj[0] = to_exynos_gem_obj(obj);
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exynos_fb->buf_cnt = exynos_drm_format_num_buffers(mode_cmd);
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exynos_fb->buf_cnt = drm_format_num_planes(mode_cmd->pixel_format);
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DRM_DEBUG_KMS("buf_cnt = %d\n", exynos_fb->buf_cnt);
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@ -33,7 +33,6 @@
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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#include "exynos_drm_fimd.h"
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/*
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* FIMD stands for Fully Interactive Mobile Display and
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@ -216,7 +215,7 @@ static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
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DRM_DEBUG_KMS("vblank wait timed out.\n");
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}
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static void fimd_enable_video_output(struct fimd_context *ctx, int win,
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static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
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bool enable)
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{
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u32 val = readl(ctx->regs + WINCON(win));
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@ -229,7 +228,8 @@ static void fimd_enable_video_output(struct fimd_context *ctx, int win,
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writel(val, ctx->regs + WINCON(win));
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}
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static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
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static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
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unsigned int win,
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bool enable)
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{
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u32 val = readl(ctx->regs + SHADOWCON);
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@ -244,7 +244,7 @@ static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
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static void fimd_clear_channel(struct fimd_context *ctx)
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{
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int win, ch_enabled = 0;
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unsigned int win, ch_enabled = 0;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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@ -946,7 +946,24 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc)
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drm_handle_vblank(ctx->drm_dev, ctx->pipe);
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}
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static struct exynos_drm_crtc_ops fimd_crtc_ops = {
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static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
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{
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struct fimd_context *ctx = crtc->ctx;
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u32 val;
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/*
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* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
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* clock. On these SoCs the bootloader may enable it but any
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* power domain off/on will reset it to disable state.
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*/
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if (ctx->driver_data != &exynos5_fimd_driver_data)
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return;
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val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
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writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
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}
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static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
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.dpms = fimd_dpms,
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.mode_fixup = fimd_mode_fixup,
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.commit = fimd_commit,
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@ -956,6 +973,7 @@ static struct exynos_drm_crtc_ops fimd_crtc_ops = {
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.win_commit = fimd_win_commit,
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.win_disable = fimd_win_disable,
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.te_handler = fimd_te_handler,
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.clock_enable = fimd_dp_clock_enable,
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};
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static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
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@ -1025,12 +1043,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
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if (ctx->display)
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exynos_drm_create_enc_conn(drm_dev, ctx->display);
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ret = fimd_iommu_attach_devices(ctx, drm_dev);
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if (ret)
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return ret;
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return 0;
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return fimd_iommu_attach_devices(ctx, drm_dev);
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}
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static void fimd_unbind(struct device *dev, struct device *master,
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@ -1192,24 +1205,6 @@ static int fimd_remove(struct platform_device *pdev)
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return 0;
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}
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void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
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{
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struct fimd_context *ctx = crtc->ctx;
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u32 val;
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/*
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* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
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* clock. On these SoCs the bootloader may enable it but any
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* power domain off/on will reset it to disable state.
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*/
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if (ctx->driver_data != &exynos5_fimd_driver_data)
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return;
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val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
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writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
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}
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EXPORT_SYMBOL_GPL(fimd_dp_clock_enable);
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struct platform_driver fimd_driver = {
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.probe = fimd_probe,
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.remove = fimd_remove,
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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*
|
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
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* Free Software Foundation; either version 2 of the License, or (at your
|
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* option) any later version.
|
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*/
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#ifndef _EXYNOS_DRM_FIMD_H_
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#define _EXYNOS_DRM_FIMD_H_
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extern void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable);
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#endif /* _EXYNOS_DRM_FIMD_H_ */
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@ -76,7 +76,7 @@ int exynos_check_plane(struct drm_plane *plane, struct drm_framebuffer *fb)
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return -EFAULT;
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}
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exynos_plane->dma_addr[i] = buffer->dma_addr;
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exynos_plane->dma_addr[i] = buffer->dma_addr + fb->offsets[i];
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DRM_DEBUG_KMS("buffer: %d, dma_addr = 0x%lx\n",
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i, (unsigned long)exynos_plane->dma_addr[i]);
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|
|
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|
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@ -217,7 +217,7 @@ static int vidi_ctx_initialize(struct vidi_context *ctx,
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return 0;
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}
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static struct exynos_drm_crtc_ops vidi_crtc_ops = {
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static const struct exynos_drm_crtc_ops vidi_crtc_ops = {
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.dpms = vidi_dpms,
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.enable_vblank = vidi_enable_vblank,
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.disable_vblank = vidi_disable_vblank,
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|
|
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|
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@ -44,6 +44,12 @@
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|||
#define MIXER_WIN_NR 3
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#define MIXER_DEFAULT_WIN 0
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||||
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||||
/* The pixelformats that are natively supported by the mixer. */
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||||
#define MXR_FORMAT_RGB565 4
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||||
#define MXR_FORMAT_ARGB1555 5
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||||
#define MXR_FORMAT_ARGB4444 6
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||||
#define MXR_FORMAT_ARGB8888 7
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||||
|
||||
struct mixer_resources {
|
||||
int irq;
|
||||
void __iomem *mixer_regs;
|
||||
|
|
@ -327,7 +333,8 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
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mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
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||||
}
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||||
static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
|
||||
static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
|
||||
bool enable)
|
||||
{
|
||||
struct mixer_resources *res = &ctx->mixer_res;
|
||||
u32 val = enable ? ~0 : 0;
|
||||
|
|
@ -359,8 +366,6 @@ static void mixer_run(struct mixer_context *ctx)
|
|||
struct mixer_resources *res = &ctx->mixer_res;
|
||||
|
||||
mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
|
||||
|
||||
mixer_regs_dump(ctx);
|
||||
}
|
||||
|
||||
static void mixer_stop(struct mixer_context *ctx)
|
||||
|
|
@ -373,16 +378,13 @@ static void mixer_stop(struct mixer_context *ctx)
|
|||
while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
|
||||
--timeout)
|
||||
usleep_range(10000, 12000);
|
||||
|
||||
mixer_regs_dump(ctx);
|
||||
}
|
||||
|
||||
static void vp_video_buffer(struct mixer_context *ctx, int win)
|
||||
static void vp_video_buffer(struct mixer_context *ctx, unsigned int win)
|
||||
{
|
||||
struct mixer_resources *res = &ctx->mixer_res;
|
||||
unsigned long flags;
|
||||
struct exynos_drm_plane *plane;
|
||||
unsigned int buf_num = 1;
|
||||
dma_addr_t luma_addr[2], chroma_addr[2];
|
||||
bool tiled_mode = false;
|
||||
bool crcb_mode = false;
|
||||
|
|
@ -393,27 +395,18 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
|
|||
switch (plane->pixel_format) {
|
||||
case DRM_FORMAT_NV12:
|
||||
crcb_mode = false;
|
||||
buf_num = 2;
|
||||
break;
|
||||
/* TODO: single buffer format NV12, NV21 */
|
||||
case DRM_FORMAT_NV21:
|
||||
crcb_mode = true;
|
||||
break;
|
||||
default:
|
||||
/* ignore pixel format at disable time */
|
||||
if (!plane->dma_addr[0])
|
||||
break;
|
||||
|
||||
DRM_ERROR("pixel format for vp is wrong [%d].\n",
|
||||
plane->pixel_format);
|
||||
return;
|
||||
}
|
||||
|
||||
if (buf_num == 2) {
|
||||
luma_addr[0] = plane->dma_addr[0];
|
||||
chroma_addr[0] = plane->dma_addr[1];
|
||||
} else {
|
||||
luma_addr[0] = plane->dma_addr[0];
|
||||
chroma_addr[0] = plane->dma_addr[0]
|
||||
+ (plane->pitch * plane->fb_height);
|
||||
}
|
||||
luma_addr[0] = plane->dma_addr[0];
|
||||
chroma_addr[0] = plane->dma_addr[1];
|
||||
|
||||
if (plane->scan_flag & DRM_MODE_FLAG_INTERLACE) {
|
||||
ctx->interlace = true;
|
||||
|
|
@ -484,6 +477,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
|
|||
mixer_vsync_set_update(ctx, true);
|
||||
spin_unlock_irqrestore(&res->reg_slock, flags);
|
||||
|
||||
mixer_regs_dump(ctx);
|
||||
vp_regs_dump(ctx);
|
||||
}
|
||||
|
||||
|
|
@ -518,7 +512,7 @@ static int mixer_setup_scale(const struct exynos_drm_plane *plane,
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static void mixer_graph_buffer(struct mixer_context *ctx, int win)
|
||||
static void mixer_graph_buffer(struct mixer_context *ctx, unsigned int win)
|
||||
{
|
||||
struct mixer_resources *res = &ctx->mixer_res;
|
||||
unsigned long flags;
|
||||
|
|
@ -531,20 +525,27 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
|
|||
|
||||
plane = &ctx->planes[win];
|
||||
|
||||
#define RGB565 4
|
||||
#define ARGB1555 5
|
||||
#define ARGB4444 6
|
||||
#define ARGB8888 7
|
||||
switch (plane->pixel_format) {
|
||||
case DRM_FORMAT_XRGB4444:
|
||||
fmt = MXR_FORMAT_ARGB4444;
|
||||
break;
|
||||
|
||||
switch (plane->bpp) {
|
||||
case 16:
|
||||
fmt = ARGB4444;
|
||||
case DRM_FORMAT_XRGB1555:
|
||||
fmt = MXR_FORMAT_ARGB1555;
|
||||
break;
|
||||
case 32:
|
||||
fmt = ARGB8888;
|
||||
|
||||
case DRM_FORMAT_RGB565:
|
||||
fmt = MXR_FORMAT_RGB565;
|
||||
break;
|
||||
|
||||
case DRM_FORMAT_XRGB8888:
|
||||
case DRM_FORMAT_ARGB8888:
|
||||
fmt = MXR_FORMAT_ARGB8888;
|
||||
break;
|
||||
|
||||
default:
|
||||
fmt = ARGB8888;
|
||||
DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* check if mixer supports requested scaling setup */
|
||||
|
|
@ -617,6 +618,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
|
|||
|
||||
mixer_vsync_set_update(ctx, true);
|
||||
spin_unlock_irqrestore(&res->reg_slock, flags);
|
||||
|
||||
mixer_regs_dump(ctx);
|
||||
}
|
||||
|
||||
static void vp_win_reset(struct mixer_context *ctx)
|
||||
|
|
@ -1070,6 +1073,7 @@ static void mixer_poweroff(struct mixer_context *ctx)
|
|||
mutex_unlock(&ctx->mixer_mutex);
|
||||
|
||||
mixer_stop(ctx);
|
||||
mixer_regs_dump(ctx);
|
||||
mixer_window_suspend(ctx);
|
||||
|
||||
ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
|
||||
|
|
@ -1126,7 +1130,7 @@ int mixer_check_mode(struct drm_display_mode *mode)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct exynos_drm_crtc_ops mixer_crtc_ops = {
|
||||
static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
|
||||
.dpms = mixer_dpms,
|
||||
.enable_vblank = mixer_enable_vblank,
|
||||
.disable_vblank = mixer_disable_vblank,
|
||||
|
|
@ -1156,7 +1160,7 @@ static struct mixer_drv_data exynos4210_mxr_drv_data = {
|
|||
.has_sclk = 1,
|
||||
};
|
||||
|
||||
static struct platform_device_id mixer_driver_types[] = {
|
||||
static const struct platform_device_id mixer_driver_types[] = {
|
||||
{
|
||||
.name = "s5p-mixer",
|
||||
.driver_data = (unsigned long)&exynos4210_mxr_drv_data,
|
||||
|
|
|
|||
Loading…
Reference in a new issue