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arm64: dts: layerscape: Add label to pcie nodes 

Add label to pcie nodes so that they are easy to
refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Wasim Khan 2020-09-13 10:51:16 +05:30 committed by Shawn Guo
parent 7358e05bdd
commit f7d48ffcfc
7 changed files with 30 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
View File

@ -87,7 +87,7 @@
status = "okay";
};
&pcie {
&pcie1 {
status = "okay";
};

5
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1012A family SoC.
* Device Tree Include file for NXP Layerscape-1012A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019-2020 NXP
*
*/
@ -489,7 +490,7 @@
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
};
pcie: pcie@3400000 {
pcie1: pcie@3400000 {
compatible = "fsl,ls1012a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */

6
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1028A family SoC.
*
* Copyright 2018 NXP
* Copyright 2018-2020 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@ -553,7 +553,7 @@
status = "disabled";
};
pcie@3400000 {
pcie1: pcie@3400000 {
compatible = "fsl,ls1028a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
@ -580,7 +580,7 @@
status = "disabled";
};
pcie@3500000 {
pcie2: pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */

10
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -1,9 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* Copyright 2018, 2020 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
@ -814,7 +814,7 @@
interrupts = <0 160 0x4>;
};
pcie@3400000 {
pcie1: pcie@3400000 {
compatible = "fsl,ls1043a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
@ -840,7 +840,7 @@
status = "disabled";
};
pcie@3500000 {
pcie2: pcie@3500000 {
compatible = "fsl,ls1043a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
@ -866,7 +866,7 @@
status = "disabled";
};
pcie@3600000 {
pcie3: pcie@3600000 {
compatible = "fsl,ls1043a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */

16
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -1,9 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
* Device Tree Include file for NXP Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* Copyright 2018, 2020 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@ -718,7 +718,7 @@
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
pcie@3400000 {
pcie1: pcie@3400000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
@ -744,7 +744,7 @@
status = "disabled";
};
pcie_ep@3400000 {
pcie_ep1: pcie_ep@3400000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x40 0x00000000 0x8 0x00000000>;
@ -754,7 +754,7 @@
status = "disabled";
};
pcie@3500000 {
pcie2: pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
@ -780,7 +780,7 @@
status = "disabled";
};
pcie_ep@3500000 {
pcie_ep2: pcie_ep@3500000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
0x48 0x00000000 0x8 0x00000000>;
@ -790,7 +790,7 @@
status = "disabled";
};
pcie@3600000 {
pcie3: pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
@ -816,7 +816,7 @@
status = "disabled";
};
pcie_ep@3600000 {
pcie_ep3: pcie_ep@3600000 {
compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
0x50 0x00000000 0x8 0x00000000>;

8
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
* Copyright 2017 NXP
* Copyright 2017-2020 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@ -491,7 +491,7 @@
};
};
pcie@3400000 {
pcie1: pcie@3400000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x20 0x00000000 0x0 0x00002000>; /* configuration space */
@ -517,7 +517,7 @@
status = "disabled";
};
pcie@3500000 {
pcie2: pcie@3500000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x28 0x00000000 0x0 0x00002000>; /* configuration space */
@ -543,7 +543,7 @@
status = "disabled";
};
pcie@3600000 {
pcie3: pcie@3600000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x30 0x00000000 0x0 0x00002000>; /* configuration space */

12
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -1011,7 +1011,7 @@
status = "disabled";
};
pcie@3400000 {
pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
@ -1039,7 +1039,7 @@
status = "disabled";
};
pcie@3500000 {
pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
@ -1067,7 +1067,7 @@
status = "disabled";
};
pcie@3600000 {
pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
@ -1095,7 +1095,7 @@
status = "disabled";
};
pcie@3700000 {
pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
@ -1123,7 +1123,7 @@
status = "disabled";
};
pcie@3800000 {
pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
@ -1151,7 +1151,7 @@
status = "disabled";
};
pcie@3900000 {
pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */