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Code Issues Releases Wiki Activity

[SCSI] qla4xxx: Update function name from 8xxx to 82xx

Browse source 
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: Mike Christie <michaelc@cs.wisc.edu>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Vikas Chaudhary 2012-08-22 07:54:59 -04:00 committed by James Bottomley
parent d986788b26
commit f8086f4fd4
7 changed files with 352 additions and 351 deletions
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8
drivers/scsi/qla4xxx/ql4_attr.c
View file

@ -75,13 +75,13 @@ qla4_8xxx_sysfs_write_fw_dump(struct file *filep, struct kobject *kobj,
break;
case 2:
/* Reset HBA */
qla4_8xxx_idc_lock(ha);
dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
if (dev_state == QLA82XX_DEV_READY) {
ql4_printk(KERN_INFO, ha,
"%s: Setting Need reset, reset_owner is 0x%x.\n",
__func__, ha->func_num);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_NEED_RESET);
set_bit(AF_82XX_RST_OWNER, &ha->flags);
} else
@ -89,7 +89,7 @@ qla4_8xxx_sysfs_write_fw_dump(struct file *filep, struct kobject *kobj,
"%s: Reset not performed as device state is 0x%x\n",
__func__, dev_state);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
break;
default:
/* do nothing */

36
drivers/scsi/qla4xxx/ql4_glbl.h
View file

@ -109,28 +109,28 @@ uint8_t qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
void qla4_8xxx_pci_config(struct scsi_qla_host *);
int qla4_8xxx_iospace_config(struct scsi_qla_host *ha);
int qla4_8xxx_load_risc(struct scsi_qla_host *);
irqreturn_t qla4_8xxx_intr_handler(int irq, void *dev_id);
void qla4_8xxx_queue_iocb(struct scsi_qla_host *ha);
void qla4_8xxx_complete_iocb(struct scsi_qla_host *ha);
irqreturn_t qla4_82xx_intr_handler(int irq, void *dev_id);
void qla4_82xx_queue_iocb(struct scsi_qla_host *ha);
void qla4_82xx_complete_iocb(struct scsi_qla_host *ha);
int qla4_8xxx_crb_win_lock(struct scsi_qla_host *);
void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *);
int qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *, ulong *);
void qla4_8xxx_wr_32(struct scsi_qla_host *, ulong, u32);
int qla4_8xxx_rd_32(struct scsi_qla_host *, ulong);
int qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *, u64, void *, int);
int qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, u64, void *, int);
int qla4_8xxx_isp_reset(struct scsi_qla_host *ha);
void qla4_8xxx_interrupt_service_routine(struct scsi_qla_host *ha,
int qla4_82xx_crb_win_lock(struct scsi_qla_host *);
void qla4_82xx_crb_win_unlock(struct scsi_qla_host *);
int qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *, ulong *);
void qla4_82xx_wr_32(struct scsi_qla_host *, ulong, u32);
int qla4_82xx_rd_32(struct scsi_qla_host *, ulong);
int qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *, u64, void *, int);
int qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, u64, void *, int);
int qla4_82xx_isp_reset(struct scsi_qla_host *ha);
void qla4_82xx_interrupt_service_routine(struct scsi_qla_host *ha,
uint32_t intr_status);
uint16_t qla4_8xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha);
uint16_t qla4_8xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha);
uint16_t qla4_82xx_rd_shdw_req_q_out(struct scsi_qla_host *ha);
uint16_t qla4_82xx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha);
int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha);
void qla4_8xxx_watchdog(struct scsi_qla_host *ha);
int qla4_8xxx_stop_firmware(struct scsi_qla_host *ha);
int qla4_8xxx_get_flash_info(struct scsi_qla_host *ha);
void qla4_8xxx_enable_intrs(struct scsi_qla_host *ha);
void qla4_8xxx_disable_intrs(struct scsi_qla_host *ha);
void qla4_82xx_enable_intrs(struct scsi_qla_host *ha);
void qla4_82xx_disable_intrs(struct scsi_qla_host *ha);
int qla4_8xxx_enable_msix(struct scsi_qla_host *ha);
void qla4_8xxx_disable_msix(struct scsi_qla_host *ha);
irqreturn_t qla4_8xxx_msi_handler(int irq, void *dev_id);
@ -138,8 +138,8 @@ irqreturn_t qla4_8xxx_default_intr_handler(int irq, void *dev_id);
irqreturn_t qla4_8xxx_msix_rsp_q(int irq, void *dev_id);
void qla4xxx_mark_all_devices_missing(struct scsi_qla_host *ha);
void qla4xxx_dead_adapter_cleanup(struct scsi_qla_host *ha);
int qla4_8xxx_idc_lock(struct scsi_qla_host *ha);
void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha);
int qla4_82xx_idc_lock(struct scsi_qla_host *ha);
void qla4_82xx_idc_unlock(struct scsi_qla_host *ha);
int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha);
void qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha);
void qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha);

10
drivers/scsi/qla4xxx/ql4_iocb.c
View file

@ -193,31 +193,31 @@ static void qla4xxx_build_scsi_iocbs(struct srb *srb,
}
/**
* qla4_8xxx_queue_iocb - Tell ISP it's got new request(s)
* qla4_82xx_queue_iocb - Tell ISP it's got new request(s)
* @ha: pointer to host adapter structure.
*
* This routine notifies the ISP that one or more new request
* queue entries have been placed on the request queue.
**/
void qla4_8xxx_queue_iocb(struct scsi_qla_host *ha)
void qla4_82xx_queue_iocb(struct scsi_qla_host *ha)
{
uint32_t dbval = 0;
dbval = 0x14 | (ha->func_num << 5);
dbval = dbval | (0 << 8) | (ha->request_in << 16);
qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, ha->request_in);
qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, ha->request_in);
}
/**
* qla4_8xxx_complete_iocb - Tell ISP we're done with response(s)
* qla4_82xx_complete_iocb - Tell ISP we're done with response(s)
* @ha: pointer to host adapter structure.
*
* This routine notifies the ISP that one or more response/completion
* queue entries have been processed by the driver.
* This also clears the interrupt.
**/
void qla4_8xxx_complete_iocb(struct scsi_qla_host *ha)
void qla4_82xx_complete_iocb(struct scsi_qla_host *ha)
{
writel(ha->response_out, &ha->qla4_8xxx_reg->rsp_q_out);
readl(&ha->qla4_8xxx_reg->rsp_q_out);

40
drivers/scsi/qla4xxx/ql4_isr.c
View file

@ -816,13 +816,13 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha,
}
/**
* qla4_8xxx_interrupt_service_routine - isr
* qla4_82xx_interrupt_service_routine - isr
* @ha: pointer to host adapter structure.
*
* This is the main interrupt service routine.
* hardware_lock locked upon entry. runs in interrupt context.
**/
void qla4_8xxx_interrupt_service_routine(struct scsi_qla_host *ha,
void qla4_82xx_interrupt_service_routine(struct scsi_qla_host *ha,
uint32_t intr_status)
{
/* Process response queue interrupt. */
@ -866,12 +866,12 @@ void qla4xxx_interrupt_service_routine(struct scsi_qla_host * ha,
}
/**
* qla4_8xxx_spurious_interrupt - processes spurious interrupt
* qla4_82xx_spurious_interrupt - processes spurious interrupt
* @ha: pointer to host adapter structure.
* @reqs_count: .
*
**/
static void qla4_8xxx_spurious_interrupt(struct scsi_qla_host *ha,
static void qla4_82xx_spurious_interrupt(struct scsi_qla_host *ha,
uint8_t reqs_count)
{
if (reqs_count)
@ -881,7 +881,7 @@ static void qla4_8xxx_spurious_interrupt(struct scsi_qla_host *ha,
if (is_qla8022(ha)) {
writel(0, &ha->qla4_8xxx_reg->host_int);
if (test_bit(AF_INTx_ENABLED, &ha->flags))
qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
0xfbff);
}
ha->spurious_int_count++;
@ -984,11 +984,11 @@ irqreturn_t qla4xxx_intr_handler(int irq, void *dev_id)
}
/**
* qla4_8xxx_intr_handler - hardware interrupt handler.
* qla4_82xx_intr_handler - hardware interrupt handler.
* @irq: Unused
* @dev_id: Pointer to host adapter structure
**/
irqreturn_t qla4_8xxx_intr_handler(int irq, void *dev_id)
irqreturn_t qla4_82xx_intr_handler(int irq, void *dev_id)
{
struct scsi_qla_host *ha = dev_id;
uint32_t intr_status;
@ -1000,11 +1000,11 @@ irqreturn_t qla4_8xxx_intr_handler(int irq, void *dev_id)
return IRQ_HANDLED;
ha->isr_count++;
status = qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
status = qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
if (!(status & ha->nx_legacy_intr.int_vec_bit))
return IRQ_NONE;
status = qla4_8xxx_rd_32(ha, ISR_INT_STATE_REG);
status = qla4_82xx_rd_32(ha, ISR_INT_STATE_REG);
if (!ISR_IS_LEGACY_INTR_TRIGGERED(status)) {
DEBUG2(ql4_printk(KERN_INFO, ha,
"%s legacy Int not triggered\n", __func__));
@ -1012,30 +1012,30 @@ irqreturn_t qla4_8xxx_intr_handler(int irq, void *dev_id)
}
/* clear the interrupt */
qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
/* read twice to ensure write is flushed */
qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
spin_lock_irqsave(&ha->hardware_lock, flags);
while (1) {
if (!(readl(&ha->qla4_8xxx_reg->host_int) &
ISRX_82XX_RISC_INT)) {
qla4_8xxx_spurious_interrupt(ha, reqs_count);
qla4_82xx_spurious_interrupt(ha, reqs_count);
break;
}
intr_status = readl(&ha->qla4_8xxx_reg->host_status);
if ((intr_status &
(HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
qla4_8xxx_spurious_interrupt(ha, reqs_count);
qla4_82xx_spurious_interrupt(ha, reqs_count);
break;
}
ha->isp_ops->interrupt_service_routine(ha, intr_status);
/* Enable Interrupt */
qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
if (++reqs_count == MAX_REQS_SERVICED_PER_INTR)
break;
@ -1059,11 +1059,11 @@ qla4_8xxx_msi_handler(int irq, void *dev_id)
ha->isr_count++;
/* clear the interrupt */
qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
/* read twice to ensure write is flushed */
qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
return qla4_8xxx_default_intr_handler(irq, dev_id);
}
@ -1088,14 +1088,14 @@ qla4_8xxx_default_intr_handler(int irq, void *dev_id)
while (1) {
if (!(readl(&ha->qla4_8xxx_reg->host_int) &
ISRX_82XX_RISC_INT)) {
qla4_8xxx_spurious_interrupt(ha, reqs_count);
qla4_82xx_spurious_interrupt(ha, reqs_count);
break;
}
intr_status = readl(&ha->qla4_8xxx_reg->host_status);
if ((intr_status &
(HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
qla4_8xxx_spurious_interrupt(ha, reqs_count);
qla4_82xx_spurious_interrupt(ha, reqs_count);
break;
}

12
drivers/scsi/qla4xxx/ql4_mbx.c
View file

@ -85,9 +85,9 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
goto mbox_exit;
}
/* Do not send any mbx cmd if h/w is in failed state*/
qla4_8xxx_idc_lock(ha);
dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_unlock(ha);
if (dev_state == QLA82XX_DEV_FAILED) {
ql4_printk(KERN_WARNING, ha,
"scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
@ -180,7 +180,7 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
&ha->flags) &&
test_bit(AF_INTx_ENABLED,
&ha->flags))
qla4_8xxx_wr_32(ha,
qla4_82xx_wr_32(ha,
ha->nx_legacy_intr.tgt_mask_reg,
0xfbff);
}
@ -222,7 +222,7 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
if (is_qla8022(ha)) {
ql4_printk(KERN_INFO, ha,
"disabling pause transmit on port 0 & 1.\n");
qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
CRB_NIU_XG_PAUSE_CTL_P0 |
CRB_NIU_XG_PAUSE_CTL_P1);
}
@ -373,7 +373,7 @@ qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
if (is_qla8022(ha))
qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
mbox_cmd[1] = 0;

497
drivers/scsi/qla4xxx/ql4_nx.c
View file

File diff suppressed because it is too large Load diff

100
drivers/scsi/qla4xxx/ql4_os.c
View file

@ -2420,7 +2420,7 @@ static int qla4_8xxx_check_temp(struct scsi_qla_host *ha)
uint32_t temp, temp_state, temp_val;
int status = QLA_SUCCESS;
temp = qla4_8xxx_rd_32(ha, CRB_TEMP_STATE);
temp = qla4_82xx_rd_32(ha, CRB_TEMP_STATE);
temp_state = qla82xx_get_temp_state(temp);
temp_val = qla82xx_get_temp_val(temp);
@ -2456,7 +2456,7 @@ static int qla4_8xxx_check_fw_alive(struct scsi_qla_host *ha)
uint32_t fw_heartbeat_counter;
int status = QLA_SUCCESS;
fw_heartbeat_counter = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
fw_heartbeat_counter = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
/* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
if (fw_heartbeat_counter == 0xffffffff) {
DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Device in frozen "
@ -2478,19 +2478,19 @@ static int qla4_8xxx_check_fw_alive(struct scsi_qla_host *ha)
" 0x%x,\n PEG_NET_2_PC: 0x%x, PEG_NET_3_PC:"
" 0x%x,\n PEG_NET_4_PC: 0x%x\n",
ha->host_no, __func__,
qla4_8xxx_rd_32(ha,
qla4_82xx_rd_32(ha,
QLA82XX_PEG_HALT_STATUS1),
qla4_8xxx_rd_32(ha,
qla4_82xx_rd_32(ha,
QLA82XX_PEG_HALT_STATUS2),
qla4_8xxx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 +
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 +
0x3c),
qla4_8xxx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 +
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 +
0x3c),
qla4_8xxx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 +
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 +
0x3c),
qla4_8xxx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 +
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 +
0x3c),
qla4_8xxx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 +
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 +
0x3c));
status = QLA_ERROR;
}
@ -2515,12 +2515,12 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
if (!(test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags))) {
dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
if (qla4_8xxx_check_temp(ha)) {
ql4_printk(KERN_INFO, ha, "disabling pause"
" transmit on port 0 & 1.\n");
qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
CRB_NIU_XG_PAUSE_CTL_P0 |
CRB_NIU_XG_PAUSE_CTL_P1);
set_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
@ -2544,10 +2544,10 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
if (qla4_8xxx_check_fw_alive(ha)) {
ql4_printk(KERN_INFO, ha, "disabling pause"
" transmit on port 0 & 1.\n");
qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
CRB_NIU_XG_PAUSE_CTL_P0 |
CRB_NIU_XG_PAUSE_CTL_P1);
halt_status = qla4_8xxx_rd_32(ha,
halt_status = qla4_82xx_rd_32(ha,
QLA82XX_PEG_HALT_STATUS1);
if (QLA82XX_FWERROR_CODE(halt_status) == 0x67)
@ -3040,9 +3040,9 @@ static int qla4xxx_recover_adapter(struct scsi_qla_host *ha)
* with multiple resets in the same thread,
* utilize DPC to retry */
if (is_qla8022(ha)) {
qla4_8xxx_idc_lock(ha);
dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_unlock(ha);
if (dev_state == QLA82XX_DEV_FAILED) {
ql4_printk(KERN_INFO, ha, "%s: don't retry "
"recover adapter. H/W is in Failed "
@ -3385,10 +3385,10 @@ static void qla4xxx_do_dpc(struct work_struct *work)
if (is_qla8022(ha)) {
if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) {
qla4_8xxx_idc_lock(ha);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
qla4_82xx_idc_lock(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_FAILED);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
qla4_8xxx_device_state_handler(ha);
}
@ -3512,9 +3512,9 @@ static void qla4xxx_free_adapter(struct scsi_qla_host *ha)
ha->isp_ops->reset_firmware(ha);
if (is_qla8022(ha)) {
qla4_8xxx_idc_lock(ha);
qla4_82xx_idc_lock(ha);
qla4_8xxx_clear_drv_active(ha);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
}
/* Detach interrupts */
@ -3663,17 +3663,17 @@ static struct isp_operations qla4xxx_isp_ops = {
static struct isp_operations qla4_8xxx_isp_ops = {
.iospace_config = qla4_8xxx_iospace_config,
.pci_config = qla4_8xxx_pci_config,
.disable_intrs = qla4_8xxx_disable_intrs,
.enable_intrs = qla4_8xxx_enable_intrs,
.disable_intrs = qla4_82xx_disable_intrs,
.enable_intrs = qla4_82xx_enable_intrs,
.start_firmware = qla4_8xxx_load_risc,
.intr_handler = qla4_8xxx_intr_handler,
.interrupt_service_routine = qla4_8xxx_interrupt_service_routine,
.reset_chip = qla4_8xxx_isp_reset,
.intr_handler = qla4_82xx_intr_handler,
.interrupt_service_routine = qla4_82xx_interrupt_service_routine,
.reset_chip = qla4_82xx_isp_reset,
.reset_firmware = qla4_8xxx_stop_firmware,
.queue_iocb = qla4_8xxx_queue_iocb,
.complete_iocb = qla4_8xxx_complete_iocb,
.rd_shdw_req_q_out = qla4_8xxx_rd_shdw_req_q_out,
.rd_shdw_rsp_q_in = qla4_8xxx_rd_shdw_rsp_q_in,
.queue_iocb = qla4_82xx_queue_iocb,
.complete_iocb = qla4_82xx_complete_iocb,
.rd_shdw_req_q_out = qla4_82xx_rd_shdw_req_q_out,
.rd_shdw_rsp_q_in = qla4_82xx_rd_shdw_rsp_q_in,
.get_sys_info = qla4_8xxx_get_sys_info,
};
@ -3682,7 +3682,7 @@ uint16_t qla4xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha)
return (uint16_t)le32_to_cpu(ha->shadow_regs->req_q_out);
}
uint16_t qla4_8xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha)
uint16_t qla4_82xx_rd_shdw_req_q_out(struct scsi_qla_host *ha)
{
return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->req_q_out));
}
@ -3692,7 +3692,7 @@ uint16_t qla4xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha)
return (uint16_t)le32_to_cpu(ha->shadow_regs->rsp_q_in);
}
uint16_t qla4_8xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha)
uint16_t qla4_82xx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha)
{
return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->rsp_q_in));
}
@ -5161,9 +5161,9 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
init_retry_count++ < MAX_INIT_RETRIES) {
if (is_qla8022(ha)) {
qla4_8xxx_idc_lock(ha);
dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_unlock(ha);
if (dev_state == QLA82XX_DEV_FAILED) {
ql4_printk(KERN_WARNING, ha, "%s: don't retry "
"initialize adapter. H/W is in failed state\n",
@ -5186,10 +5186,10 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
if (is_qla8022(ha) && ql4xdontresethba) {
/* Put the device in failed state. */
DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n"));
qla4_8xxx_idc_lock(ha);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
qla4_82xx_idc_lock(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_FAILED);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
}
ret = -ENODEV;
goto remove_host;
@ -6033,31 +6033,31 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
"0x%x is the owner\n", ha->host_no, __func__,
ha->pdev->devfn);
qla4_8xxx_idc_lock(ha);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
qla4_82xx_idc_lock(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_COLD);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
QLA82XX_IDC_VERSION);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
clear_bit(AF_FW_RECOVERY, &ha->flags);
rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER);
qla4_8xxx_idc_lock(ha);
qla4_82xx_idc_lock(ha);
if (rval != QLA_SUCCESS) {
ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: "
"FAILED\n", ha->host_no, __func__);
qla4_8xxx_clear_drv_active(ha);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_FAILED);
} else {
ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: "
"READY\n", ha->host_no, __func__);
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_READY);
/* Clear driver state register */
qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
qla4_8xxx_set_drv_active(ha);
ret = qla4xxx_request_irqs(ha);
if (ret) {
@ -6070,12 +6070,12 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
rval = QLA_SUCCESS;
}
}
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
} else {
ql4_printk(KERN_INFO, ha, "scsi%ld: %s: devfn 0x%x is not "
"the reset owner\n", ha->host_no, __func__,
ha->pdev->devfn);
if ((qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
if ((qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
QLA82XX_DEV_READY)) {
clear_bit(AF_FW_RECOVERY, &ha->flags);
rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER);
@ -6091,9 +6091,9 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
rval = QLA_SUCCESS;
}
}
qla4_8xxx_idc_lock(ha);
qla4_82xx_idc_lock(ha);
qla4_8xxx_set_drv_active(ha);
qla4_8xxx_idc_unlock(ha);
qla4_82xx_idc_unlock(ha);
}
}
clear_bit(DPC_RESET_ACTIVE, &ha->dpc_flags);