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dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE. It shall helps the DMA clients to create size-optimized linked-list for the controller. However, there are certain situations where DMA client might not be abled to benefit from the dma_get_max_seg_size() if the segment size can't meet the nature of the DMA client's operation. In the case of ALSA operation, ALSA application and driver expecting to run in a period of larger than 10ms regardless of the bit depth. With this large period, there is a strong request to split the linked-list in the AxiDMA driver. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-18-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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parent
78a90a1e48
commit
f80f7c96f7
2 changed files with 91 additions and 19 deletions
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@ -581,6 +581,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
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if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
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mem_width = DWAXIDMAC_TRANS_WIDTH_32;
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if (!IS_ALIGNED(mem_addr, 4)) {
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dev_err(chan->chip->dev, "invalid buffer alignment\n");
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return -EINVAL;
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}
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switch (chan->direction) {
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case DMA_MEM_TO_DEV:
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reg_width = __ffs(chan->config.dst_addr_width);
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@ -642,6 +647,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
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return 0;
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}
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static size_t calculate_block_len(struct axi_dma_chan *chan,
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dma_addr_t dma_addr, size_t buf_len,
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enum dma_transfer_direction direction)
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{
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u32 data_width, reg_width, mem_width;
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size_t axi_block_ts, block_len;
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axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
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switch (direction) {
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case DMA_MEM_TO_DEV:
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data_width = BIT(chan->chip->dw->hdata->m_data_width);
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mem_width = __ffs(data_width | dma_addr | buf_len);
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if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
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mem_width = DWAXIDMAC_TRANS_WIDTH_32;
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block_len = axi_block_ts << mem_width;
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break;
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case DMA_DEV_TO_MEM:
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reg_width = __ffs(chan->config.src_addr_width);
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block_len = axi_block_ts << reg_width;
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break;
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default:
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block_len = 0;
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}
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return block_len;
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}
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static struct dma_async_tx_descriptor *
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dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
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size_t buf_len, size_t period_len,
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@ -652,13 +686,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
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struct axi_dma_hw_desc *hw_desc = NULL;
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struct axi_dma_desc *desc = NULL;
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dma_addr_t src_addr = dma_addr;
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u32 num_periods = buf_len / period_len;
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u32 num_periods, num_segments;
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size_t axi_block_len;
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u32 total_segments;
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u32 segment_len;
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unsigned int i;
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int status;
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u64 llp = 0;
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u8 lms = 0; /* Select AXI0 master for LLI fetching */
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desc = axi_desc_alloc(num_periods);
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num_periods = buf_len / period_len;
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axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
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if (axi_block_len == 0)
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return NULL;
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num_segments = DIV_ROUND_UP(period_len, axi_block_len);
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segment_len = DIV_ROUND_UP(period_len, num_segments);
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total_segments = num_periods * num_segments;
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desc = axi_desc_alloc(total_segments);
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if (unlikely(!desc))
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goto err_desc_get;
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@ -666,12 +714,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
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desc->chan = chan;
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chan->cyclic = true;
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desc->length = 0;
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desc->period_len = period_len;
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for (i = 0; i < num_periods; i++) {
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for (i = 0; i < total_segments; i++) {
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hw_desc = &desc->hw_desc[i];
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status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
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period_len);
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segment_len);
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if (status < 0)
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goto err_desc_get;
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@ -681,17 +730,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
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*/
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set_desc_last(hw_desc);
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src_addr += period_len;
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src_addr += segment_len;
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}
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llp = desc->hw_desc[0].llp;
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/* Managed transfer list */
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do {
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hw_desc = &desc->hw_desc[--num_periods];
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hw_desc = &desc->hw_desc[--total_segments];
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write_desc_llp(hw_desc, llp | lms);
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llp = hw_desc->llp;
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} while (num_periods);
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} while (total_segments);
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dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
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@ -713,9 +762,13 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
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struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
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struct axi_dma_hw_desc *hw_desc = NULL;
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struct axi_dma_desc *desc = NULL;
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u32 num_segments, segment_len;
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unsigned int loop = 0;
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struct scatterlist *sg;
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size_t axi_block_len;
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u32 len, num_sgs = 0;
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unsigned int i;
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u32 mem, len;
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dma_addr_t mem;
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int status;
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u64 llp = 0;
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u8 lms = 0; /* Select AXI0 master for LLI fetching */
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@ -723,35 +776,51 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
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if (unlikely(!is_slave_direction(direction) || !sg_len))
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return NULL;
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chan->direction = direction;
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mem = sg_dma_address(sgl);
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len = sg_dma_len(sgl);
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desc = axi_desc_alloc(sg_len);
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axi_block_len = calculate_block_len(chan, mem, len, direction);
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if (axi_block_len == 0)
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return NULL;
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for_each_sg(sgl, sg, sg_len, i)
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num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
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desc = axi_desc_alloc(num_sgs);
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if (unlikely(!desc))
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goto err_desc_get;
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desc->chan = chan;
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desc->length = 0;
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chan->direction = direction;
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for_each_sg(sgl, sg, sg_len, i) {
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mem = sg_dma_address(sg);
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len = sg_dma_len(sg);
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hw_desc = &desc->hw_desc[i];
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num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
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segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
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status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
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if (status < 0)
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goto err_desc_get;
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desc->length += hw_desc->len;
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do {
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hw_desc = &desc->hw_desc[loop++];
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status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
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if (status < 0)
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goto err_desc_get;
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desc->length += hw_desc->len;
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len -= segment_len;
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mem += segment_len;
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} while (len >= segment_len);
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}
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/* Set end-of-link to the last link descriptor of list */
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set_desc_last(&desc->hw_desc[sg_len - 1]);
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set_desc_last(&desc->hw_desc[num_sgs - 1]);
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/* Managed transfer list */
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do {
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hw_desc = &desc->hw_desc[--sg_len];
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hw_desc = &desc->hw_desc[--num_sgs];
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write_desc_llp(hw_desc, llp | lms);
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llp = hw_desc->llp;
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} while (sg_len);
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} while (num_sgs);
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dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
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@ -953,7 +1022,6 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
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vd = vchan_next_desc(&chan->vc);
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if (chan->cyclic) {
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vchan_cyclic_callback(vd);
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desc = vd_to_axi_desc(vd);
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if (desc) {
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llp = lo_hi_readq(chan->chan_regs + CH_LLP);
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@ -963,6 +1031,9 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
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axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
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hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
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desc->completed_blocks = i;
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if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
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vchan_cyclic_callback(vd);
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break;
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}
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}
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@ -100,6 +100,7 @@ struct axi_dma_desc {
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struct axi_dma_chan *chan;
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u32 completed_blocks;
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u32 length;
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u32 period_len;
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};
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static inline struct device *dchan2dev(struct dma_chan *dchan)
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