igc: Remove no need declaration of the igc_assign_vector
We want to avoid forward-declarations of function if possible. Rearrange the igc_assign_vector function implementation. Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -54,7 +54,6 @@ MODULE_DEVICE_TABLE(pci, igc_pci_tbl);
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/* forward declaration */
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/* forward declaration */
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static int igc_sw_init(struct igc_adapter *);
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static int igc_sw_init(struct igc_adapter *);
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static void igc_write_itr(struct igc_q_vector *q_vector);
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static void igc_write_itr(struct igc_q_vector *q_vector);
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static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector);
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enum latency_range {
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enum latency_range {
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lowest_latency = 0,
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lowest_latency = 0,
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@ -2195,6 +2194,67 @@ static void igc_configure(struct igc_adapter *adapter)
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}
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}
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}
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}
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/**
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* igc_write_ivar - configure ivar for given MSI-X vector
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* @hw: pointer to the HW structure
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* @msix_vector: vector number we are allocating to a given ring
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* @index: row index of IVAR register to write within IVAR table
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* @offset: column offset of in IVAR, should be multiple of 8
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*
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* The IVAR table consists of 2 columns,
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* each containing an cause allocation for an Rx and Tx ring, and a
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* variable number of rows depending on the number of queues supported.
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*/
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static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
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int index, int offset)
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{
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u32 ivar = array_rd32(IGC_IVAR0, index);
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/* clear any bits that are currently set */
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ivar &= ~((u32)0xFF << offset);
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/* write vector and valid bit */
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ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
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array_wr32(IGC_IVAR0, index, ivar);
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}
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static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
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{
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struct igc_adapter *adapter = q_vector->adapter;
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struct igc_hw *hw = &adapter->hw;
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int rx_queue = IGC_N0_QUEUE;
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int tx_queue = IGC_N0_QUEUE;
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if (q_vector->rx.ring)
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rx_queue = q_vector->rx.ring->reg_idx;
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if (q_vector->tx.ring)
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tx_queue = q_vector->tx.ring->reg_idx;
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switch (hw->mac.type) {
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case igc_i225:
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if (rx_queue > IGC_N0_QUEUE)
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igc_write_ivar(hw, msix_vector,
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rx_queue >> 1,
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(rx_queue & 0x1) << 4);
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if (tx_queue > IGC_N0_QUEUE)
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igc_write_ivar(hw, msix_vector,
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tx_queue >> 1,
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((tx_queue & 0x1) << 4) + 8);
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q_vector->eims_value = BIT(msix_vector);
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break;
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default:
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WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
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break;
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}
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/* add q_vector eims value to global eims_enable_mask */
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adapter->eims_enable_mask |= q_vector->eims_value;
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/* configure q_vector to set itr on first interrupt */
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q_vector->set_itr = 1;
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}
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/**
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/**
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* igc_configure_msix - Configure MSI-X hardware
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* igc_configure_msix - Configure MSI-X hardware
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* @adapter: Pointer to adapter structure
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* @adapter: Pointer to adapter structure
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@ -2871,67 +2931,6 @@ static irqreturn_t igc_msix_other(int irq, void *data)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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/**
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* igc_write_ivar - configure ivar for given MSI-X vector
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* @hw: pointer to the HW structure
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* @msix_vector: vector number we are allocating to a given ring
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* @index: row index of IVAR register to write within IVAR table
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* @offset: column offset of in IVAR, should be multiple of 8
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*
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* The IVAR table consists of 2 columns,
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* each containing an cause allocation for an Rx and Tx ring, and a
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* variable number of rows depending on the number of queues supported.
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*/
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static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
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int index, int offset)
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{
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u32 ivar = array_rd32(IGC_IVAR0, index);
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/* clear any bits that are currently set */
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ivar &= ~((u32)0xFF << offset);
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/* write vector and valid bit */
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ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
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array_wr32(IGC_IVAR0, index, ivar);
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}
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static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
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{
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struct igc_adapter *adapter = q_vector->adapter;
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struct igc_hw *hw = &adapter->hw;
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int rx_queue = IGC_N0_QUEUE;
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int tx_queue = IGC_N0_QUEUE;
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if (q_vector->rx.ring)
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rx_queue = q_vector->rx.ring->reg_idx;
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if (q_vector->tx.ring)
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tx_queue = q_vector->tx.ring->reg_idx;
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switch (hw->mac.type) {
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case igc_i225:
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if (rx_queue > IGC_N0_QUEUE)
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igc_write_ivar(hw, msix_vector,
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rx_queue >> 1,
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(rx_queue & 0x1) << 4);
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if (tx_queue > IGC_N0_QUEUE)
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igc_write_ivar(hw, msix_vector,
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tx_queue >> 1,
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((tx_queue & 0x1) << 4) + 8);
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q_vector->eims_value = BIT(msix_vector);
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break;
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default:
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WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
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break;
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}
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/* add q_vector eims value to global eims_enable_mask */
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adapter->eims_enable_mask |= q_vector->eims_value;
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/* configure q_vector to set itr on first interrupt */
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q_vector->set_itr = 1;
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}
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static irqreturn_t igc_msix_ring(int irq, void *data)
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static irqreturn_t igc_msix_ring(int irq, void *data)
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{
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{
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struct igc_q_vector *q_vector = data;
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struct igc_q_vector *q_vector = data;
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