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[POWERPC] Fix the UCC rx/tx clock of QE
MPC8323EMDS board ethernet interface with RMII uses the CLK16 divisor for the rx and tx clock, but the ucc_set_qe_mux_rxtx() function doesn't handle the CLK16 setting of the CMXUCR3 and CMXUCR4 registers. This fixes it. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -207,6 +207,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
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case QE_CLK18: source = 8; break;
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case QE_CLK7: source = 9; break;
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case QE_CLK8: source = 10; break;
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case QE_CLK16: source = 11; break;
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default: source = -1; break;
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}
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break;
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@ -222,6 +223,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
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case QE_CLK22: source = 8; break;
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case QE_CLK7: source = 9; break;
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case QE_CLK8: source = 10; break;
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case QE_CLK16: source = 11; break;
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default: source = -1; break;
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}
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break;
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