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perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support
M2PCIe* blocks manage the interface between the mesh and each IIO stack. The layout of the control registers for a M2PCIe uncore unit is similar to a IRP uncore unit. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com
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1 changed files with 6 additions and 1 deletions
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@ -5628,13 +5628,18 @@ static struct intel_uncore_type spr_uncore_irp = {
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};
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};
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static struct intel_uncore_type spr_uncore_m2pcie = {
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SPR_UNCORE_COMMON_FORMAT(),
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.name = "m2pcie",
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};
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#define UNCORE_SPR_NUM_UNCORE_TYPES 12
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#define UNCORE_SPR_NUM_UNCORE_TYPES 12
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static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
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static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
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&spr_uncore_chabox,
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&spr_uncore_chabox,
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&spr_uncore_iio,
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&spr_uncore_iio,
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&spr_uncore_irp,
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&spr_uncore_irp,
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NULL,
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&spr_uncore_m2pcie,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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