EDAC, xgene: Add SoC support
Add support for the SoC component. Signed-off-by: Loc Ho <lho@apm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mark.rutland@arm.com Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1443055261-8613-4-git-send-email-lho@apm.com Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Loc Ho
Borislav Petkov
parent
9bc1c0c0ec
commit
f864b79ba2
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@ -68,6 +68,7 @@ struct xgene_edac {
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struct list_head mcus;
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struct list_head pmds;
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struct list_head l3s;
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struct list_head socs;
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struct mutex mc_lock;
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int mc_active_mask;
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@ -1281,6 +1282,492 @@ static int xgene_edac_l3_remove(struct xgene_edac_dev_ctx *l3)
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return 0;
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}
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/* SoC error device */
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#define IOBAXIS0TRANSERRINTSTS 0x0000
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#define IOBAXIS0_M_ILLEGAL_ACCESS_MASK BIT(1)
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#define IOBAXIS0_ILLEGAL_ACCESS_MASK BIT(0)
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#define IOBAXIS0TRANSERRINTMSK 0x0004
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#define IOBAXIS0TRANSERRREQINFOL 0x0008
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#define IOBAXIS0TRANSERRREQINFOH 0x000c
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#define REQTYPE_RD(src) (((src) & BIT(0)))
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#define ERRADDRH_RD(src) (((src) & 0xffc00000) >> 22)
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#define IOBAXIS1TRANSERRINTSTS 0x0010
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#define IOBAXIS1TRANSERRINTMSK 0x0014
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#define IOBAXIS1TRANSERRREQINFOL 0x0018
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#define IOBAXIS1TRANSERRREQINFOH 0x001c
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#define IOBPATRANSERRINTSTS 0x0020
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#define IOBPA_M_REQIDRAM_CORRUPT_MASK BIT(7)
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#define IOBPA_REQIDRAM_CORRUPT_MASK BIT(6)
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#define IOBPA_M_TRANS_CORRUPT_MASK BIT(5)
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#define IOBPA_TRANS_CORRUPT_MASK BIT(4)
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#define IOBPA_M_WDATA_CORRUPT_MASK BIT(3)
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#define IOBPA_WDATA_CORRUPT_MASK BIT(2)
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#define IOBPA_M_RDATA_CORRUPT_MASK BIT(1)
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#define IOBPA_RDATA_CORRUPT_MASK BIT(0)
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#define IOBBATRANSERRINTSTS 0x0030
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#define M_ILLEGAL_ACCESS_MASK BIT(15)
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#define ILLEGAL_ACCESS_MASK BIT(14)
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#define M_WIDRAM_CORRUPT_MASK BIT(13)
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#define WIDRAM_CORRUPT_MASK BIT(12)
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#define M_RIDRAM_CORRUPT_MASK BIT(11)
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#define RIDRAM_CORRUPT_MASK BIT(10)
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#define M_TRANS_CORRUPT_MASK BIT(9)
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#define TRANS_CORRUPT_MASK BIT(8)
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#define M_WDATA_CORRUPT_MASK BIT(7)
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#define WDATA_CORRUPT_MASK BIT(6)
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#define M_RBM_POISONED_REQ_MASK BIT(5)
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#define RBM_POISONED_REQ_MASK BIT(4)
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#define M_XGIC_POISONED_REQ_MASK BIT(3)
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#define XGIC_POISONED_REQ_MASK BIT(2)
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#define M_WRERR_RESP_MASK BIT(1)
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#define WRERR_RESP_MASK BIT(0)
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#define IOBBATRANSERRREQINFOL 0x0038
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#define IOBBATRANSERRREQINFOH 0x003c
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#define REQTYPE_F2_RD(src) ((src) & BIT(0))
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#define ERRADDRH_F2_RD(src) (((src) & 0xffc00000) >> 22)
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#define IOBBATRANSERRCSWREQID 0x0040
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#define XGICTRANSERRINTSTS 0x0050
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#define M_WR_ACCESS_ERR_MASK BIT(3)
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#define WR_ACCESS_ERR_MASK BIT(2)
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#define M_RD_ACCESS_ERR_MASK BIT(1)
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#define RD_ACCESS_ERR_MASK BIT(0)
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#define XGICTRANSERRINTMSK 0x0054
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#define XGICTRANSERRREQINFO 0x0058
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#define REQTYPE_MASK BIT(26)
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#define ERRADDR_RD(src) ((src) & 0x03ffffff)
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#define GLBL_ERR_STS 0x0800
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#define MDED_ERR_MASK BIT(3)
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#define DED_ERR_MASK BIT(2)
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#define MSEC_ERR_MASK BIT(1)
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#define SEC_ERR_MASK BIT(0)
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#define GLBL_SEC_ERRL 0x0810
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#define GLBL_SEC_ERRH 0x0818
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#define GLBL_MSEC_ERRL 0x0820
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#define GLBL_MSEC_ERRH 0x0828
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#define GLBL_DED_ERRL 0x0830
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#define GLBL_DED_ERRLMASK 0x0834
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#define GLBL_DED_ERRH 0x0838
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#define GLBL_DED_ERRHMASK 0x083c
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#define GLBL_MDED_ERRL 0x0840
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#define GLBL_MDED_ERRLMASK 0x0844
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#define GLBL_MDED_ERRH 0x0848
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#define GLBL_MDED_ERRHMASK 0x084c
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static const char * const soc_mem_err_v1[] = {
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"10GbE0",
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"10GbE1",
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"Security",
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"SATA45",
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"SATA23/ETH23",
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"SATA01/ETH01",
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"USB1",
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"USB0",
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"QML",
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"QM0",
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"QM1 (XGbE01)",
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"PCIE4",
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"PCIE3",
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"PCIE2",
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"PCIE1",
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"PCIE0",
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"CTX Manager",
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"OCM",
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"1GbE",
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"CLE",
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"AHBC",
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"PktDMA",
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"GFC",
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"MSLIM",
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"10GbE2",
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"10GbE3",
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"QM2 (XGbE23)",
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"IOB",
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"unknown",
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"unknown",
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"unknown",
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"unknown",
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};
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static void xgene_edac_iob_gic_report(struct edac_device_ctl_info *edac_dev)
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{
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struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
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u32 err_addr_lo;
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u32 err_addr_hi;
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u32 reg;
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u32 info;
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/* GIC transaction error interrupt */
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reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS);
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if (!reg)
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goto chk_iob_err;
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dev_err(edac_dev->dev, "XGIC transaction error\n");
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if (reg & RD_ACCESS_ERR_MASK)
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dev_err(edac_dev->dev, "XGIC read size error\n");
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if (reg & M_RD_ACCESS_ERR_MASK)
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dev_err(edac_dev->dev, "Multiple XGIC read size error\n");
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if (reg & WR_ACCESS_ERR_MASK)
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dev_err(edac_dev->dev, "XGIC write size error\n");
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if (reg & M_WR_ACCESS_ERR_MASK)
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dev_err(edac_dev->dev, "Multiple XGIC write size error\n");
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info = readl(ctx->dev_csr + XGICTRANSERRREQINFO);
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dev_err(edac_dev->dev, "XGIC %s access @ 0x%08X (0x%08X)\n",
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info & REQTYPE_MASK ? "read" : "write", ERRADDR_RD(info),
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info);
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writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS);
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chk_iob_err:
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/* IOB memory error */
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reg = readl(ctx->dev_csr + GLBL_ERR_STS);
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if (!reg)
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return;
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if (reg & SEC_ERR_MASK) {
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err_addr_lo = readl(ctx->dev_csr + GLBL_SEC_ERRL);
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err_addr_hi = readl(ctx->dev_csr + GLBL_SEC_ERRH);
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dev_err(edac_dev->dev,
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"IOB single-bit correctable memory at 0x%08X.%08X error\n",
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err_addr_lo, err_addr_hi);
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writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL);
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writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH);
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}
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if (reg & MSEC_ERR_MASK) {
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err_addr_lo = readl(ctx->dev_csr + GLBL_MSEC_ERRL);
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err_addr_hi = readl(ctx->dev_csr + GLBL_MSEC_ERRH);
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dev_err(edac_dev->dev,
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"IOB multiple single-bit correctable memory at 0x%08X.%08X error\n",
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err_addr_lo, err_addr_hi);
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writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL);
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writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH);
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}
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if (reg & (SEC_ERR_MASK | MSEC_ERR_MASK))
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edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
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if (reg & DED_ERR_MASK) {
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err_addr_lo = readl(ctx->dev_csr + GLBL_DED_ERRL);
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err_addr_hi = readl(ctx->dev_csr + GLBL_DED_ERRH);
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dev_err(edac_dev->dev,
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"IOB double-bit uncorrectable memory at 0x%08X.%08X error\n",
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err_addr_lo, err_addr_hi);
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writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL);
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writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH);
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}
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if (reg & MDED_ERR_MASK) {
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err_addr_lo = readl(ctx->dev_csr + GLBL_MDED_ERRL);
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err_addr_hi = readl(ctx->dev_csr + GLBL_MDED_ERRH);
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dev_err(edac_dev->dev,
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"Multiple IOB double-bit uncorrectable memory at 0x%08X.%08X error\n",
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err_addr_lo, err_addr_hi);
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writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL);
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writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH);
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}
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if (reg & (DED_ERR_MASK | MDED_ERR_MASK))
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edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
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}
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static void xgene_edac_rb_report(struct edac_device_ctl_info *edac_dev)
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{
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struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
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u32 err_addr_lo;
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u32 err_addr_hi;
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u32 reg;
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/* IOB Bridge agent transaction error interrupt */
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reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS);
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if (!reg)
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return;
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dev_err(edac_dev->dev, "IOB bridge agent (BA) transaction error\n");
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if (reg & WRERR_RESP_MASK)
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dev_err(edac_dev->dev, "IOB BA write response error\n");
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if (reg & M_WRERR_RESP_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB BA write response error\n");
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if (reg & XGIC_POISONED_REQ_MASK)
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dev_err(edac_dev->dev, "IOB BA XGIC poisoned write error\n");
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if (reg & M_XGIC_POISONED_REQ_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB BA XGIC poisoned write error\n");
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if (reg & RBM_POISONED_REQ_MASK)
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dev_err(edac_dev->dev, "IOB BA RBM poisoned write error\n");
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if (reg & M_RBM_POISONED_REQ_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB BA RBM poisoned write error\n");
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if (reg & WDATA_CORRUPT_MASK)
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dev_err(edac_dev->dev, "IOB BA write error\n");
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if (reg & M_WDATA_CORRUPT_MASK)
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dev_err(edac_dev->dev, "Multiple IOB BA write error\n");
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if (reg & TRANS_CORRUPT_MASK)
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dev_err(edac_dev->dev, "IOB BA transaction error\n");
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if (reg & M_TRANS_CORRUPT_MASK)
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dev_err(edac_dev->dev, "Multiple IOB BA transaction error\n");
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if (reg & RIDRAM_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"IOB BA RDIDRAM read transaction ID error\n");
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if (reg & M_RIDRAM_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB BA RDIDRAM read transaction ID error\n");
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if (reg & WIDRAM_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"IOB BA RDIDRAM write transaction ID error\n");
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if (reg & M_WIDRAM_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB BA RDIDRAM write transaction ID error\n");
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if (reg & ILLEGAL_ACCESS_MASK)
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dev_err(edac_dev->dev,
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"IOB BA XGIC/RB illegal access error\n");
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if (reg & M_ILLEGAL_ACCESS_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB BA XGIC/RB illegal access error\n");
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err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL);
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err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH);
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dev_err(edac_dev->dev, "IOB BA %s access at 0x%02X.%08X (0x%08X)\n",
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REQTYPE_F2_RD(err_addr_hi) ? "read" : "write",
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ERRADDRH_F2_RD(err_addr_hi), err_addr_lo, err_addr_hi);
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if (reg & WRERR_RESP_MASK)
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dev_err(edac_dev->dev, "IOB BA requestor ID 0x%08X\n",
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readl(ctx->dev_csr + IOBBATRANSERRCSWREQID));
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writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS);
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}
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static void xgene_edac_pa_report(struct edac_device_ctl_info *edac_dev)
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{
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struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
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u32 err_addr_lo;
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u32 err_addr_hi;
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u32 reg;
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/* IOB Processing agent transaction error interrupt */
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reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS);
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if (!reg)
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goto chk_iob_axi0;
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dev_err(edac_dev->dev, "IOB procesing agent (PA) transaction error\n");
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if (reg & IOBPA_RDATA_CORRUPT_MASK)
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dev_err(edac_dev->dev, "IOB PA read data RAM error\n");
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if (reg & IOBPA_M_RDATA_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"Mutilple IOB PA read data RAM error\n");
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if (reg & IOBPA_WDATA_CORRUPT_MASK)
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dev_err(edac_dev->dev, "IOB PA write data RAM error\n");
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if (reg & IOBPA_M_WDATA_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"Mutilple IOB PA write data RAM error\n");
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if (reg & IOBPA_TRANS_CORRUPT_MASK)
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dev_err(edac_dev->dev, "IOB PA transaction error\n");
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if (reg & IOBPA_M_TRANS_CORRUPT_MASK)
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dev_err(edac_dev->dev, "Mutilple IOB PA transaction error\n");
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if (reg & IOBPA_REQIDRAM_CORRUPT_MASK)
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dev_err(edac_dev->dev, "IOB PA transaction ID RAM error\n");
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if (reg & IOBPA_M_REQIDRAM_CORRUPT_MASK)
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dev_err(edac_dev->dev,
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"Multiple IOB PA transaction ID RAM error\n");
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writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS);
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chk_iob_axi0:
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/* IOB AXI0 Error */
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reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
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if (!reg)
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goto chk_iob_axi1;
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err_addr_lo = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOL);
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err_addr_hi = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOH);
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dev_err(edac_dev->dev,
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"%sAXI slave 0 illegal %s access @ 0x%02X.%08X (0x%08X)\n",
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reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "",
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REQTYPE_RD(err_addr_hi) ? "read" : "write",
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ERRADDRH_RD(err_addr_hi), err_addr_lo, err_addr_hi);
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writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
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chk_iob_axi1:
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/* IOB AXI1 Error */
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reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
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if (!reg)
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return;
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err_addr_lo = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOL);
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err_addr_hi = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOH);
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dev_err(edac_dev->dev,
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"%sAXI slave 1 illegal %s access @ 0x%02X.%08X (0x%08X)\n",
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reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "",
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REQTYPE_RD(err_addr_hi) ? "read" : "write",
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ERRADDRH_RD(err_addr_hi), err_addr_lo, err_addr_hi);
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writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
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}
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static void xgene_edac_soc_check(struct edac_device_ctl_info *edac_dev)
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{
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struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
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const char * const *soc_mem_err = NULL;
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u32 pcp_hp_stat;
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u32 pcp_lp_stat;
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u32 reg;
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int i;
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xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat);
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xgene_edac_pcp_rd(ctx->edac, PCPLPERRINTSTS, &pcp_lp_stat);
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xgene_edac_pcp_rd(ctx->edac, MEMERRINTSTS, ®);
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if (!((pcp_hp_stat & (IOB_PA_ERR_MASK | IOB_BA_ERR_MASK |
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IOB_XGIC_ERR_MASK | IOB_RB_ERR_MASK)) ||
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(pcp_lp_stat & CSW_SWITCH_TRACE_ERR_MASK) || reg))
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return;
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if (pcp_hp_stat & IOB_XGIC_ERR_MASK)
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xgene_edac_iob_gic_report(edac_dev);
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if (pcp_hp_stat & (IOB_RB_ERR_MASK | IOB_BA_ERR_MASK))
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xgene_edac_rb_report(edac_dev);
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if (pcp_hp_stat & IOB_PA_ERR_MASK)
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xgene_edac_pa_report(edac_dev);
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if (pcp_lp_stat & CSW_SWITCH_TRACE_ERR_MASK) {
|
||||
dev_info(edac_dev->dev,
|
||||
"CSW switch trace correctable memory parity error\n");
|
||||
edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
|
||||
}
|
||||
|
||||
if (!reg)
|
||||
return;
|
||||
if (ctx->version == 1)
|
||||
soc_mem_err = soc_mem_err_v1;
|
||||
if (!soc_mem_err) {
|
||||
dev_err(edac_dev->dev, "SoC memory parity error 0x%08X\n",
|
||||
reg);
|
||||
edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
|
||||
return;
|
||||
}
|
||||
for (i = 0; i < 31; i++) {
|
||||
if (reg & (1 << i)) {
|
||||
dev_err(edac_dev->dev, "%s memory parity error\n",
|
||||
soc_mem_err[i]);
|
||||
edac_device_handle_ue(edac_dev, 0, 0,
|
||||
edac_dev->ctl_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void xgene_edac_soc_hw_init(struct edac_device_ctl_info *edac_dev,
|
||||
bool enable)
|
||||
{
|
||||
struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
|
||||
|
||||
/* Enable SoC IP error interrupt */
|
||||
if (edac_dev->op_state == OP_RUNNING_INTERRUPT) {
|
||||
if (enable) {
|
||||
xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK,
|
||||
IOB_PA_ERR_MASK |
|
||||
IOB_BA_ERR_MASK |
|
||||
IOB_XGIC_ERR_MASK |
|
||||
IOB_RB_ERR_MASK);
|
||||
xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK,
|
||||
CSW_SWITCH_TRACE_ERR_MASK);
|
||||
} else {
|
||||
xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK,
|
||||
IOB_PA_ERR_MASK |
|
||||
IOB_BA_ERR_MASK |
|
||||
IOB_XGIC_ERR_MASK |
|
||||
IOB_RB_ERR_MASK);
|
||||
xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK,
|
||||
CSW_SWITCH_TRACE_ERR_MASK);
|
||||
}
|
||||
|
||||
writel(enable ? 0x0 : 0xFFFFFFFF,
|
||||
ctx->dev_csr + IOBAXIS0TRANSERRINTMSK);
|
||||
writel(enable ? 0x0 : 0xFFFFFFFF,
|
||||
ctx->dev_csr + IOBAXIS1TRANSERRINTMSK);
|
||||
writel(enable ? 0x0 : 0xFFFFFFFF,
|
||||
ctx->dev_csr + XGICTRANSERRINTMSK);
|
||||
|
||||
xgene_edac_pcp_setbits(ctx->edac, MEMERRINTMSK,
|
||||
enable ? 0x0 : 0xFFFFFFFF);
|
||||
}
|
||||
}
|
||||
|
||||
static int xgene_edac_soc_add(struct xgene_edac *edac, struct device_node *np,
|
||||
int version)
|
||||
{
|
||||
struct edac_device_ctl_info *edac_dev;
|
||||
struct xgene_edac_dev_ctx *ctx;
|
||||
void __iomem *dev_csr;
|
||||
struct resource res;
|
||||
int edac_idx;
|
||||
int rc;
|
||||
|
||||
if (!devres_open_group(edac->dev, xgene_edac_soc_add, GFP_KERNEL))
|
||||
return -ENOMEM;
|
||||
|
||||
rc = of_address_to_resource(np, 0, &res);
|
||||
if (rc < 0) {
|
||||
dev_err(edac->dev, "no SoC resource address\n");
|
||||
goto err_release_group;
|
||||
}
|
||||
dev_csr = devm_ioremap_resource(edac->dev, &res);
|
||||
if (IS_ERR(dev_csr)) {
|
||||
dev_err(edac->dev,
|
||||
"devm_ioremap_resource failed for soc resource address\n");
|
||||
rc = PTR_ERR(dev_csr);
|
||||
goto err_release_group;
|
||||
}
|
||||
|
||||
edac_idx = edac_device_alloc_index();
|
||||
edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx),
|
||||
"SOC", 1, "SOC", 1, 2, NULL, 0,
|
||||
edac_idx);
|
||||
if (!edac_dev) {
|
||||
rc = -ENOMEM;
|
||||
goto err_release_group;
|
||||
}
|
||||
|
||||
ctx = edac_dev->pvt_info;
|
||||
ctx->dev_csr = dev_csr;
|
||||
ctx->name = "xgene_soc_err";
|
||||
ctx->edac_idx = edac_idx;
|
||||
ctx->edac = edac;
|
||||
ctx->edac_dev = edac_dev;
|
||||
ctx->ddev = *edac->dev;
|
||||
ctx->version = version;
|
||||
edac_dev->dev = &ctx->ddev;
|
||||
edac_dev->ctl_name = ctx->name;
|
||||
edac_dev->dev_name = ctx->name;
|
||||
edac_dev->mod_name = EDAC_MOD_STR;
|
||||
|
||||
if (edac_op_state == EDAC_OPSTATE_POLL)
|
||||
edac_dev->edac_check = xgene_edac_soc_check;
|
||||
|
||||
rc = edac_device_add_device(edac_dev);
|
||||
if (rc > 0) {
|
||||
dev_err(edac->dev, "failed edac_device_add_device()\n");
|
||||
rc = -ENOMEM;
|
||||
goto err_ctl_free;
|
||||
}
|
||||
|
||||
if (edac_op_state == EDAC_OPSTATE_INT)
|
||||
edac_dev->op_state = OP_RUNNING_INTERRUPT;
|
||||
|
||||
list_add(&ctx->next, &edac->socs);
|
||||
|
||||
xgene_edac_soc_hw_init(edac_dev, 1);
|
||||
|
||||
devres_remove_group(edac->dev, xgene_edac_soc_add);
|
||||
|
||||
dev_info(edac->dev, "X-Gene EDAC SoC registered\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_ctl_free:
|
||||
edac_device_free_ctl_info(edac_dev);
|
||||
err_release_group:
|
||||
devres_release_group(edac->dev, xgene_edac_soc_add);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int xgene_edac_soc_remove(struct xgene_edac_dev_ctx *soc)
|
||||
{
|
||||
struct edac_device_ctl_info *edac_dev = soc->edac_dev;
|
||||
|
||||
xgene_edac_soc_hw_init(edac_dev, 0);
|
||||
edac_device_del_device(soc->edac->dev);
|
||||
edac_device_free_ctl_info(edac_dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t xgene_edac_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct xgene_edac *ctx = dev_id;
|
||||
|
|
@ -1308,6 +1795,9 @@ static irqreturn_t xgene_edac_isr(int irq, void *dev_id)
|
|||
list_for_each_entry(node, &ctx->l3s, next)
|
||||
xgene_edac_l3_check(node->edac_dev);
|
||||
|
||||
list_for_each_entry(node, &ctx->socs, next)
|
||||
xgene_edac_soc_check(node->edac_dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
@ -1327,6 +1817,7 @@ static int xgene_edac_probe(struct platform_device *pdev)
|
|||
INIT_LIST_HEAD(&edac->mcus);
|
||||
INIT_LIST_HEAD(&edac->pmds);
|
||||
INIT_LIST_HEAD(&edac->l3s);
|
||||
INIT_LIST_HEAD(&edac->socs);
|
||||
spin_lock_init(&edac->lock);
|
||||
mutex_init(&edac->mc_lock);
|
||||
|
||||
|
|
@ -1406,6 +1897,10 @@ static int xgene_edac_probe(struct platform_device *pdev)
|
|||
xgene_edac_l3_add(edac, child, 1);
|
||||
if (of_device_is_compatible(child, "apm,xgene-edac-l3-v2"))
|
||||
xgene_edac_l3_add(edac, child, 2);
|
||||
if (of_device_is_compatible(child, "apm,xgene-edac-soc"))
|
||||
xgene_edac_soc_add(edac, child, 0);
|
||||
if (of_device_is_compatible(child, "apm,xgene-edac-soc-v1"))
|
||||
xgene_edac_soc_add(edac, child, 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1433,6 +1928,9 @@ static int xgene_edac_remove(struct platform_device *pdev)
|
|||
list_for_each_entry_safe(node, temp_node, &edac->l3s, next)
|
||||
xgene_edac_l3_remove(node);
|
||||
|
||||
list_for_each_entry_safe(node, temp_node, &edac->socs, next)
|
||||
xgene_edac_soc_remove(node);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue