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This pull request contains Broadcom ARM64-based SoCs Device Tree updates

Browse source 
for 6.2, please pull the following:
 
 - Rafal describes the timer/watchdog block for the BCM4908 and BCM6858
   SoCs
 
 - Krzysztof corrects invalid "reg" properties for the memory nodes that
   were off by one digit
 
 - Pierre updates a number of cache Device Tree node properties to be
   schema compliant
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Merge tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt

This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.2, please pull the following:

- Rafal describes the timer/watchdog block for the BCM4908 and BCM6858
  SoCs

- Krzysztof corrects invalid "reg" properties for the memory nodes that
  were off by one digit

- Pierre updates a number of cache Device Tree node properties to be
  schema compliant

* tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: Update cache properties for broadcom
  arm64: dts: broadcom: trim addresses to 8 digits
  arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
  arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer

Link: https://lore.kernel.org/r/20221129191755.542584-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-30 17:41:56 +01:00
commit f8a9f2704a
11 changed files with 38 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
View file

@ -63,6 +63,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};
@ -283,6 +284,11 @@ twd: timer-mfd@400 {
#address-cells = <1>;
#size-cells = <1>;
timer@0 {
compatible = "brcm,bcm63138-timer";
reg = <0x0 0x28>;
};
watchdog@28 {
compatible = "brcm,bcm6345-wdt";
reg = <0x28 0x8>;

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
View file

@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
View file

@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
View file

@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
View file

@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
View file

@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

20
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
View file

@ -50,6 +50,7 @@ B53_3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};
@ -109,6 +110,25 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x62000>;
twd: timer-mfd@400 {
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
reg = <0x400 0x4c>;
ranges = <0x0 0x400 0x4c>;
#address-cells = <1>;
#size-cells = <1>;
timer@0 {
compatible = "brcm,bcm63138-timer";
reg = <0x0 0x28>;
};
watchdog@28 {
compatible = "brcm,bcm6345-wdt";
reg = <0x28 0x8>;
};
};
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;

2
arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
View file

@ -52,7 +52,7 @@ chosen {
memory {
device_type = "memory";
reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
};

2
arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
View file

@ -49,7 +49,7 @@ chosen {
memory {
device_type = "memory";
reg = <0x000000000 0x80000000 0x00000001 0x00000000>;
reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
};
};

1
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View file

@ -79,6 +79,7 @@ A57_3: cpu@3 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
cache-level = <2>;
};
};

4
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View file

@ -108,18 +108,22 @@ cpu@301 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
cache-level = <2>;
};
};