eeprom: at25: Add DT support for EEPROMs with odd address bits

Certain EEPROMS have a size that is larger than the number of address
bytes would allow, and store the MSB of the address in bit 3 of the
instruction byte.

This can be described in platform data using EE_INSTR_BIT3_IS_ADDR, or
in DT using the obsolete legacy "at25,addr-mode" property.
But currently there exists no non-deprecated way to describe this in DT.

Hence extend the existing "address-width" DT property to allow
specifying 9 address bits, and enable support for that in the driver.

This has been tested with a Microchip 25LC040A.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Geert Uytterhoeven 2017-12-08 14:46:41 +01:00 committed by Greg Kroah-Hartman
parent eb90826bab
commit f8d3bc1004
2 changed files with 6 additions and 1 deletions

View File

@ -11,7 +11,9 @@ Required properties:
- spi-max-frequency : max spi frequency to use
- pagesize : size of the eeprom page
- size : total eeprom size in bytes
- address-width : number of address bits (one of 8, 16, or 24)
- address-width : number of address bits (one of 8, 9, 16, or 24).
For 9 bits, the MSB of the address is sent as bit 3 of the instruction
byte, before the address byte.
Optional properties:
- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.

View File

@ -276,6 +276,9 @@ static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
return -ENODEV;
}
switch (val) {
case 9:
chip->flags |= EE_INSTR_BIT3_IS_ADDR;
/* fall through */
case 8:
chip->flags |= EE_ADDR1;
break;