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drm/amdgpu: update tile table for oland/hainan
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
This commit is contained in:
parent
3548f9a829
commit
f8d9422ef8
1 changed files with 192 additions and 140 deletions
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@ -708,238 +708,290 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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switch (reg_offset) {
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case 0:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 1:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 2:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 3:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK) |
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TILE_SPLIT(split_equal_to_row_size));
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break;
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case 4:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2));
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 6:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 7:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_4_BANK));
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break;
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case 8:
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gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2));
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break;
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case 10:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 11:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 12:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2));
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break;
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case 14:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 15:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 16:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK));
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break;
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case 17:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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TILE_SPLIT(split_equal_to_row_size));
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break;
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case 18:
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P2));
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break;
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case 19:
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gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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||||
TILE_SPLIT(split_equal_to_row_size));
|
||||
break;
|
||||
case 20:
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
|
||||
NUM_BANKS(ADDR_SURF_16_BANK) |
|
||||
TILE_SPLIT(split_equal_to_row_size));
|
||||
break;
|
||||
case 21:
|
||||
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
|
||||
NUM_BANKS(ADDR_SURF_16_BANK) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_8_BANK));
|
||||
break;
|
||||
case 22:
|
||||
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
|
||||
NUM_BANKS(ADDR_SURF_16_BANK) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_8_BANK));
|
||||
break;
|
||||
case 23:
|
||||
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
|
||||
NUM_BANKS(ADDR_SURF_16_BANK) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_8_BANK));
|
||||
break;
|
||||
case 24:
|
||||
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
|
||||
NUM_BANKS(ADDR_SURF_16_BANK) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_8_BANK));
|
||||
break;
|
||||
case 25:
|
||||
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
|
||||
NUM_BANKS(ADDR_SURF_8_BANK) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_4_BANK));
|
||||
break;
|
||||
case 26:
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_4_BANK));
|
||||
break;
|
||||
case 27:
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_4_BANK));
|
||||
break;
|
||||
case 28:
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_4_BANK));
|
||||
break;
|
||||
case 29:
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_4_BANK));
|
||||
break;
|
||||
case 30:
|
||||
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
|
||||
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||
PIPE_CONFIG(ADDR_SURF_P2) |
|
||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
|
||||
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
|
||||
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
|
||||
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
|
||||
NUM_BANKS(ADDR_SURF_4_BANK));
|
||||
break;
|
||||
default:
|
||||
gb_tile_moden = 0;
|
||||
break;
|
||||
continue;
|
||||
}
|
||||
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
|
||||
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
|
||||
|
|
Loading…
Reference in a new issue