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Update peci-next for v6.6-rc1 

* Add Intel Sapphire Rapids support.
 * Add Nuvoton controller driver.
 -----BEGIN PGP SIGNATURE-----
 
 iQJOBAABCAA4FiEEVeIYQcCloMPRsCC93RgStozwYHYFAmTRcpMaHGl3b25hLndp
 bmlhcnNrYUBpbnRlbC5jb20ACgkQ3RgStozwYHa/mg/7Bhm/+rOfN3F6yYIVZtAk
 kc+VskI4H20wmr76D5mx5lzOlhbXQZIN2J2G8dhOJVVVJa+9OzS5Gw5LsVeLZTaf
 PYZxmkn20hidIz6ULH+CmeN1+JcwSrnbOWzXO/BJbfp9QRbxX2qINB5yi8TgRB9T
 rJSxzxb98aFXAtZJ1jqJSDGN2LZDmr5M7weFN6k9jMT+x0xivqAny6lKeJdjaMye
 /IwMWKWzLObUFvgpWsIVAY/RZWIg+vy6JqREu1RdA7HAALco2f0HpE96tkXLv+g0
 QiAXzWErcmBsQiN04EX+g+J24tpwuyA8TuDZYg49duX9I8BmI0ydIO/9PRtM3H9J
 4wd5EI3vWmH/3gERSHg7QAj9EplJyexWv33gZo0DerglxikfpNryZPhPz+6GEUPr
 r16oFu+kY/kSaGTcZaQ9Jsvtv/dZWZm+8oDVHNNX5VWH0ZUC8JbPK7PgBovvzAYq
 KwbyvqVYhzVMBDk0oWP/cEcWhEwA8Q2/v63dE2+ExVcfimHPai0PBwF5sgUyir3p
 ud9fzjLZUWRumASlRzZNZa3EztP2wuWO/GAo0lJdGDvylX5y8Ms5upwr8RKKhCBi
 F3ceO0S5Ff4zqKjBvKrhBgzyyFkU6ARoEXhoSVAvr8yAOyxMd+HE+Ci08fx6GvKv
 VGL4cvD6E5dzbgoOanZk09o=
 =KO5M
 -----END PGP SIGNATURE-----

Merge tag 'peci-next-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/iwi/linux into char-misc-next

Iwona writes:

Update peci-next for v6.6-rc1

* Add Intel Sapphire Rapids support.
* Add Nuvoton controller driver.

* tag 'peci-next-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/iwi/linux:
  arm64: dts: nuvoton: Add PECI controller node
  ARM: dts: nuvoton: Add PECI controller node
  peci: Add peci-npcm controller driver
  dt-bindings: Add bindings for peci-npcm
  hwmon: (peci/dimmtemp) Add Sapphire Rapids support
  hwmon: (peci/cputemp) Add Intel Sapphire Rapids support
  peci: cpu: Add Intel Sapphire Rapids support
This commit is contained in:
Greg Kroah-Hartman 2023-08-08 10:53:30 +02:00
parent abe8ff435f d7c99890fe
commit f90bebb36a
9 changed files with 462 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
Documentation/devicetree/bindings/peci/nuvoton,npcm-peci.yaml Normal file
View File

@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/peci/nuvoton,npcm-peci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton PECI Bus
maintainers:
- Tomer Maimon <tmaimon77@gmail.com>
allOf:
- $ref: peci-controller.yaml#
properties:
compatible:
enum:
- nuvoton,npcm750-peci
- nuvoton,npcm845-peci
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description:
Clock source for PECI controller. Should reference the APB clock.
maxItems: 1
cmd-timeout-ms:
minimum: 1
maximum: 1000
default: 1000
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
peci-controller@f0100000 {
compatible = "nuvoton,npcm750-peci";
reg = <0xf0100000 0x200>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_APB3>;
cmd-timeout-ms = <1000>;
};
...

9
arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi
View File

@ -220,6 +220,15 @@
};
};
peci: peci-controller@f0100000 {
compatible = "nuvoton,npcm750-peci";
reg = <0xf0100000 0x200>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_APB3>;
cmd-timeout-ms = <1000>;
status = "disabled";
};
spi0: spi@200000 {
compatible = "nuvoton,npcm750-pspi";
reg = <0x200000 0x1000>;

9
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
View File

@ -68,6 +68,15 @@
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
peci: peci-controller@100000 {
compatible = "nuvoton,npcm845-peci";
reg = <0x100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_APB3>;
cmd-timeout-ms = <1000>;
status = "disabled";
};
timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

18
drivers/hwmon/peci/cputemp.c
View File

@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv)
switch (peci_dev->info.model) {
case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
reg->func, reg->offset + 4, &data);
if (ret)
@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx = {
.offset = 0xd0,
};
static struct resolved_cores_reg resolved_cores_reg_spr = {
.bus = 31,
.dev = 30,
.func = 6,
.offset = 0x80,
};
static const struct cpu_info cpu_hsx = {
.reg = &resolved_cores_reg_hsx,
.min_peci_revision = 0x33,
@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = {
.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
};
static const struct cpu_info cpu_spr = {
.reg = &resolved_cores_reg_spr,
.min_peci_revision = 0x40,
.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
};
static const struct auxiliary_device_id peci_cputemp_ids[] = {
{
.name = "peci_cpu.cputemp.hsx",
@ -574,6 +588,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = {
.name = "peci_cpu.cputemp.icxd",
.driver_data = (kernel_ulong_t)&cpu_icx,
},
{
.name = "peci_cpu.cputemp.spr",
.driver_data = (kernel_ulong_t)&cpu_spr,
},
{ }
};
MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);

50
drivers/hwmon/peci/dimmtemp.c
View File

@ -30,6 +30,8 @@
#define DIMM_IDX_MAX_ON_ICX 2
#define CHAN_RANK_MAX_ON_ICXD 4
#define DIMM_IDX_MAX_ON_ICXD 2
#define CHAN_RANK_MAX_ON_SPR 8
#define DIMM_IDX_MAX_ON_SPR 2
#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
@ -530,6 +532,43 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
return 0;
}
static int
read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
{
u32 reg_val;
u64 offset;
int ret;
u8 dev;
ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, &reg_val);
if (ret || !(reg_val & BIT(31)))
return -ENODATA; /* Use default or previous value */
ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, &reg_val);
if (ret)
return -ENODATA; /* Use default or previous value */
/*
* Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0
* Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1
* Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2
* Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3
* Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4
* Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5
* Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6
* Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7
*/
dev = 26 + chan_rank / 2;
offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000;
ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),
dev, 0, offset, data);
if (ret)
return ret;
return 0;
}
static const struct dimm_info dimm_hsx = {
.chan_rank_max = CHAN_RANK_MAX_ON_HSX,
.dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
@ -572,6 +611,13 @@ static const struct dimm_info dimm_icxd = {
.read_thresholds = &read_thresholds_icx,
};
static const struct dimm_info dimm_spr = {
.chan_rank_max = CHAN_RANK_MAX_ON_SPR,
.dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
.min_peci_revision = 0x40,
.read_thresholds = &read_thresholds_spr,
};
static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
{
.name = "peci_cpu.dimmtemp.hsx",
@ -597,6 +643,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
.name = "peci_cpu.dimmtemp.icxd",
.driver_data = (kernel_ulong_t)&dimm_icxd,
},
{
.name = "peci_cpu.dimmtemp.spr",
.driver_data = (kernel_ulong_t)&dimm_spr,
},
{ }
};
MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);

16
drivers/peci/controller/Kconfig
View File

@ -16,3 +16,19 @@ config PECI_ASPEED
This driver can also be built as a module. If so, the module will
be called peci-aspeed.
config PECI_NPCM
tristate "Nuvoton NPCM PECI support"
depends on ARCH_NPCM || COMPILE_TEST
depends on OF
select REGMAP_MMIO
help
This option enables PECI controller driver for Nuvoton NPCM7XX
and NPCM8XX SoCs. It allows BMC to discover devices connected
to it and communicate with them using PECI protocol.
Say Y here if you want support for the Platform Environment Control
Interface (PECI) bus adapter driver on the Nuvoton NPCM SoCs.
This support is also available as a module. If so, the module
will be called peci-npcm.

1
drivers/peci/controller/Makefile
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o
obj-$(CONFIG_PECI_NPCM) += peci-npcm.o

298
drivers/peci/controller/peci-npcm.c Normal file
View File

@ -0,0 +1,298 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019 Nuvoton Technology corporation
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/peci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
/* NPCM GCR module */
#define NPCM_INTCR3_OFFSET 0x9C
#define NPCM_INTCR3_PECIVSEL BIT(19)
/* NPCM PECI Registers */
#define NPCM_PECI_CTL_STS 0x00
#define NPCM_PECI_RD_LENGTH 0x04
#define NPCM_PECI_ADDR 0x08
#define NPCM_PECI_CMD 0x0C
#define NPCM_PECI_CTL2 0x10
#define NPCM_PECI_WR_LENGTH 0x1C
#define NPCM_PECI_PDDR 0x2C
#define NPCM_PECI_DAT_INOUT(n) (0x100 + ((n) * 4))
#define NPCM_PECI_MAX_REG 0x200
/* NPCM_PECI_CTL_STS - 0x00 : Control Register */
#define NPCM_PECI_CTRL_DONE_INT_EN BIT(6)
#define NPCM_PECI_CTRL_ABRT_ERR BIT(4)
#define NPCM_PECI_CTRL_CRC_ERR BIT(3)
#define NPCM_PECI_CTRL_DONE BIT(1)
#define NPCM_PECI_CTRL_START_BUSY BIT(0)
/* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */
#define NPCM_PECI_RD_LEN_MASK GENMASK(6, 0)
/* NPCM_PECI_CMD - 0x10 : Command Register */
#define NPCM_PECI_CTL2_MASK GENMASK(7, 6)
/* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */
#define NPCM_PECI_WR_LEN_MASK GENMASK(6, 0)
/* NPCM_PECI_PDDR - 0x2C : Command Register */
#define NPCM_PECI_PDDR_MASK GENMASK(4, 0)
#define NPCM_PECI_INT_MASK (NPCM_PECI_CTRL_ABRT_ERR | \
NPCM_PECI_CTRL_CRC_ERR | \
NPCM_PECI_CTRL_DONE)
#define NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC (50 * USEC_PER_MSEC)
#define NPCM_PECI_IDLE_CHECK_INTERVAL_USEC (10 * USEC_PER_MSEC)
#define NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT 1000
#define NPCM_PECI_CMD_TIMEOUT_MS_MAX 60000
#define NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT 15
#define NPCM_PECI_PULL_DOWN_DEFAULT 0
struct npcm_peci {
u32 cmd_timeout_ms;
struct completion xfer_complete;
struct regmap *regmap;
u32 status;
spinlock_t lock; /* to sync completion status handling */
struct peci_controller *controller;
struct device *dev;
struct clk *clk;
int irq;
};
static int npcm_peci_xfer(struct peci_controller *controller, u8 addr, struct peci_request *req)
{
struct npcm_peci *priv = dev_get_drvdata(controller->dev.parent);
unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms);
unsigned int msg_rd;
u32 cmd_sts;
int i, ret;
/* Check command sts and bus idle state */
ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts,
!(cmd_sts & NPCM_PECI_CTRL_START_BUSY),
NPCM_PECI_IDLE_CHECK_INTERVAL_USEC,
NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC);
if (ret)
return ret; /* -ETIMEDOUT */
spin_lock_irq(&priv->lock);
reinit_completion(&priv->xfer_complete);
regmap_write(priv->regmap, NPCM_PECI_ADDR, addr);
regmap_write(priv->regmap, NPCM_PECI_RD_LENGTH, NPCM_PECI_WR_LEN_MASK & req->rx.len);
regmap_write(priv->regmap, NPCM_PECI_WR_LENGTH, NPCM_PECI_WR_LEN_MASK & req->tx.len);
if (req->tx.len) {
regmap_write(priv->regmap, NPCM_PECI_CMD, req->tx.buf[0]);
for (i = 0; i < (req->tx.len - 1); i++)
regmap_write(priv->regmap, NPCM_PECI_DAT_INOUT(i), req->tx.buf[i + 1]);
}
#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
dev_dbg(priv->dev, "addr : %#02x, tx.len : %#02x, rx.len : %#02x\n",
addr, req->tx.len, req->rx.len);
print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req->tx.len);
#endif
priv->status = 0;
regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_START_BUSY,
NPCM_PECI_CTRL_START_BUSY);
spin_unlock_irq(&priv->lock);
ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete, timeout);
if (ret < 0)
return ret;
if (ret == 0) {
dev_dbg(priv->dev, "timeout waiting for a response\n");
return -ETIMEDOUT;
}
spin_lock_irq(&priv->lock);
if (priv->status != NPCM_PECI_CTRL_DONE) {
spin_unlock_irq(&priv->lock);
dev_dbg(priv->dev, "no valid response, status: %#02x\n", priv->status);
return -EIO;
}
regmap_write(priv->regmap, NPCM_PECI_CMD, 0);
for (i = 0; i < req->rx.len; i++) {
regmap_read(priv->regmap, NPCM_PECI_DAT_INOUT(i), &msg_rd);
req->rx.buf[i] = (u8)msg_rd;
}
spin_unlock_irq(&priv->lock);
#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req->rx.len);
#endif
return 0;
}
static irqreturn_t npcm_peci_irq_handler(int irq, void *arg)
{
struct npcm_peci *priv = arg;
u32 status_ack = 0;
u32 status;
spin_lock(&priv->lock);
regmap_read(priv->regmap, NPCM_PECI_CTL_STS, &status);
priv->status |= (status & NPCM_PECI_INT_MASK);
if (status & NPCM_PECI_CTRL_CRC_ERR)
status_ack |= NPCM_PECI_CTRL_CRC_ERR;
if (status & NPCM_PECI_CTRL_ABRT_ERR)
status_ack |= NPCM_PECI_CTRL_ABRT_ERR;
/*
* All commands should be ended up with a NPCM_PECI_CTRL_DONE
* bit set even in an error case.
*/
if (status & NPCM_PECI_CTRL_DONE) {
status_ack |= NPCM_PECI_CTRL_DONE;
complete(&priv->xfer_complete);
}
regmap_write_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_INT_MASK, status_ack);
spin_unlock(&priv->lock);
return IRQ_HANDLED;
}
static int npcm_peci_init_ctrl(struct npcm_peci *priv)
{
u32 cmd_sts;
int ret;
priv->clk = devm_clk_get_enabled(priv->dev, NULL);
if (IS_ERR(priv->clk)) {
dev_err(priv->dev, "failed to get ref clock\n");
return PTR_ERR(priv->clk);
}
ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", &priv->cmd_timeout_ms);
if (ret) {
priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT;
} else if (priv->cmd_timeout_ms > NPCM_PECI_CMD_TIMEOUT_MS_MAX ||
priv->cmd_timeout_ms == 0) {
dev_warn(priv->dev, "invalid cmd-timeout-ms: %u, falling back to: %u\n",
priv->cmd_timeout_ms, NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT);
priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT;
}
regmap_update_bits(priv->regmap, NPCM_PECI_CTL2, NPCM_PECI_CTL2_MASK,
NPCM_PECI_PULL_DOWN_DEFAULT << 6);
regmap_update_bits(priv->regmap, NPCM_PECI_PDDR, NPCM_PECI_PDDR_MASK,
NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT);
ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts,
!(cmd_sts & NPCM_PECI_CTRL_START_BUSY),
NPCM_PECI_IDLE_CHECK_INTERVAL_USEC,
NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC);
if (ret)
return ret; /* -ETIMEDOUT */
/* PECI interrupt enable */
regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_DONE_INT_EN,
NPCM_PECI_CTRL_DONE_INT_EN);
return 0;
}
static const struct regmap_config npcm_peci_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = NPCM_PECI_MAX_REG,
.fast_io = true,
};
static struct peci_controller_ops npcm_ops = {
.xfer = npcm_peci_xfer,
};
static int npcm_peci_probe(struct platform_device *pdev)
{
struct peci_controller *controller;
struct npcm_peci *priv;
void __iomem *base;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, priv);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &npcm_peci_regmap_config);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
priv->irq = platform_get_irq(pdev, 0);
if (priv->irq < 0)
return priv->irq;
ret = devm_request_irq(&pdev->dev, priv->irq, npcm_peci_irq_handler,
0, "peci-npcm-irq", priv);
if (ret)
return ret;
init_completion(&priv->xfer_complete);
spin_lock_init(&priv->lock);
ret = npcm_peci_init_ctrl(priv);
if (ret)
return ret;
controller = devm_peci_controller_add(priv->dev, &npcm_ops);
if (IS_ERR(controller))
return dev_err_probe(priv->dev, PTR_ERR(controller),
"failed to add npcm peci controller\n");
priv->controller = controller;
return 0;
}
static const struct of_device_id npcm_peci_of_table[] = {
{ .compatible = "nuvoton,npcm750-peci", },
{ .compatible = "nuvoton,npcm845-peci", },
{ }
};
MODULE_DEVICE_TABLE(of, npcm_peci_of_table);
static struct platform_driver npcm_peci_driver = {
.probe = npcm_peci_probe,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = npcm_peci_of_table,
},
};
module_platform_driver(npcm_peci_driver);
MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
MODULE_DESCRIPTION("NPCM PECI driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(PECI);

5
drivers/peci/cpu.c
View File

@ -323,6 +323,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = {
.model = INTEL_FAM6_ICELAKE_D,
.data = "icxd",
},
{ /* Sapphire Rapids Xeon */
.family = 6,
.model = INTEL_FAM6_SAPPHIRERAPIDS_X,
.data = "spr",
},
{ }
};
MODULE_DEVICE_TABLE(peci, peci_cpu_device_ids);