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ath9k: split ar5008_hw_spur_mitigate and reuse common code in ar9002_hw_spur_mitigate.
[ar5008 and ar9002]_hw_spur_mitigate have big portion of identical code. This patch will move common part of ar5008_hw_spur_mitigate to ar5008_hw_cmn_spur_mitigate and reuse it in ar9002_hw_spur_mitigate. As noticed by Joe Perches I reuse ar9002_hw_spur_mitigate (const) version of declarations for pilot_mask_reg and chan_mask_reg. There should be no other difference with original code. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Oleksij Rempel
Kalle Valo
parent
1277fa2ab2
commit
f911085ffa
3 changed files with 89 additions and 216 deletions
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@ -254,86 +254,25 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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return 0;
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}
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/**
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* ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
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* @ah: atheros hardware structure
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* @chan:
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*
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* For non single-chip solutions. Converts to baseband spur frequency given the
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* input channel frequency and compute register settings below.
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*/
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static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
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struct ath9k_channel *chan)
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void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
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struct ath9k_channel *chan, int bin)
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{
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int bb_spur = AR_NO_SPUR;
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int bin, cur_bin;
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int spur_freq_sd;
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int spur_delta_phase;
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int denominator;
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int cur_bin;
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int upper, lower, cur_vit_mask;
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int tmp, new;
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int i;
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static int pilot_mask_reg[4] = {
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AR_PHY_TIMING7, AR_PHY_TIMING8,
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
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};
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static int chan_mask_reg[4] = {
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AR_PHY_TIMING9, AR_PHY_TIMING10,
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AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
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};
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static int inc[4] = { 0, 100, 0, 0 };
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int8_t mask_m[123];
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int8_t mask_p[123];
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int8_t mask_amt;
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int tmp_mask;
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int cur_bb_spur;
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bool is2GHz = IS_CHAN_2GHZ(chan);
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memset(&mask_m, 0, sizeof(int8_t) * 123);
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memset(&mask_p, 0, sizeof(int8_t) * 123);
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for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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if (AR_NO_SPUR == cur_bb_spur)
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break;
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cur_bb_spur = cur_bb_spur - (chan->channel * 10);
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if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
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bb_spur = cur_bb_spur;
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break;
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}
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}
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if (AR_NO_SPUR == bb_spur)
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return;
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bin = bb_spur * 32;
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tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
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new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
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AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
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AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
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AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
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new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
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AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
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AR_PHY_SPUR_REG_MASK_RATE_SELECT |
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AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
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SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
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REG_WRITE(ah, AR_PHY_SPUR_REG, new);
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spur_delta_phase = ((bb_spur * 524288) / 100) &
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AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
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spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
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new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
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SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
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SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
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REG_WRITE(ah, AR_PHY_TIMING11, new);
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static const int pilot_mask_reg[4] = {
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AR_PHY_TIMING7, AR_PHY_TIMING8,
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
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};
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static const int chan_mask_reg[4] = {
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AR_PHY_TIMING9, AR_PHY_TIMING10,
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AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
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};
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static const int inc[4] = { 0, 100, 0, 0 };
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cur_bin = -6000;
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upper = bin + 100;
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@ -343,6 +282,7 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
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int pilot_mask = 0;
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int chan_mask = 0;
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int bp = 0;
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for (bp = 0; bp < 30; bp++) {
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if ((cur_bin > lower) && (cur_bin < upper)) {
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pilot_mask = pilot_mask | 0x1 << bp;
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@ -361,7 +301,6 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
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for (i = 0; i < 123; i++) {
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if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
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/* workaround for gcc bug #37014 */
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volatile int tmp_v = abs(cur_vit_mask - bin);
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@ -466,6 +405,78 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
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REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
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}
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/**
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* ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
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* @ah: atheros hardware structure
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* @chan:
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*
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* For non single-chip solutions. Converts to baseband spur frequency given the
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* input channel frequency and compute register settings below.
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*/
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static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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int bb_spur = AR_NO_SPUR;
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int bin;
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int spur_freq_sd;
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int spur_delta_phase;
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int denominator;
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int tmp, new;
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int i;
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int8_t mask_m[123];
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int8_t mask_p[123];
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int cur_bb_spur;
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bool is2GHz = IS_CHAN_2GHZ(chan);
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memset(&mask_m, 0, sizeof(int8_t) * 123);
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memset(&mask_p, 0, sizeof(int8_t) * 123);
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for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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if (AR_NO_SPUR == cur_bb_spur)
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break;
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cur_bb_spur = cur_bb_spur - (chan->channel * 10);
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if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
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bb_spur = cur_bb_spur;
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break;
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}
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}
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if (AR_NO_SPUR == bb_spur)
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return;
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bin = bb_spur * 32;
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tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
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new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
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AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
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AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
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AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
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new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
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AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
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AR_PHY_SPUR_REG_MASK_RATE_SELECT |
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AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
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SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
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REG_WRITE(ah, AR_PHY_SPUR_REG, new);
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spur_delta_phase = ((bb_spur * 524288) / 100) &
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AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
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spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
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new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
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SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
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SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
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REG_WRITE(ah, AR_PHY_TIMING11, new);
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ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
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}
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/**
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* ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
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* @ah: atheros hardware structure
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@ -169,29 +169,17 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
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{
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int bb_spur = AR_NO_SPUR;
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int freq;
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int bin, cur_bin;
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int bin;
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int bb_spur_off, spur_subchannel_sd;
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int spur_freq_sd;
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int spur_delta_phase;
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int denominator;
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int upper, lower, cur_vit_mask;
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int tmp, newVal;
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int i;
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static const int pilot_mask_reg[4] = {
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AR_PHY_TIMING7, AR_PHY_TIMING8,
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
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};
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static const int chan_mask_reg[4] = {
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AR_PHY_TIMING9, AR_PHY_TIMING10,
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AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
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};
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static const int inc[4] = { 0, 100, 0, 0 };
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struct chan_centers centers;
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int8_t mask_m[123];
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int8_t mask_p[123];
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int8_t mask_amt;
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int tmp_mask;
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int cur_bb_spur;
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bool is2GHz = IS_CHAN_2GHZ(chan);
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@ -288,135 +276,7 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
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newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
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REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
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cur_bin = -6000;
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upper = bin + 100;
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lower = bin - 100;
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for (i = 0; i < 4; i++) {
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int pilot_mask = 0;
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int chan_mask = 0;
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int bp = 0;
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for (bp = 0; bp < 30; bp++) {
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if ((cur_bin > lower) && (cur_bin < upper)) {
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pilot_mask = pilot_mask | 0x1 << bp;
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chan_mask = chan_mask | 0x1 << bp;
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}
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cur_bin += 100;
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}
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cur_bin += inc[i];
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REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
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REG_WRITE(ah, chan_mask_reg[i], chan_mask);
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}
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cur_vit_mask = 6100;
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upper = bin + 120;
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lower = bin - 120;
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for (i = 0; i < 123; i++) {
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if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
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/* workaround for gcc bug #37014 */
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volatile int tmp_v = abs(cur_vit_mask - bin);
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if (tmp_v < 75)
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mask_amt = 1;
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else
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mask_amt = 0;
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if (cur_vit_mask < 0)
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mask_m[abs(cur_vit_mask / 100)] = mask_amt;
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else
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mask_p[cur_vit_mask / 100] = mask_amt;
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}
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cur_vit_mask -= 100;
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}
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tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
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| (mask_m[48] << 26) | (mask_m[49] << 24)
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| (mask_m[50] << 22) | (mask_m[51] << 20)
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| (mask_m[52] << 18) | (mask_m[53] << 16)
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| (mask_m[54] << 14) | (mask_m[55] << 12)
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| (mask_m[56] << 10) | (mask_m[57] << 8)
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| (mask_m[58] << 6) | (mask_m[59] << 4)
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| (mask_m[60] << 2) | (mask_m[61] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
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REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
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tmp_mask = (mask_m[31] << 28)
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| (mask_m[32] << 26) | (mask_m[33] << 24)
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| (mask_m[34] << 22) | (mask_m[35] << 20)
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| (mask_m[36] << 18) | (mask_m[37] << 16)
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| (mask_m[48] << 14) | (mask_m[39] << 12)
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| (mask_m[40] << 10) | (mask_m[41] << 8)
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| (mask_m[42] << 6) | (mask_m[43] << 4)
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| (mask_m[44] << 2) | (mask_m[45] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
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tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
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| (mask_m[18] << 26) | (mask_m[18] << 24)
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| (mask_m[20] << 22) | (mask_m[20] << 20)
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| (mask_m[22] << 18) | (mask_m[22] << 16)
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| (mask_m[24] << 14) | (mask_m[24] << 12)
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| (mask_m[25] << 10) | (mask_m[26] << 8)
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| (mask_m[27] << 6) | (mask_m[28] << 4)
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| (mask_m[29] << 2) | (mask_m[30] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
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tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
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| (mask_m[2] << 26) | (mask_m[3] << 24)
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| (mask_m[4] << 22) | (mask_m[5] << 20)
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| (mask_m[6] << 18) | (mask_m[7] << 16)
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| (mask_m[8] << 14) | (mask_m[9] << 12)
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| (mask_m[10] << 10) | (mask_m[11] << 8)
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| (mask_m[12] << 6) | (mask_m[13] << 4)
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| (mask_m[14] << 2) | (mask_m[15] << 0);
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REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
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tmp_mask = (mask_p[15] << 28)
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| (mask_p[14] << 26) | (mask_p[13] << 24)
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| (mask_p[12] << 22) | (mask_p[11] << 20)
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| (mask_p[10] << 18) | (mask_p[9] << 16)
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| (mask_p[8] << 14) | (mask_p[7] << 12)
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| (mask_p[6] << 10) | (mask_p[5] << 8)
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| (mask_p[4] << 6) | (mask_p[3] << 4)
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| (mask_p[2] << 2) | (mask_p[1] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
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tmp_mask = (mask_p[30] << 28)
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| (mask_p[29] << 26) | (mask_p[28] << 24)
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| (mask_p[27] << 22) | (mask_p[26] << 20)
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| (mask_p[25] << 18) | (mask_p[24] << 16)
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| (mask_p[23] << 14) | (mask_p[22] << 12)
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| (mask_p[21] << 10) | (mask_p[20] << 8)
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| (mask_p[19] << 6) | (mask_p[18] << 4)
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| (mask_p[17] << 2) | (mask_p[16] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
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tmp_mask = (mask_p[45] << 28)
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| (mask_p[44] << 26) | (mask_p[43] << 24)
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| (mask_p[42] << 22) | (mask_p[41] << 20)
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| (mask_p[40] << 18) | (mask_p[39] << 16)
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| (mask_p[38] << 14) | (mask_p[37] << 12)
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| (mask_p[36] << 10) | (mask_p[35] << 8)
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| (mask_p[34] << 6) | (mask_p[33] << 4)
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| (mask_p[32] << 2) | (mask_p[31] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
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tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
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| (mask_p[59] << 26) | (mask_p[58] << 24)
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| (mask_p[57] << 22) | (mask_p[56] << 20)
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| (mask_p[55] << 18) | (mask_p[54] << 16)
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| (mask_p[53] << 14) | (mask_p[52] << 12)
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| (mask_p[51] << 10) | (mask_p[50] << 8)
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| (mask_p[49] << 6) | (mask_p[48] << 4)
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| (mask_p[47] << 2) | (mask_p[46] << 0);
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REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
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REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
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ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
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|
||||
REGWRITE_BUFFER_FLUSH(ah);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1119,6 +1119,8 @@ bool ar9003_is_paprd_enabled(struct ath_hw *ah);
|
|||
void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
|
||||
void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
|
||||
struct ath9k_channel *chan);
|
||||
void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan, int bin);
|
||||
void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
|
||||
struct ath9k_channel *chan, int ht40_delta);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue