mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 01:41:39 +00:00
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says:
====================
Intel Wired LAN Driver Updates 2015-05-04
This series contains updates to igb, e100, e1000e and ixgbe.
Todd cleans up igb_enable_mas() since it should only be called for the
82575 silicon and has no clear return, so modify the function to void.
Jean Sacren found upon inspection that 'err' did not need to be
initialized, since it is immediately overwritten.
Alex Duyck provides two patches for e1000e, the first cleans up the
handling VLAN_HLEN as a part of max frame size. Fixes the issue:
c751a3d58c
("e1000e: Correctly include VLAN_HLEN when changing
interface MTU"). The second fixes an issue where the driver was not
allowing jumbo frames to be enabled when CRC stripping was disabled,
however it was allowing CRC stripping to be disabled while jumbo frames
were enabled.
Jeff (me) fixes a warning found on PPC where the use of do_div() needed
to use u64 arg and not s64.
Mark provides three ixgbe patches, first to fix the Intel On-chip System
Fabric (IOSF) Sideband message interfaces, to serialize access using both
PHY bits in the SWFW_SEMAPHORE register. Then fixes how semaphore bits
were released, since they should be released in reverse of the order that
they were taken. Lastly updates ixgbe to use a signed type to hold
error codes, since error codes are negative, so consistently use signed
types when handling them.
v2: dropped the previous #6-#8 patches by Hiroshi Shimanoto based on
feedback from Or Gerlitz (and David Miller) that it appears there
needs to be further discussion on how this gets implemented.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
f9161585b2
10 changed files with 123 additions and 95 deletions
|
@ -874,7 +874,7 @@ static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
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{
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struct cb *cb;
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unsigned long flags;
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int err = 0;
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int err;
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spin_lock_irqsave(&nic->cb_lock, flags);
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|
|
|
@ -2010,7 +2010,7 @@ const struct e1000_info e1000_82573_info = {
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.flags2 = FLAG2_DISABLE_ASPM_L1
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| FLAG2_DISABLE_ASPM_L0S,
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.pba = 20,
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.max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
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.max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
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.get_variants = e1000_get_variants_82571,
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.mac_ops = &e82571_mac_ops,
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.phy_ops = &e82_phy_ops_m88,
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|
|
|
@ -1015,7 +1015,7 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
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u16 max_snoop, max_nosnoop;
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u16 max_ltr_enc; /* max LTR latency encoded */
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s64 lat_ns; /* latency (ns) */
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s64 value;
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u64 value;
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u32 rxa;
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if (!hw->adapter->max_frame_size) {
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@ -1042,12 +1042,13 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
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*/
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lat_ns = ((s64)rxa * 1024 -
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(2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
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if (lat_ns < 0)
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lat_ns = 0;
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else
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do_div(lat_ns, speed);
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if (lat_ns < 0) {
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value = 0;
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} else {
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value = lat_ns;
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do_div(value, speed);
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}
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value = lat_ns;
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while (value > PCI_LTR_VALUE_MASK) {
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scale++;
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value = DIV_ROUND_UP(value, (1 << 5));
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|
@ -1563,7 +1564,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
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((adapter->hw.mac.type >= e1000_pch2lan) &&
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(!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
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adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
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adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
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adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
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hw->mac.ops.blink_led = NULL;
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}
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|
@ -5681,7 +5682,7 @@ const struct e1000_info e1000_ich8_info = {
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| FLAG_HAS_FLASH
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| FLAG_APME_IN_WUC,
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.pba = 8,
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.max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
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.max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
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.get_variants = e1000_get_variants_ich8lan,
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.mac_ops = &ich8_mac_ops,
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.phy_ops = &ich8_phy_ops,
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|
@ -5754,7 +5755,7 @@ const struct e1000_info e1000_pch2_info = {
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.flags2 = FLAG2_HAS_PHY_STATS
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| FLAG2_HAS_EEE,
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.pba = 26,
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.max_hw_frame_size = 9018,
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.max_hw_frame_size = 9022,
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.get_variants = e1000_get_variants_ich8lan,
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.mac_ops = &ich8_mac_ops,
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.phy_ops = &ich8_phy_ops,
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|
@ -5774,7 +5775,7 @@ const struct e1000_info e1000_pch_lpt_info = {
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.flags2 = FLAG2_HAS_PHY_STATS
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| FLAG2_HAS_EEE,
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.pba = 26,
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.max_hw_frame_size = 9018,
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.max_hw_frame_size = 9022,
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.get_variants = e1000_get_variants_ich8lan,
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.mac_ops = &ich8_mac_ops,
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.phy_ops = &ich8_phy_ops,
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|
@ -5794,7 +5795,7 @@ const struct e1000_info e1000_pch_spt_info = {
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.flags2 = FLAG2_HAS_PHY_STATS
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| FLAG2_HAS_EEE,
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.pba = 26,
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.max_hw_frame_size = 9018,
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.max_hw_frame_size = 9022,
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.get_variants = e1000_get_variants_ich8lan,
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.mac_ops = &ich8_mac_ops,
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.phy_ops = &ich8_phy_ops,
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|
|
|
@ -3807,7 +3807,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
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/* reset Packet Buffer Allocation to default */
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ew32(PBA, pba);
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if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
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if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
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/* To maintain wire speed transmits, the Tx FIFO should be
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* large enough to accommodate two full transmit packets,
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* rounded up to the next 1KB and expressed in KB. Likewise,
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|
@ -4196,9 +4196,9 @@ static int e1000_sw_init(struct e1000_adapter *adapter)
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{
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struct net_device *netdev = adapter->netdev;
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adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
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adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
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adapter->rx_ps_bsize0 = 128;
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adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
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adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
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adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
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adapter->tx_ring_count = E1000_DEFAULT_TXD;
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adapter->rx_ring_count = E1000_DEFAULT_RXD;
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|
@ -5781,17 +5781,17 @@ struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
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static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
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{
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struct e1000_adapter *adapter = netdev_priv(netdev);
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int max_frame = new_mtu + VLAN_HLEN + ETH_HLEN + ETH_FCS_LEN;
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int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
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/* Jumbo frame support */
|
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if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
|
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if ((max_frame > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) &&
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!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
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e_err("Jumbo Frames not supported.\n");
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return -EINVAL;
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}
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/* Supported frame sizes */
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if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
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if ((new_mtu < (VLAN_ETH_ZLEN + ETH_FCS_LEN)) ||
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(max_frame > adapter->max_hw_frame_size)) {
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e_err("Unsupported MTU setting\n");
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return -EINVAL;
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|
@ -5831,10 +5831,8 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
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adapter->rx_buffer_len = 4096;
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/* adjust allocation if LPE protects us, and we aren't using SBP */
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if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
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(max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
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adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
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+ ETH_FCS_LEN;
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if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
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adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
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if (netif_running(netdev))
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e1000e_up(adapter);
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@ -6678,6 +6676,19 @@ static void e1000_eeprom_checks(struct e1000_adapter *adapter)
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}
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}
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static netdev_features_t e1000_fix_features(struct net_device *netdev,
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netdev_features_t features)
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{
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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/* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
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if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
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features &= ~NETIF_F_RXFCS;
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return features;
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}
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static int e1000_set_features(struct net_device *netdev,
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netdev_features_t features)
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{
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@ -6734,6 +6745,7 @@ static const struct net_device_ops e1000e_netdev_ops = {
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.ndo_poll_controller = e1000_netpoll,
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#endif
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.ndo_set_features = e1000_set_features,
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.ndo_fix_features = e1000_fix_features,
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};
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/**
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|
|
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@ -1834,31 +1834,19 @@ void igb_reinit_locked(struct igb_adapter *adapter)
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*
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* @adapter: adapter struct
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**/
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static s32 igb_enable_mas(struct igb_adapter *adapter)
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static void igb_enable_mas(struct igb_adapter *adapter)
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{
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struct e1000_hw *hw = &adapter->hw;
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u32 connsw;
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s32 ret_val = 0;
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connsw = rd32(E1000_CONNSW);
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if (!(hw->phy.media_type == e1000_media_type_copper))
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return ret_val;
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u32 connsw = rd32(E1000_CONNSW);
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/* configure for SerDes media detect */
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if (!(connsw & E1000_CONNSW_SERDESD)) {
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if ((hw->phy.media_type == e1000_media_type_copper) &&
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(!(connsw & E1000_CONNSW_SERDESD))) {
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connsw |= E1000_CONNSW_ENRGSRC;
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connsw |= E1000_CONNSW_AUTOSENSE_EN;
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wr32(E1000_CONNSW, connsw);
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wrfl();
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} else if (connsw & E1000_CONNSW_SERDESD) {
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/* already SerDes, no need to enable anything */
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return ret_val;
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} else {
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netdev_info(adapter->netdev,
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"MAS: Unable to configure feature, disabling..\n");
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adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
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}
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return ret_val;
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}
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void igb_reset(struct igb_adapter *adapter)
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|
@ -1978,10 +1966,9 @@ void igb_reset(struct igb_adapter *adapter)
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adapter->ei.get_invariants(hw);
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adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
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}
|
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if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
|
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if (igb_enable_mas(adapter))
|
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dev_err(&pdev->dev,
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"Error enabling Media Auto Sense\n");
|
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if ((mac->type == e1000_82575) &&
|
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(adapter->flags & IGB_FLAG_MAS_ENABLE)) {
|
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igb_enable_mas(adapter);
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}
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if (hw->mac.ops.init_hw(hw))
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dev_err(&pdev->dev, "Hardware Error\n");
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|
|
|
@ -3053,7 +3053,7 @@ static int ixgbe_get_module_info(struct net_device *dev,
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{
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struct ixgbe_adapter *adapter = netdev_priv(dev);
|
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struct ixgbe_hw *hw = &adapter->hw;
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u32 status;
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s32 status;
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u8 sff8472_rev, addr_mode;
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bool page_swap = false;
|
||||
|
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|
@ -3061,14 +3061,14 @@ static int ixgbe_get_module_info(struct net_device *dev,
|
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status = hw->phy.ops.read_i2c_eeprom(hw,
|
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IXGBE_SFF_SFF_8472_COMP,
|
||||
&sff8472_rev);
|
||||
if (status != 0)
|
||||
if (status)
|
||||
return -EIO;
|
||||
|
||||
/* addressing mode is not supported */
|
||||
status = hw->phy.ops.read_i2c_eeprom(hw,
|
||||
IXGBE_SFF_SFF_8472_SWAP,
|
||||
&addr_mode);
|
||||
if (status != 0)
|
||||
if (status)
|
||||
return -EIO;
|
||||
|
||||
if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
|
||||
|
@ -3095,7 +3095,7 @@ static int ixgbe_get_module_eeprom(struct net_device *dev,
|
|||
{
|
||||
struct ixgbe_adapter *adapter = netdev_priv(dev);
|
||||
struct ixgbe_hw *hw = &adapter->hw;
|
||||
u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
|
||||
s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
|
||||
u8 databyte = 0xFF;
|
||||
int i = 0;
|
||||
|
||||
|
@ -3112,7 +3112,7 @@ static int ixgbe_get_module_eeprom(struct net_device *dev,
|
|||
else
|
||||
status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
|
||||
|
||||
if (status != 0)
|
||||
if (status)
|
||||
return -EIO;
|
||||
|
||||
data[i - ee->offset] = databyte;
|
||||
|
|
|
@ -4757,7 +4757,7 @@ static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
|
|||
{
|
||||
u32 speed;
|
||||
bool autoneg, link_up = false;
|
||||
u32 ret = IXGBE_ERR_LINK_SETUP;
|
||||
int ret = IXGBE_ERR_LINK_SETUP;
|
||||
|
||||
if (hw->mac.ops.check_link)
|
||||
ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
|
||||
|
@ -8022,7 +8022,7 @@ static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
|
|||
return -EINVAL;
|
||||
|
||||
nla_for_each_nested(attr, br_spec, rem) {
|
||||
u32 status;
|
||||
int status;
|
||||
__u16 mode;
|
||||
|
||||
if (nla_type(attr) != IFLA_BRIDGE_MODE)
|
||||
|
|
|
@ -317,14 +317,14 @@ bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
|
|||
**/
|
||||
static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
|
||||
{
|
||||
u32 status;
|
||||
s32 status;
|
||||
u16 phy_id_high = 0;
|
||||
u16 phy_id_low = 0;
|
||||
|
||||
status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
|
||||
&phy_id_high);
|
||||
|
||||
if (status == 0) {
|
||||
if (!status) {
|
||||
hw->phy.id = (u32)(phy_id_high << 16);
|
||||
status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
|
||||
&phy_id_low);
|
||||
|
|
|
@ -696,14 +696,14 @@ static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
|
|||
|
||||
/* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
|
||||
|
||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
|
||||
swsm &= ~IXGBE_SWSM_SMBI;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
|
||||
|
||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
|
||||
swsm &= ~IXGBE_SWFW_REGSMP;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
|
||||
|
||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
|
||||
swsm &= ~IXGBE_SWSM_SMBI;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
|
||||
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
}
|
||||
|
||||
|
|
|
@ -103,6 +103,39 @@ static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_iosf_wait - Wait for IOSF command completion
|
||||
* @hw: pointer to hardware structure
|
||||
* @ctrl: pointer to location to receive final IOSF control value
|
||||
*
|
||||
* Return: failing status on timeout
|
||||
*
|
||||
* Note: ctrl can be NULL if the IOSF control register value is not needed
|
||||
*/
|
||||
static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
|
||||
{
|
||||
u32 i, command;
|
||||
|
||||
/* Check every 10 usec to see if the address cycle completed.
|
||||
* The SB IOSF BUSY bit will clear when the operation is
|
||||
* complete.
|
||||
*/
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
|
||||
if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
|
||||
break;
|
||||
usleep_range(10, 20);
|
||||
}
|
||||
if (ctrl)
|
||||
*ctrl = command;
|
||||
if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
|
||||
hw_dbg(hw, "IOSF wait timed out\n");
|
||||
return IXGBE_ERR_PHY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
|
||||
* IOSF device
|
||||
* @hw: pointer to hardware structure
|
||||
|
@ -113,7 +146,17 @@ static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
|
|||
static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
u32 device_type, u32 *data)
|
||||
{
|
||||
u32 i, command, error;
|
||||
u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
|
||||
u32 command, error;
|
||||
s32 ret;
|
||||
|
||||
ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ixgbe_iosf_wait(hw, NULL);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
|
||||
(device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
|
||||
|
@ -121,17 +164,7 @@ static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
|||
/* Write IOSF control register */
|
||||
IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
|
||||
|
||||
/* Check every 10 usec to see if the address cycle completed.
|
||||
* The SB IOSF BUSY bit will clear when the operation is
|
||||
* complete
|
||||
*/
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
usleep_range(10, 20);
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
|
||||
if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
ret = ixgbe_iosf_wait(hw, &command);
|
||||
|
||||
if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
|
||||
error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
|
||||
|
@ -140,14 +173,12 @@ static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
|||
return IXGBE_ERR_PHY;
|
||||
}
|
||||
|
||||
if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
|
||||
hw_dbg(hw, "Read timed out\n");
|
||||
return IXGBE_ERR_PHY;
|
||||
}
|
||||
if (!ret)
|
||||
*data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
|
||||
|
||||
*data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
hw->mac.ops.release_swfw_sync(hw, gssr);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
|
||||
|
@ -789,7 +820,17 @@ static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
|
|||
static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
u32 device_type, u32 data)
|
||||
{
|
||||
u32 i, command, error;
|
||||
u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
|
||||
u32 command, error;
|
||||
s32 ret;
|
||||
|
||||
ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ixgbe_iosf_wait(hw, NULL);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
|
||||
(device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
|
||||
|
@ -800,17 +841,7 @@ static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
|||
/* Write IOSF data register */
|
||||
IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
|
||||
|
||||
/* Check every 10 usec to see if the address cycle completed.
|
||||
* The SB IOSF BUSY bit will clear when the operation is
|
||||
* complete
|
||||
*/
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
usleep_range(10, 20);
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
|
||||
if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
ret = ixgbe_iosf_wait(hw, &command);
|
||||
|
||||
if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
|
||||
error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
|
||||
|
@ -819,12 +850,9 @@ static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
|||
return IXGBE_ERR_PHY;
|
||||
}
|
||||
|
||||
if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
|
||||
hw_dbg(hw, "Write timed out\n");
|
||||
return IXGBE_ERR_PHY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
out:
|
||||
hw->mac.ops.release_swfw_sync(hw, gssr);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
|
||||
|
@ -1035,7 +1063,7 @@ static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
|
|||
**/
|
||||
static s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
|
||||
{
|
||||
u32 status;
|
||||
s32 status;
|
||||
u16 lasi, autoneg_status, speed;
|
||||
ixgbe_link_speed force_speed;
|
||||
|
||||
|
@ -1177,7 +1205,7 @@ static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
|
|||
**/
|
||||
static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
|
||||
{
|
||||
u32 status;
|
||||
s32 status;
|
||||
u16 reg;
|
||||
u32 retries = 2;
|
||||
|
||||
|
|
Loading…
Reference in a new issue