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[TG3]: Add rx BD workaround
Add workaround to limit the burst size of rx BDs being DMA'ed to the chip. This works around hardware errata on a number of 5750, 5752, and 5755 chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
29315e8770
commit
f92905deb9
2 changed files with 29 additions and 2 deletions
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@ -3195,7 +3195,7 @@ static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
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*/
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static int tg3_rx(struct tg3 *tp, int budget)
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{
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u32 work_mask;
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u32 work_mask, rx_std_posted = 0;
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u32 sw_idx = tp->rx_rcb_ptr;
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u16 hw_idx;
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int received;
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@ -3222,6 +3222,7 @@ static int tg3_rx(struct tg3 *tp, int budget)
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mapping);
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skb = tp->rx_std_buffers[desc_idx].skb;
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post_ptr = &tp->rx_std_ptr;
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rx_std_posted++;
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} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
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dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
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mapping);
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@ -3309,6 +3310,15 @@ static int tg3_rx(struct tg3 *tp, int budget)
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next_pkt:
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(*post_ptr)++;
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if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
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u32 idx = *post_ptr % TG3_RX_RING_SIZE;
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tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
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TG3_64BIT_REG_LOW, idx);
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work_mask &= ~RXD_OPAQUE_RING_STD;
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rx_std_posted = 0;
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}
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next_pkt_nopost:
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sw_idx++;
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sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
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@ -5981,7 +5991,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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}
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/* Setup replenish threshold. */
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tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
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val = tp->rx_pending / 8;
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if (val == 0)
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val = 1;
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else if (val > tp->rx_std_max_post)
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val = tp->rx_std_max_post;
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tw32(RCVBDI_STD_THRESH, val);
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/* Initialize TG3_BDINFO's at:
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* RCVDBDI_STD_BD: standard eth size rx ring
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@ -10545,6 +10561,16 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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(tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
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tp->rx_offset = 0;
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tp->rx_std_max_post = TG3_RX_RING_SIZE;
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/* Increment the rx prod index on the rx std ring by at most
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* 8 for these chips to workaround hw errata.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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tp->rx_std_max_post = 8;
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/* By default, disable wake-on-lan. User can change this
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* using ETHTOOL_SWOL.
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*/
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@ -2137,6 +2137,7 @@ struct tg3 {
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struct tg3_rx_buffer_desc *rx_std;
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struct ring_info *rx_std_buffers;
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dma_addr_t rx_std_mapping;
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u32 rx_std_max_post;
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struct tg3_rx_buffer_desc *rx_jumbo;
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struct ring_info *rx_jumbo_buffers;
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