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clk: qcom: add read-only divider operations
Some of the divider settings are preconfigured and should not
be changed by the clock framework during frequency change. This
patch adds the read-only divider operation for QCOM dividers
which is equivalent to generic divider operations in
'commit 79c6ab5095
("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
parent
23c68cc968
commit
f933d383df
2 changed files with 30 additions and 0 deletions
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@ -23,6 +23,29 @@ static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
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return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
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}
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static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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struct clk_regmap *clkr = ÷r->clkr;
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u32 div;
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struct clk_hw *hw_parent = clk_hw_get_parent(hw);
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regmap_read(clkr->regmap, divider->reg, &div);
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div >>= divider->shift;
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div &= BIT(divider->width) - 1;
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div += 1;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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if (!hw_parent)
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return -EINVAL;
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*prate = clk_hw_round_rate(hw_parent, rate * div);
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}
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return DIV_ROUND_UP_ULL((u64)*prate, div);
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}
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static long div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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@ -68,3 +91,9 @@ const struct clk_ops clk_regmap_div_ops = {
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.recalc_rate = div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
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const struct clk_ops clk_regmap_div_ro_ops = {
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.round_rate = div_round_ro_rate,
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.recalc_rate = div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
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@ -25,5 +25,6 @@ struct clk_regmap_div {
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};
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extern const struct clk_ops clk_regmap_div_ops;
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extern const struct clk_ops clk_regmap_div_ro_ops;
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#endif
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