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Merge branch 'pci/dpc'
- Work around a BIOS defect that makes some Intel Root Ports report an RP PIO log size of zero (Mika Westerberg) * pci/dpc: PCI/DPC: Quirk PIO log size for certain Intel Root Ports
This commit is contained in:
commit
f9538e27a2
2 changed files with 46 additions and 5 deletions
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@ -335,11 +335,16 @@ void pci_dpc_init(struct pci_dev *pdev)
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return;
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pdev->dpc_rp_extensions = true;
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pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
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pci_err(pdev, "RP PIO log size %u is invalid\n",
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pdev->dpc_rp_log_size);
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pdev->dpc_rp_log_size = 0;
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/* Quirks may set dpc_rp_log_size if device or firmware is buggy */
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if (!pdev->dpc_rp_log_size) {
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pdev->dpc_rp_log_size =
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(cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
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pci_err(pdev, "RP PIO log size %u is invalid\n",
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pdev->dpc_rp_log_size);
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pdev->dpc_rp_log_size = 0;
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}
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}
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}
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@ -5956,3 +5956,39 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
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#endif
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#ifdef CONFIG_PCIE_DPC
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/*
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* Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
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* RP PIO Log Size of the integrated Thunderbolt PCIe Root Ports.
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*/
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static void dpc_log_size(struct pci_dev *dev)
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{
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u16 dpc, val;
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dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
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if (!dpc)
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return;
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pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
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if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
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return;
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if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
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pci_info(dev, "Overriding RP PIO Log Size to 4\n");
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dev->dpc_rp_log_size = 4;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
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#endif
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