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arm64: dts: qcom: sa8775p: sort soc nodes by reg property
Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl
This commit is contained in:
Bartosz Golaszewski
Bjorn Andersson
parent
3fd7e2eec8
commit
f95f988cf7
1 changed files with 197 additions and 197 deletions
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@ -471,50 +471,6 @@ ipcc: mailbox@408000 {
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#mbox-cells = <2>;
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};
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qupv3_id_1: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x00ac0000 0x0 0x6000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x443 0x0>;
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status = "disabled";
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uart10: serial@a8c000 {
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compatible = "qcom,geni-uart";
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reg = <0x0 0x00a8c000 0x0 0x4000>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interconnect-names = "qup-core", "qup-config";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 0
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&clk_virt SLAVE_QUP_CORE_1 0>,
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<&gem_noc MASTER_APPSS_PROC 0
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&config_noc SLAVE_QUP_1 0>;
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power-domains = <&rpmhpd SA8775P_CX>;
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operating-points-v2 = <&qup_opp_table_100mhz>;
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status = "disabled";
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};
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uart12: serial@a94000 {
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compatible = "qcom,geni-uart";
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reg = <0x0 0x00a94000 0x0 0x4000>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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};
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qupv3_id_2: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x008c0000 0x0 0x6000>;
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@ -585,152 +541,48 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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};
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
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<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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};
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qupv3_id_1: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x00ac0000 0x0 0x6000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x443 0x0>;
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status = "disabled";
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memtimer: timer@17c20000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x17c20000 0x0 0x1000>;
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ranges = <0x0 0x0 0x0 0x20000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@17c21000 {
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <0>;
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};
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frame@17c23000 {
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reg = <0x17c23000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <1>;
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uart10: serial@a8c000 {
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compatible = "qcom,geni-uart";
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reg = <0x0 0x00a8c000 0x0 0x4000>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interconnect-names = "qup-core", "qup-config";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 0
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&clk_virt SLAVE_QUP_CORE_1 0>,
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<&gem_noc MASTER_APPSS_PROC 0
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&config_noc SLAVE_QUP_1 0>;
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power-domains = <&rpmhpd SA8775P_CX>;
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operating-points-v2 = <&qup_opp_table_100mhz>;
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status = "disabled";
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};
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frame@17c25000 {
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reg = <0x17c25000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <2>;
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uart12: serial@a94000 {
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compatible = "qcom,geni-uart";
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reg = <0x0 0x00a94000 0x0 0x4000>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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frame@17c27000 {
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reg = <0x17c27000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <3>;
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status = "disabled";
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};
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frame@17c29000 {
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reg = <0x17c29000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <4>;
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status = "disabled";
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};
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frame@17c2b000 {
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reg = <0x17c2b000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <5>;
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status = "disabled";
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};
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frame@17c2d000 {
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reg = <0x17c2d000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <6>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@18200000 {
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compatible = "qcom,rpmh-rsc";
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reg = <0x0 0x18200000 0x0 0x10000>,
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<0x0 0x18210000 0x0 0x10000>,
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<0x0 0x18220000 0x0 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 0>;
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label = "apps_rsc";
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apps_bcm_voter: bcm-voter {
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compatible = "qcom,bcm-voter";
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};
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rpmhcc: clock-controller {
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compatible = "qcom,sa8775p-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board_clk>;
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};
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rpmhpd: power-controller {
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compatible = "qcom,sa8775p-rpmhpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmhpd_opp_table>;
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rpmhpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmhpd_opp_ret: opp-0 {
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opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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};
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rpmhpd_opp_min_svs: opp-1 {
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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rpmhpd_opp_low_svs: opp2 {
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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rpmhpd_opp_svs: opp3 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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rpmhpd_opp_svs_l1: opp-4 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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rpmhpd_opp_nom: opp-5 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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rpmhpd_opp_nom_l1: opp-6 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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rpmhpd_opp_nom_l2: opp-7 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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};
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rpmhpd_opp_turbo: opp-8 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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rpmhpd_opp_turbo_l1: opp-9 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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};
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};
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};
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tcsr_mutex: hwlock@1f40000 {
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@ -739,19 +591,6 @@ tcsr_mutex: hwlock@1f40000 {
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#hwlock-cells = <1>;
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};
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cpufreq_hw: cpufreq@18591000 {
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compatible = "qcom,sa8775p-cpufreq-epss",
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"qcom,cpufreq-epss";
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reg = <0x0 0x18591000 0x0 0x1000>,
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<0x0 0x18593000 0x0 0x1000>;
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reg-names = "freq-domain0", "freq-domain1";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
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clock-names = "xo", "alternate";
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#freq-domain-cells = <1>;
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,sa8775p-tlmm";
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reg = <0x0 0x0f000000 0x0 0x1000000>;
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@ -900,6 +739,167 @@ apps_smmu: iommu@15000000 {
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<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
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<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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};
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memtimer: timer@17c20000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x17c20000 0x0 0x1000>;
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ranges = <0x0 0x0 0x0 0x20000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@17c21000 {
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <0>;
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};
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frame@17c23000 {
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reg = <0x17c23000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <1>;
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status = "disabled";
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};
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frame@17c25000 {
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reg = <0x17c25000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <2>;
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status = "disabled";
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};
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frame@17c27000 {
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reg = <0x17c27000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <3>;
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status = "disabled";
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};
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frame@17c29000 {
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reg = <0x17c29000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <4>;
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status = "disabled";
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};
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frame@17c2b000 {
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reg = <0x17c2b000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <5>;
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status = "disabled";
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};
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frame@17c2d000 {
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reg = <0x17c2d000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <6>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@18200000 {
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compatible = "qcom,rpmh-rsc";
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reg = <0x0 0x18200000 0x0 0x10000>,
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<0x0 0x18210000 0x0 0x10000>,
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<0x0 0x18220000 0x0 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 0>;
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label = "apps_rsc";
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apps_bcm_voter: bcm-voter {
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compatible = "qcom,bcm-voter";
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};
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rpmhcc: clock-controller {
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compatible = "qcom,sa8775p-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board_clk>;
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};
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rpmhpd: power-controller {
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compatible = "qcom,sa8775p-rpmhpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmhpd_opp_table>;
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rpmhpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmhpd_opp_ret: opp-0 {
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opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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};
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rpmhpd_opp_min_svs: opp-1 {
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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rpmhpd_opp_low_svs: opp2 {
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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rpmhpd_opp_svs: opp3 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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rpmhpd_opp_svs_l1: opp-4 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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rpmhpd_opp_nom: opp-5 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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rpmhpd_opp_nom_l1: opp-6 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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rpmhpd_opp_nom_l2: opp-7 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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};
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rpmhpd_opp_turbo: opp-8 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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rpmhpd_opp_turbo_l1: opp-9 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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};
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};
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};
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cpufreq_hw: cpufreq@18591000 {
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compatible = "qcom,sa8775p-cpufreq-epss",
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"qcom,cpufreq-epss";
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reg = <0x0 0x18591000 0x0 0x1000>,
|
||||
<0x0 0x18593000 0x0 0x1000>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
|
|
|
|||
Loading…
Reference in a new issue