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clk: meson: mpll: properly handle spread spectrum

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The bit 'SSEN' available on some MPLL DSS outputs is not related to the
fractional part of the divider but to the function called
'Spread Spectrum'.

This function might be used to solve EM issues by adding a jitter on
clock signal. This widens the signal spectrum and weakens the peaks in it.

While spread spectrum might be useful for some application, it is
problematic for others, such as audio.

This patch introduce a new flag to the MPLL driver to enable (or not) the
spread spectrum function.

Fixes: 1f737ffa13 ("clk: meson: mpll: fix mpll0 fractional part ignored")
Tested-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet 2019-05-13 14:31:09 +02:00
parent 3ff46efbcd
commit f9b3eeebef
2 changed files with 7 additions and 3 deletions
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9
drivers/clk/meson/clk-mpll.c
View file

@ -119,9 +119,12 @@ static int mpll_set_rate(struct clk_hw *hw,
meson_parm_write(clk->map, &mpll->sdm, sdm);
meson_parm_write(clk->map, &mpll->sdm_en, 1);
/* Set additional fractional part enable if required */
if (MESON_PARM_APPLICABLE(&mpll->ssen))
meson_parm_write(clk->map, &mpll->ssen, 1);
/* Set spread spectrum if possible */
if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
unsigned int ss =
mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
meson_parm_write(clk->map, &mpll->ssen, ss);
}
/* Set the integer divider part */
meson_parm_write(clk->map, &mpll->n2, n2);

1
drivers/clk/meson/clk-mpll.h
View file

@ -23,6 +23,7 @@ struct meson_clk_mpll_data {
};
#define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0)
#define CLK_MESON_MPLL_SPREAD_SPECTRUM BIT(1)
extern const struct clk_ops meson_clk_mpll_ro_ops;
extern const struct clk_ops meson_clk_mpll_ops;