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drm/radeon: rework VCE FW size calculation
Previously we were completely over allocating, fix this by actually implementing the size calculation. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
72b9076b28
commit
fa0cf2f246
4 changed files with 15 additions and 7 deletions
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@ -1709,8 +1709,6 @@ int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
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* VCE
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*/
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#define RADEON_MAX_VCE_HANDLES 16
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#define RADEON_VCE_STACK_SIZE (1024*1024)
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#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
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struct radeon_vce {
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struct radeon_bo *vcpu_bo;
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@ -974,6 +974,7 @@ int vce_v1_0_init(struct radeon_device *rdev);
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int vce_v1_0_start(struct radeon_device *rdev);
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/* vce v2.0 */
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unsigned vce_v2_0_bo_size(struct radeon_device *rdev);
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int vce_v2_0_resume(struct radeon_device *rdev);
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#endif
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@ -123,8 +123,7 @@ int radeon_vce_init(struct radeon_device *rdev)
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/* allocate firmware, stack and heap BO */
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +
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RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;
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size = vce_v2_0_bo_size(rdev);
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL,
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&rdev->vce.vcpu_bo);
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@ -31,6 +31,10 @@
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#include "radeon_asic.h"
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#include "cikd.h"
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#define VCE_V2_0_FW_SIZE (256 * 1024)
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#define VCE_V2_0_STACK_SIZE (64 * 1024)
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#define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES)
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static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
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{
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u32 tmp;
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@ -140,6 +144,12 @@ static void vce_v2_0_init_cg(struct radeon_device *rdev)
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WREG32(VCE_CLOCK_GATING_B, tmp);
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}
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unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
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{
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WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
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return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
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}
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int vce_v2_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr = rdev->vce.gpu_addr;
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@ -159,17 +169,17 @@ int vce_v2_0_resume(struct radeon_device *rdev)
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WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
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addr &= 0xff;
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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size = VCE_V2_0_FW_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = RADEON_VCE_STACK_SIZE;
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size = VCE_V2_0_STACK_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = RADEON_VCE_HEAP_SIZE;
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size = VCE_V2_0_DATA_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE2, size);
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