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[ARM] Separate VIC (vectored interrupt controller) support from Versatile
Other machines may wish to make use of the VIC support code, so move it to arch/arm/common. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
5ff3fd2716
commit
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8 changed files with 151 additions and 77 deletions
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@ -180,6 +180,7 @@ config ARCH_OMAP
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config ARCH_VERSATILE
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bool "Versatile"
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select ARM_AMBA
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select ARM_VIC
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select ICST307
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help
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This enables support for ARM Ltd Versatile board.
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@ -1,7 +1,10 @@
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config ICST525
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config ARM_GIC
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bool
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config ARM_GIC
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config ARM_VIC
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bool
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config ICST525
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bool
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config ICST307
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@ -4,6 +4,7 @@
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obj-y += rtctime.o
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obj-$(CONFIG_ARM_GIC) += gic.o
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obj-$(CONFIG_ARM_VIC) += vic.o
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obj-$(CONFIG_ICST525) += icst525.o
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obj-$(CONFIG_ICST307) += icst307.o
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obj-$(CONFIG_SA1111) += sa1111.o
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92
arch/arm/common/vic.c
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92
arch/arm/common/vic.c
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@ -0,0 +1,92 @@
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/*
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* linux/arch/arm/common/vic.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/list.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/vic.h>
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static void __iomem *vic_base;
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static void vic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_VIC_START;
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writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
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}
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static void vic_unmask_irq(unsigned int irq)
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{
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irq -= IRQ_VIC_START;
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writel(1 << irq, vic_base + VIC_INT_ENABLE);
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}
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static struct irqchip vic_chip = {
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.ack = vic_mask_irq,
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.mask = vic_mask_irq,
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.unmask = vic_unmask_irq,
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};
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void __init vic_init(void __iomem *base, u32 vic_sources)
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{
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unsigned int i;
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vic_base = base;
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/* Disable all interrupts initially. */
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writel(0, vic_base + VIC_INT_SELECT);
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writel(0, vic_base + VIC_INT_ENABLE);
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writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
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writel(0, vic_base + VIC_IRQ_STATUS);
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writel(0, vic_base + VIC_ITCR);
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writel(~0, vic_base + VIC_INT_SOFT_CLEAR);
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/*
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* Make sure we clear all existing interrupts
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*/
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writel(0, vic_base + VIC_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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unsigned int value;
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value = readl(vic_base + VIC_VECT_ADDR);
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writel(value, vic_base + VIC_VECT_ADDR);
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}
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for (i = 0; i < 16; i++) {
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void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, vic_base + VIC_DEF_VECT_ADDR);
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for (i = 0; i < 32; i++) {
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unsigned int irq = IRQ_VIC_START + i;
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set_irq_chip(irq, &vic_chip);
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if (vic_sources & (1 << i)) {
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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}
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@ -35,6 +35,7 @@
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#include <asm/leds.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/icst307.h>
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#include <asm/hardware/vic.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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@ -56,24 +57,6 @@
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#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
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#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
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static void vic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_VIC_START;
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writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
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}
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static void vic_unmask_irq(unsigned int irq)
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{
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irq -= IRQ_VIC_START;
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writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
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}
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static struct irqchip vic_chip = {
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.ack = vic_mask_irq,
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.mask = vic_mask_irq,
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.unmask = vic_unmask_irq,
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};
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static void sic_mask_irq(unsigned int irq)
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{
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irq -= IRQ_SIC_START;
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@ -127,43 +110,12 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
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void __init versatile_init_irq(void)
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{
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unsigned int i, value;
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unsigned int i;
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/* Disable all interrupts initially. */
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writel(0, VA_VIC_BASE + VIC_INT_SELECT);
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writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
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writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
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writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
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writel(0, VA_VIC_BASE + VIC_ITCR);
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writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
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/*
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* Make sure we clear all existing interrupts
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*/
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writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
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writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
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}
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for (i = 0; i < 16; i++) {
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value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
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writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
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}
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writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
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for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
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if (i != IRQ_VICSOURCE31) {
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set_irq_chip(i, &vic_chip);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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vic_init(VA_VIC_BASE, ~(1 << 31));
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set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
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vic_unmask_irq(IRQ_VICSOURCE31);
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enable_irq(IRQ_VICSOURCE31);
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/* Do second interrupt controller */
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writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
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@ -877,7 +829,7 @@ static unsigned long versatile_gettimeoffset(void)
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ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
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do {
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ticks1 = ticks2;
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status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
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status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
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ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
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} while (ticks2 > ticks1);
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@ -8,6 +8,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/hardware.h>
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#include <asm/hardware/vic.h>
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.macro disable_fiq
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.endm
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@ -293,26 +293,7 @@
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* VERSATILE_SYS_IC
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*
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*/
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#define VIC_IRQ_STATUS 0
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#define VIC_FIQ_STATUS 0x04
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#define VIC_IRQ_RAW_STATUS 0x08
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#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */
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#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
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#define VIC_IRQ_ENABLE_CLEAR 0x14
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#define VIC_IRQ_SOFT 0x18
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#define VIC_IRQ_SOFT_CLEAR 0x1C
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#define VIC_PROTECT 0x20
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#define VIC_VECT_ADDR 0x30
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#define VIC_DEF_VECT_ADDR 0x34
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#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
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#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
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#define VIC_ITCR 0x300 /* VIC test control register */
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#define VIC_FIQ_RAW_STATUS 0x08
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#define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
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#define VIC_FIQ_ENABLE_CLEAR 0x14
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#define VIC_FIQ_SOFT 0x18
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#define VIC_FIQ_SOFT_CLEAR 0x1C
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/* VIC definitions in include/asm-arm/hardware/vic.h */
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#define SIC_IRQ_STATUS 0
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#define SIC_IRQ_RAW_STATUS 0x04
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#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
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#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
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#define VICVectCntl_Enable (1 << 5)
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/* ------------------------------------------------------------------------
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* Interrupts - bit assignment (primary)
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* ------------------------------------------------------------------------
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45
include/asm-arm/hardware/vic.h
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45
include/asm-arm/hardware/vic.h
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/*
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* linux/include/asm-arm/hardware/vic.h
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*
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* Copyright (c) ARM Limited 2003. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_HARDWARE_VIC_H
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#define __ASM_ARM_HARDWARE_VIC_H
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#define VIC_IRQ_STATUS 0x00
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#define VIC_FIQ_STATUS 0x04
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#define VIC_RAW_STATUS 0x08
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#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
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#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
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#define VIC_INT_ENABLE_CLEAR 0x14
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#define VIC_INT_SOFT 0x18
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#define VIC_INT_SOFT_CLEAR 0x1c
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#define VIC_PROTECT 0x20
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#define VIC_VECT_ADDR 0x30
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#define VIC_DEF_VECT_ADDR 0x34
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#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
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#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
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#define VIC_ITCR 0x300 /* VIC test control register */
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#define VIC_VECT_CNTL_ENABLE (1 << 5)
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#ifndef __ASSEMBLY__
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void vic_init(void __iomem *base, u32 vic_sources);
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#endif
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#endif
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