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[ARM] 3601/1: i.MX/MX1 DMA error handling for signaled channels only
Patch from Pavel Pisa There has been bug, that dma_err_handler() touches even channels not signaling error condition. Problem noticed by Andrea Paterniani. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
e22b04fb6b
commit
fa3e686a34
2 changed files with 48 additions and 31 deletions
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@ -15,6 +15,9 @@
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* Changed to support scatter gather DMA
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* by taking Russell's code from RiscPC
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*
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* 2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Corrected error handling code.
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*
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*/
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#undef DEBUG
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@ -277,7 +280,7 @@ imx_dma_setup_sg(imx_dmach_t dma_ch,
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int
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imx_dma_setup_handlers(imx_dmach_t dma_ch,
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void (*irq_handler) (int, void *, struct pt_regs *),
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void (*err_handler) (int, void *, struct pt_regs *),
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void (*err_handler) (int, void *, struct pt_regs *, int),
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void *data)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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@ -463,43 +466,53 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id, struct pt_regs *regs)
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int i, disr = DISR;
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struct imx_dma_channel *channel;
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unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
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int errcode;
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DISR = disr;
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DISR = disr & err_mask;
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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if(!(err_mask & (1 << i)))
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continue;
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channel = &imx_dma_channels[i];
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errcode = 0;
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if ((err_mask & 1 << i) && channel->name
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&& channel->err_handler) {
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channel->err_handler(i, channel->data, regs);
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if (DBTOSR & (1 << i)) {
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DBTOSR = (1 << i);
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errcode |= IMX_DMA_ERR_BURST;
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}
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if (DRTOSR & (1 << i)) {
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DRTOSR = (1 << i);
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errcode |= IMX_DMA_ERR_REQUEST;
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}
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if (DSESR & (1 << i)) {
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DSESR = (1 << i);
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errcode |= IMX_DMA_ERR_TRANSFER;
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}
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if (DBOSR & (1 << i)) {
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DBOSR = (1 << i);
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errcode |= IMX_DMA_ERR_BUFFER;
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}
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/*
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* The cleaning of @sg field would be questionable
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* there, because its value can help to compute
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* remaining/transfered bytes count in the handler
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*/
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/*imx_dma_channels[i].sg = NULL;*/
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if (channel->name && channel->err_handler) {
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channel->err_handler(i, channel->data, regs, errcode);
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continue;
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}
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imx_dma_channels[i].sg = NULL;
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if (DBTOSR & (1 << i)) {
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printk(KERN_WARNING
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"Burst timeout on channel %d (%s)\n",
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i, channel->name);
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DBTOSR |= (1 << i);
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}
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if (DRTOSR & (1 << i)) {
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printk(KERN_WARNING
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"Request timeout on channel %d (%s)\n",
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i, channel->name);
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DRTOSR |= (1 << i);
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}
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if (DSESR & (1 << i)) {
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printk(KERN_WARNING
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"Transfer timeout on channel %d (%s)\n",
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i, channel->name);
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DSESR |= (1 << i);
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}
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if (DBOSR & (1 << i)) {
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printk(KERN_WARNING
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"Buffer overflow timeout on channel %d (%s)\n",
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i, channel->name);
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DBOSR |= (1 << i);
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}
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printk(KERN_WARNING
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"DMA timeout on channel %d (%s) -%s%s%s%s\n",
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i, channel->name,
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errcode&IMX_DMA_ERR_BURST? " burst":"",
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errcode&IMX_DMA_ERR_REQUEST? " request":"",
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errcode&IMX_DMA_ERR_TRANSFER? " transfer":"",
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errcode&IMX_DMA_ERR_BUFFER? " buffer":"");
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}
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return IRQ_HANDLED;
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}
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@ -46,7 +46,7 @@
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struct imx_dma_channel {
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const char *name;
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void (*irq_handler) (int, void *, struct pt_regs *);
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void (*err_handler) (int, void *, struct pt_regs *);
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void (*err_handler) (int, void *, struct pt_regs *, int errcode);
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void *data;
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dmamode_t dma_mode;
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struct scatterlist *sg;
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@ -58,6 +58,10 @@ struct imx_dma_channel {
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extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
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#define IMX_DMA_ERR_BURST 1
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#define IMX_DMA_ERR_REQUEST 2
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#define IMX_DMA_ERR_TRANSFER 4
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#define IMX_DMA_ERR_BUFFER 8
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/* The type to distinguish channel numbers parameter from ordinal int type */
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typedef int imx_dmach_t;
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@ -74,7 +78,7 @@ imx_dma_setup_sg(imx_dmach_t dma_ch,
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int
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imx_dma_setup_handlers(imx_dmach_t dma_ch,
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void (*irq_handler) (int, void *, struct pt_regs *),
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void (*err_handler) (int, void *, struct pt_regs *), void *data);
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void (*err_handler) (int, void *, struct pt_regs *, int), void *data);
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void imx_dma_enable(imx_dmach_t dma_ch);
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