mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge tag 'amd-drm-fixes-5.8-2020-06-04' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-fixes-5.8-2020-06-04 amdgpu: - Prevent hwmon accesses while GPU is in reset - CTF interrupt fix - Backlight fix for renoir - Fix for display sync groups - Display bandwidth validation workaround Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200604181900.4609-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
fa3fa2228c
4 changed files with 207 additions and 11 deletions
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@ -163,6 +163,9 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
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enum amd_pm_state_type pm;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -196,6 +199,9 @@ static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
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enum amd_pm_state_type state;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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if (strncmp("battery", buf, strlen("battery")) == 0)
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state = POWER_STATE_TYPE_BATTERY;
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else if (strncmp("balanced", buf, strlen("balanced")) == 0)
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@ -297,6 +303,9 @@ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
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enum amd_dpm_forced_level level = 0xff;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -334,6 +343,9 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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enum amd_dpm_forced_level current_level = 0xff;
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int ret = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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if (strncmp("low", buf, strlen("low")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_LOW;
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} else if (strncmp("high", buf, strlen("high")) == 0) {
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@ -433,6 +445,9 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
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struct pp_states_info data;
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int i, buf_len, ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -472,6 +487,9 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
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enum amd_pm_state_type pm = 0;
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int i = 0, ret = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -508,6 +526,9 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev,
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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if (adev->in_gpu_reset)
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return -EPERM;
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if (adev->pp_force_state_enabled)
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return amdgpu_get_pp_cur_state(dev, attr, buf);
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else
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@ -525,6 +546,9 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
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unsigned long idx;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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if (strlen(buf) == 1)
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adev->pp_force_state_enabled = false;
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else if (is_support_sw_smu(adev))
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@ -580,6 +604,9 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
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char *table = NULL;
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int size, ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -619,6 +646,9 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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struct amdgpu_device *adev = ddev->dev_private;
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int ret = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -721,6 +751,9 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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const char delimiter[3] = {' ', '\n', '\0'};
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uint32_t type;
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if (adev->in_gpu_reset)
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return -EPERM;
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if (count > 127)
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return -EINVAL;
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@ -810,6 +843,9 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -859,6 +895,9 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
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uint64_t featuremask;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = kstrtou64(buf, 0, &featuremask);
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if (ret)
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return -EINVAL;
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@ -899,6 +938,9 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -955,6 +997,9 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1018,6 +1063,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
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int ret;
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uint32_t mask = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = amdgpu_read_mask(buf, count, &mask);
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if (ret)
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return ret;
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@ -1049,6 +1097,9 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1076,6 +1127,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
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uint32_t mask = 0;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = amdgpu_read_mask(buf, count, &mask);
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if (ret)
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return ret;
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@ -1107,6 +1161,9 @@ static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1134,6 +1191,9 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
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int ret;
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uint32_t mask = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = amdgpu_read_mask(buf, count, &mask);
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if (ret)
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return ret;
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@ -1167,6 +1227,9 @@ static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1194,6 +1257,9 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
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int ret;
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uint32_t mask = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = amdgpu_read_mask(buf, count, &mask);
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if (ret)
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return ret;
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@ -1227,6 +1293,9 @@ static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1254,6 +1323,9 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
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int ret;
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uint32_t mask = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = amdgpu_read_mask(buf, count, &mask);
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if (ret)
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return ret;
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@ -1287,6 +1359,9 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1314,6 +1389,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
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int ret;
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uint32_t mask = 0;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = amdgpu_read_mask(buf, count, &mask);
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if (ret)
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return ret;
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@ -1347,6 +1425,9 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
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uint32_t value = 0;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1372,6 +1453,9 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
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int ret;
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long int value;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = kstrtol(buf, 0, &value);
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if (ret)
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@ -1410,6 +1494,9 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
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uint32_t value = 0;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1435,6 +1522,9 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
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int ret;
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long int value;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = kstrtol(buf, 0, &value);
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if (ret)
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@ -1493,6 +1583,9 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
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ssize_t size;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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ret = pm_runtime_get_sync(ddev->dev);
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if (ret < 0)
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return ret;
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@ -1528,6 +1621,9 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
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long int profile_mode = 0;
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const char delimiter[3] = {' ', '\n', '\0'};
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if (adev->in_gpu_reset)
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return -EPERM;
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tmp[0] = *(buf);
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tmp[1] = '\0';
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ret = kstrtol(tmp, 0, &profile_mode);
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@ -1587,6 +1683,9 @@ static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
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struct amdgpu_device *adev = ddev->dev_private;
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int r, value, size = sizeof(value);
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if (adev->in_gpu_reset)
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return -EPERM;
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r = pm_runtime_get_sync(ddev->dev);
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if (r < 0)
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return r;
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@ -1620,6 +1719,9 @@ static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
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struct amdgpu_device *adev = ddev->dev_private;
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int r, value, size = sizeof(value);
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if (adev->in_gpu_reset)
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return -EPERM;
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r = pm_runtime_get_sync(ddev->dev);
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if (r < 0)
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return r;
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@ -1658,6 +1760,9 @@ static ssize_t amdgpu_get_pcie_bw(struct device *dev,
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uint64_t count0 = 0, count1 = 0;
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int ret;
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if (adev->in_gpu_reset)
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return -EPERM;
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||||
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if (adev->flags & AMD_IS_APU)
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return -ENODATA;
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@ -1694,6 +1799,9 @@ static ssize_t amdgpu_get_unique_id(struct device *dev,
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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if (adev->in_gpu_reset)
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return -EPERM;
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if (adev->unique_id)
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return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
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@ -1888,6 +1996,9 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
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int channel = to_sensor_dev_attr(attr)->index;
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int r, temp = 0, size = sizeof(temp);
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if (adev->in_gpu_reset)
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return -EPERM;
|
||||
|
||||
if (channel >= PP_TEMP_MAX)
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return -EINVAL;
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||||
|
||||
|
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@ -2019,6 +2130,9 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
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u32 pwm_mode = 0;
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int ret;
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||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
ret = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
|
@ -2050,6 +2164,9 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
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int err, ret;
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||||
int value;
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||||
|
||||
if (adev->in_gpu_reset)
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||||
return -EPERM;
|
||||
|
||||
err = kstrtoint(buf, 10, &value);
|
||||
if (err)
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||||
return err;
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||||
|
|
@ -2099,6 +2216,9 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
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u32 value;
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||||
u32 pwm_mode;
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||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
err = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (err < 0)
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||||
return err;
|
||||
|
|
@ -2148,6 +2268,9 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
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int err;
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||||
u32 speed = 0;
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||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
err = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
|
@ -2178,6 +2301,9 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
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int err;
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||||
u32 speed = 0;
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||||
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||||
if (adev->in_gpu_reset)
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||||
return -EPERM;
|
||||
|
||||
err = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (err < 0)
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||||
return err;
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||||
|
|
@ -2207,6 +2333,9 @@ static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
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u32 size = sizeof(min_rpm);
|
||||
int r;
|
||||
|
||||
if (adev->in_gpu_reset)
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||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
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||||
return r;
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||||
|
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@ -2232,6 +2361,9 @@ static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
|
|||
u32 size = sizeof(max_rpm);
|
||||
int r;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -2256,6 +2388,9 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
|
|||
int err;
|
||||
u32 rpm = 0;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
err = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
|
@ -2285,6 +2420,9 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
|
|||
u32 value;
|
||||
u32 pwm_mode;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
err = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
|
@ -2331,6 +2469,9 @@ static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
|
|||
u32 pwm_mode = 0;
|
||||
int ret;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
ret = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
|
@ -2363,6 +2504,9 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
|
|||
int value;
|
||||
u32 pwm_mode;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
err = kstrtoint(buf, 10, &value);
|
||||
if (err)
|
||||
return err;
|
||||
|
|
@ -2403,6 +2547,9 @@ static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
|
|||
u32 vddgfx;
|
||||
int r, size = sizeof(vddgfx);
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -2435,6 +2582,9 @@ static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
|
|||
u32 vddnb;
|
||||
int r, size = sizeof(vddnb);
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
/* only APUs have vddnb */
|
||||
if (!(adev->flags & AMD_IS_APU))
|
||||
return -EINVAL;
|
||||
|
|
@ -2472,6 +2622,9 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
|
|||
int r, size = sizeof(u32);
|
||||
unsigned uw;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -2508,6 +2661,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
|
|||
ssize_t size;
|
||||
int r;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -2537,6 +2693,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
|
|||
ssize_t size;
|
||||
int r;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -2567,6 +2726,9 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
|
|||
int err;
|
||||
u32 value;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -2605,6 +2767,9 @@ static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
|
|||
uint32_t sclk;
|
||||
int r, size = sizeof(sclk);
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -2637,6 +2802,9 @@ static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
|
|||
uint32_t mclk;
|
||||
int r, size = sizeof(mclk);
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(adev->ddev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
@ -3497,6 +3665,9 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
|
|||
u32 flags = 0;
|
||||
int r;
|
||||
|
||||
if (adev->in_gpu_reset)
|
||||
return -EPERM;
|
||||
|
||||
r = pm_runtime_get_sync(dev->dev);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
|
|
|||
|
|
@ -1356,7 +1356,7 @@ static int dm_late_init(void *handle)
|
|||
unsigned int linear_lut[16];
|
||||
int i;
|
||||
struct dmcu *dmcu = NULL;
|
||||
bool ret = false;
|
||||
bool ret;
|
||||
|
||||
if (!adev->dm.fw_dmcu)
|
||||
return detect_mst_link_for_all_connectors(adev->ddev);
|
||||
|
|
@ -1377,13 +1377,10 @@ static int dm_late_init(void *handle)
|
|||
*/
|
||||
params.min_abm_backlight = 0x28F;
|
||||
|
||||
/* todo will enable for navi10 */
|
||||
if (adev->asic_type <= CHIP_RAVEN) {
|
||||
ret = dmcu_load_iram(dmcu, params);
|
||||
ret = dmcu_load_iram(dmcu, params);
|
||||
|
||||
if (!ret)
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!ret)
|
||||
return -EINVAL;
|
||||
|
||||
return detect_mst_link_for_all_connectors(adev->ddev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1016,9 +1016,17 @@ static void program_timing_sync(
|
|||
}
|
||||
}
|
||||
|
||||
/* set first pipe with plane as master */
|
||||
/* set first unblanked pipe as master */
|
||||
for (j = 0; j < group_size; j++) {
|
||||
if (pipe_set[j]->plane_state) {
|
||||
bool is_blanked;
|
||||
|
||||
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
|
||||
is_blanked =
|
||||
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
|
||||
else
|
||||
is_blanked =
|
||||
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
|
||||
if (!is_blanked) {
|
||||
if (j == 0)
|
||||
break;
|
||||
|
||||
|
|
@ -1039,9 +1047,17 @@ static void program_timing_sync(
|
|||
status->timing_sync_info.master = false;
|
||||
|
||||
}
|
||||
/* remove any other pipes with plane as they have already been synced */
|
||||
/* remove any other unblanked pipes as they have already been synced */
|
||||
for (j = j + 1; j < group_size; j++) {
|
||||
if (pipe_set[j]->plane_state) {
|
||||
bool is_blanked;
|
||||
|
||||
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
|
||||
is_blanked =
|
||||
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
|
||||
else
|
||||
is_blanked =
|
||||
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
|
||||
if (!is_blanked) {
|
||||
group_size--;
|
||||
pipe_set[j] = pipe_set[group_size];
|
||||
j--;
|
||||
|
|
@ -2522,6 +2538,12 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
|
||||
copy_stream_update_to_stream(dc, context, stream, stream_update);
|
||||
|
||||
if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
|
||||
DC_ERROR("Mode validation failed for stream update!\n");
|
||||
dc_release_state(context);
|
||||
return;
|
||||
}
|
||||
|
||||
commit_planes_for_stream(
|
||||
dc,
|
||||
srf_updates,
|
||||
|
|
|
|||
|
|
@ -1561,6 +1561,7 @@ static int smu_v11_0_irq_process(struct amdgpu_device *adev,
|
|||
* events for SMCToHost interrupt.
|
||||
*/
|
||||
uint32_t ctxid = entry->src_data[0];
|
||||
uint32_t data;
|
||||
|
||||
if (client_id == SOC15_IH_CLIENTID_THM) {
|
||||
switch (src_id) {
|
||||
|
|
@ -1590,6 +1591,11 @@ static int smu_v11_0_irq_process(struct amdgpu_device *adev,
|
|||
orderly_poweroff(true);
|
||||
} else if (client_id == SOC15_IH_CLIENTID_MP1) {
|
||||
if (src_id == 0xfe) {
|
||||
/* ACK SMUToHost interrupt */
|
||||
data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
|
||||
data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
|
||||
|
||||
switch (ctxid) {
|
||||
case 0x3:
|
||||
dev_dbg(adev->dev, "Switched to AC mode!\n");
|
||||
|
|
|
|||
Loading…
Reference in a new issue