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ARC: mmu: clarify the MMUv3 programming model
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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1 changed files with 5 additions and 1 deletions
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@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
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/*
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* For ARC700 MMUv3 I-cache and D-cache flushes
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* Also reused for HS38 aliasing I-cache configuration
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* - ARC700 programming model requires paddr and vaddr be passed in seperate
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* AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
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* caches actually alias or not.
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* - For HS38, only the aliasing I-cache configuration uses the PTAG reg
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* (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
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*/
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static inline
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void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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