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ARM: at91/at91x40: remove use of at91_sys_read/write
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
parent
0d78171672
commit
fac36a5ab9
3 changed files with 27 additions and 21 deletions
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@ -44,7 +44,7 @@ static void at91x40_idle(void)
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
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__raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
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cpu_do_idle();
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}
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@ -28,6 +28,12 @@
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#include <asm/mach/time.h>
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#include <mach/at91_tc.h>
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#define at91_tc_read(field) \
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__raw_readl(AT91_TC + field)
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#define at91_tc_write(field, value) \
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__raw_writel(value, AT91_TC + field);
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/*
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* 3 counter/timer units present.
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*/
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@ -37,12 +43,12 @@
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static unsigned long at91x40_gettimeoffset(void)
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{
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return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
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return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
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}
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static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
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{
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at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
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at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
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timer_tick();
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return IRQ_HANDLED;
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}
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@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
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{
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unsigned int v;
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at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
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v = at91_sys_read(AT91_TC + AT91_TC_BMR);
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at91_tc_write(AT91_TC_BCR, 0);
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v = at91_tc_read(AT91_TC_BMR);
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v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
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at91_sys_write(AT91_TC + AT91_TC_BMR, v);
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at91_tc_write(AT91_TC_BMR, v);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
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setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
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}
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struct sys_timer at91x40_timer = {
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@ -28,18 +28,18 @@
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#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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* System Peripherals
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*/
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#define AT91_BASE_SYS 0xffc00000
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#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */
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#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */
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#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */
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#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */
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#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */
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#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
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#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
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#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */
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#define AT91_EBI 0xffe00000 /* External Bus Interface */
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#define AT91_SF 0xfff00000 /* Special Function */
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#define AT91_USART1 0xfffcc000 /* USART 1 */
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#define AT91_USART0 0xfffd0000 /* USART 0 */
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#define AT91_TC 0xfffe0000 /* Timer Counter */
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#define AT91_PIOA 0xffff0000 /* PIO Controller A */
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#define AT91_PS 0xffff4000 /* Power Save */
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#define AT91_WD 0xffff8000 /* Watchdog Timer */
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/*
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* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
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