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x86/paravirt: Switch functions with custom code to ALTERNATIVE
Instead of using paravirt patching for custom code sequences use ALTERNATIVE for the functions with custom code replacements. Instead of patching an ud2 instruction for unpopulated vector entries into the caller site, use a simple function just calling BUG() as a replacement. Simplify the register defines for assembler paravirt calling, as there isn't much usage left. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20210311142319.4723-14-jgross@suse.com
This commit is contained in:
Juergen Gross
Borislav Petkov
parent
00aa3193ab
commit
fafe5e7422
6 changed files with 58 additions and 157 deletions
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@ -305,7 +305,7 @@ SYM_CODE_END(ret_from_fork)
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.macro DEBUG_ENTRY_ASSERT_IRQS_OFF
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#ifdef CONFIG_DEBUG_ENTRY
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pushq %rax
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SAVE_FLAGS(CLBR_RAX)
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SAVE_FLAGS
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testl $X86_EFLAGS_IF, %eax
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jz .Lokay_\@
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ud2
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@ -111,7 +111,7 @@ static __always_inline unsigned long arch_local_irq_save(void)
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#ifdef CONFIG_X86_64
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#ifdef CONFIG_DEBUG_ENTRY
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#define SAVE_FLAGS(x) pushfq; popq %rax
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#define SAVE_FLAGS pushfq; popq %rax
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#endif
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#define INTERRUPT_RETURN jmp native_iret
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@ -135,7 +135,9 @@ static inline void write_cr0(unsigned long x)
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static inline unsigned long read_cr2(void)
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{
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return PVOP_CALLEE0(unsigned long, mmu.read_cr2);
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return PVOP_ALT_CALLEE0(unsigned long, mmu.read_cr2,
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"mov %%cr2, %%rax;",
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ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline void write_cr2(unsigned long x)
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@ -145,12 +147,14 @@ static inline void write_cr2(unsigned long x)
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static inline unsigned long __read_cr3(void)
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{
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return PVOP_CALL0(unsigned long, mmu.read_cr3);
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return PVOP_ALT_CALL0(unsigned long, mmu.read_cr3,
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"mov %%cr3, %%rax;", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline void write_cr3(unsigned long x)
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{
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PVOP_VCALL1(mmu.write_cr3, x);
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PVOP_ALT_VCALL1(mmu.write_cr3, x,
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"mov %%rdi, %%cr3", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline void __write_cr4(unsigned long x)
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@ -170,7 +174,7 @@ static inline void halt(void)
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static inline void wbinvd(void)
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{
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PVOP_VCALL0(cpu.wbinvd);
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PVOP_ALT_VCALL0(cpu.wbinvd, "wbinvd", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline u64 paravirt_read_msr(unsigned msr)
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@ -384,22 +388,28 @@ static inline void paravirt_release_p4d(unsigned long pfn)
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static inline pte_t __pte(pteval_t val)
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{
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return (pte_t) { PVOP_CALLEE1(pteval_t, mmu.make_pte, val) };
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return (pte_t) { PVOP_ALT_CALLEE1(pteval_t, mmu.make_pte, val,
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"mov %%rdi, %%rax",
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ALT_NOT(X86_FEATURE_XENPV)) };
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}
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static inline pteval_t pte_val(pte_t pte)
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{
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return PVOP_CALLEE1(pteval_t, mmu.pte_val, pte.pte);
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return PVOP_ALT_CALLEE1(pteval_t, mmu.pte_val, pte.pte,
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"mov %%rdi, %%rax", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline pgd_t __pgd(pgdval_t val)
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{
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return (pgd_t) { PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val) };
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return (pgd_t) { PVOP_ALT_CALLEE1(pgdval_t, mmu.make_pgd, val,
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"mov %%rdi, %%rax",
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ALT_NOT(X86_FEATURE_XENPV)) };
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}
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static inline pgdval_t pgd_val(pgd_t pgd)
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{
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return PVOP_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd);
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return PVOP_ALT_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd,
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"mov %%rdi, %%rax", ALT_NOT(X86_FEATURE_XENPV));
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}
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#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
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@ -432,12 +442,15 @@ static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
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static inline pmd_t __pmd(pmdval_t val)
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{
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return (pmd_t) { PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val) };
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return (pmd_t) { PVOP_ALT_CALLEE1(pmdval_t, mmu.make_pmd, val,
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"mov %%rdi, %%rax",
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ALT_NOT(X86_FEATURE_XENPV)) };
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}
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static inline pmdval_t pmd_val(pmd_t pmd)
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{
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return PVOP_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd);
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return PVOP_ALT_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd,
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"mov %%rdi, %%rax", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline void set_pud(pud_t *pudp, pud_t pud)
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@ -449,14 +462,16 @@ static inline pud_t __pud(pudval_t val)
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{
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pudval_t ret;
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ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val);
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ret = PVOP_ALT_CALLEE1(pudval_t, mmu.make_pud, val,
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"mov %%rdi, %%rax", ALT_NOT(X86_FEATURE_XENPV));
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return (pud_t) { ret };
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}
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static inline pudval_t pud_val(pud_t pud)
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{
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return PVOP_CALLEE1(pudval_t, mmu.pud_val, pud.pud);
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return PVOP_ALT_CALLEE1(pudval_t, mmu.pud_val, pud.pud,
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"mov %%rdi, %%rax", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline void pud_clear(pud_t *pudp)
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@ -475,14 +490,17 @@ static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
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static inline p4d_t __p4d(p4dval_t val)
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{
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p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val);
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p4dval_t ret = PVOP_ALT_CALLEE1(p4dval_t, mmu.make_p4d, val,
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"mov %%rdi, %%rax",
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ALT_NOT(X86_FEATURE_XENPV));
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return (p4d_t) { ret };
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}
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static inline p4dval_t p4d_val(p4d_t p4d)
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{
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return PVOP_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d);
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return PVOP_ALT_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d,
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"mov %%rdi, %%rax", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
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@ -569,7 +587,9 @@ static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
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static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
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{
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PVOP_VCALLEE1(lock.queued_spin_unlock, lock);
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PVOP_ALT_VCALLEE1(lock.queued_spin_unlock, lock,
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"movb $0, (%%" _ASM_ARG1 ");",
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ALT_NOT(X86_FEATURE_PVUNLOCK));
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}
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static __always_inline void pv_wait(u8 *ptr, u8 val)
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@ -584,7 +604,9 @@ static __always_inline void pv_kick(int cpu)
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static __always_inline bool pv_vcpu_is_preempted(long cpu)
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{
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return PVOP_CALLEE1(bool, lock.vcpu_is_preempted, cpu);
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return PVOP_ALT_CALLEE1(bool, lock.vcpu_is_preempted, cpu,
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"xor %%" _ASM_AX ", %%" _ASM_AX ";",
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ALT_NOT(X86_FEATURE_VCPUPREEMPT));
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}
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void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock);
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@ -658,17 +680,18 @@ bool __raw_callee_save___native_vcpu_is_preempted(long cpu);
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#ifdef CONFIG_PARAVIRT_XXL
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static inline notrace unsigned long arch_local_save_flags(void)
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{
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return PVOP_CALLEE0(unsigned long, irq.save_fl);
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return PVOP_ALT_CALLEE0(unsigned long, irq.save_fl, "pushf; pop %%rax;",
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ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline notrace void arch_local_irq_disable(void)
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{
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PVOP_VCALLEE0(irq.irq_disable);
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PVOP_ALT_VCALLEE0(irq.irq_disable, "cli;", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline notrace void arch_local_irq_enable(void)
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{
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PVOP_VCALLEE0(irq.irq_enable);
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PVOP_ALT_VCALLEE0(irq.irq_enable, "sti;", ALT_NOT(X86_FEATURE_XENPV));
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}
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static inline notrace unsigned long arch_local_irq_save(void)
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@ -713,35 +736,9 @@ extern void default_banner(void);
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.popsection
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#define COND_PUSH(set, mask, reg) \
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.if ((~(set)) & mask); push %reg; .endif
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#define COND_POP(set, mask, reg) \
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.if ((~(set)) & mask); pop %reg; .endif
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#ifdef CONFIG_X86_64
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#ifdef CONFIG_PARAVIRT_XXL
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#define PV_SAVE_REGS(set) \
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COND_PUSH(set, CLBR_RAX, rax); \
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COND_PUSH(set, CLBR_RCX, rcx); \
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COND_PUSH(set, CLBR_RDX, rdx); \
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COND_PUSH(set, CLBR_RSI, rsi); \
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COND_PUSH(set, CLBR_RDI, rdi); \
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COND_PUSH(set, CLBR_R8, r8); \
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COND_PUSH(set, CLBR_R9, r9); \
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COND_PUSH(set, CLBR_R10, r10); \
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COND_PUSH(set, CLBR_R11, r11)
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#define PV_RESTORE_REGS(set) \
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COND_POP(set, CLBR_R11, r11); \
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COND_POP(set, CLBR_R10, r10); \
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COND_POP(set, CLBR_R9, r9); \
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COND_POP(set, CLBR_R8, r8); \
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COND_POP(set, CLBR_RDI, rdi); \
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COND_POP(set, CLBR_RSI, rsi); \
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COND_POP(set, CLBR_RDX, rdx); \
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COND_POP(set, CLBR_RCX, rcx); \
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COND_POP(set, CLBR_RAX, rax)
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#define PARA_PATCH(off) ((off) / 8)
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#define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .quad, 8)
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#define PARA_INDIRECT(addr) *addr(%rip)
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@ -752,12 +749,14 @@ extern void default_banner(void);
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X86_FEATURE_XENPV, "jmp xen_iret;", "jmp native_iret;")
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#ifdef CONFIG_DEBUG_ENTRY
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#define SAVE_FLAGS(clobbers) \
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PARA_SITE(PARA_PATCH(PV_IRQ_save_fl), \
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PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
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ANNOTATE_RETPOLINE_SAFE; \
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call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl); \
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PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
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.macro PARA_IRQ_save_fl
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PARA_SITE(PARA_PATCH(PV_IRQ_save_fl),
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ANNOTATE_RETPOLINE_SAFE;
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call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl);)
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.endm
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#define SAVE_FLAGS ALTERNATIVE "PARA_IRQ_save_fl;", "pushf; pop %rax;", \
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ALT_NOT(X86_FEATURE_XENPV)
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#endif
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#endif /* CONFIG_PARAVIRT_XXL */
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#endif /* CONFIG_X86_64 */
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@ -3,7 +3,6 @@
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#define _ASM_X86_PARAVIRT_TYPES_H
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/* Bitmask of what can be clobbered: usually at least eax. */
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#define CLBR_NONE 0
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#define CLBR_EAX (1 << 0)
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#define CLBR_ECX (1 << 1)
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#define CLBR_EDX (1 << 2)
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@ -15,7 +14,6 @@
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#define CLBR_ARG_REGS (CLBR_EAX | CLBR_EDX | CLBR_ECX)
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#define CLBR_RET_REG (CLBR_EAX | CLBR_EDX)
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#define CLBR_SCRATCH (0)
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#else
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#define CLBR_RAX CLBR_EAX
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#define CLBR_RCX CLBR_ECX
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@ -32,12 +30,9 @@
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#define CLBR_ARG_REGS (CLBR_RDI | CLBR_RSI | CLBR_RDX | \
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CLBR_RCX | CLBR_R8 | CLBR_R9)
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#define CLBR_RET_REG (CLBR_RAX)
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#define CLBR_SCRATCH (CLBR_R10 | CLBR_R11)
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#endif /* X86_64 */
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#define CLBR_CALLEE_SAVE ((CLBR_ARG_REGS | CLBR_SCRATCH) & ~CLBR_RET_REG)
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#ifndef __ASSEMBLY__
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#include <asm/desc_defs.h>
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@ -322,7 +317,6 @@ extern void (*paravirt_iret)(void);
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/* Simple instruction patching code. */
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#define NATIVE_LABEL(a,x,b) "\n\t.globl " a #x "_" #b "\n" a #x "_" #b ":\n\t"
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unsigned paravirt_patch_ident_64(void *insn_buff, unsigned len);
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unsigned paravirt_patch_default(u8 type, void *insn_buff, unsigned long addr, unsigned len);
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unsigned paravirt_patch_insns(void *insn_buff, unsigned len, const char *start, const char *end);
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@ -53,7 +53,10 @@ void __init default_banner(void)
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}
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/* Undefined instruction for dealing with missing ops pointers. */
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static const unsigned char ud2a[] = { 0x0f, 0x0b };
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static void paravirt_BUG(void)
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{
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BUG();
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}
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struct branch {
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unsigned char opcode;
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@ -107,17 +110,10 @@ unsigned paravirt_patch_default(u8 type, void *insn_buff,
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unsigned ret;
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if (opfunc == NULL)
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/* If there's no function, patch it with a ud2a (BUG) */
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ret = paravirt_patch_insns(insn_buff, len, ud2a, ud2a+sizeof(ud2a));
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/* If there's no function, patch it with paravirt_BUG() */
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ret = paravirt_patch_call(insn_buff, paravirt_BUG, addr, len);
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else if (opfunc == _paravirt_nop)
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ret = 0;
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#ifdef CONFIG_PARAVIRT_XXL
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/* identity functions just return their single argument */
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else if (opfunc == _paravirt_ident_64)
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ret = paravirt_patch_ident_64(insn_buff, len);
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#endif
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else
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/* Otherwise call the function. */
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ret = paravirt_patch_call(insn_buff, opfunc, addr, len);
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@ -4,96 +4,8 @@
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#include <asm/paravirt.h>
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#include <asm/asm-offsets.h>
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#define PSTART(d, m) \
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patch_data_##d.m
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#define PEND(d, m) \
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(PSTART(d, m) + sizeof(patch_data_##d.m))
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#define PATCH(d, m, insn_buff, len) \
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paravirt_patch_insns(insn_buff, len, PSTART(d, m), PEND(d, m))
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#define PATCH_CASE(ops, m, data, insn_buff, len) \
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case PARAVIRT_PATCH(ops.m): \
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return PATCH(data, ops##_##m, insn_buff, len)
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#ifdef CONFIG_PARAVIRT_XXL
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struct patch_xxl {
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const unsigned char irq_irq_disable[1];
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const unsigned char irq_irq_enable[1];
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const unsigned char irq_save_fl[2];
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const unsigned char mmu_read_cr2[3];
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const unsigned char mmu_read_cr3[3];
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const unsigned char mmu_write_cr3[3];
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const unsigned char cpu_wbinvd[2];
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const unsigned char mov64[3];
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};
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static const struct patch_xxl patch_data_xxl = {
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.irq_irq_disable = { 0xfa }, // cli
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.irq_irq_enable = { 0xfb }, // sti
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.irq_save_fl = { 0x9c, 0x58 }, // pushf; pop %[re]ax
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.mmu_read_cr2 = { 0x0f, 0x20, 0xd0 }, // mov %cr2, %[re]ax
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.mmu_read_cr3 = { 0x0f, 0x20, 0xd8 }, // mov %cr3, %[re]ax
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.mmu_write_cr3 = { 0x0f, 0x22, 0xdf }, // mov %rdi, %cr3
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.cpu_wbinvd = { 0x0f, 0x09 }, // wbinvd
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.mov64 = { 0x48, 0x89, 0xf8 }, // mov %rdi, %rax
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};
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unsigned int paravirt_patch_ident_64(void *insn_buff, unsigned int len)
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{
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return PATCH(xxl, mov64, insn_buff, len);
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}
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# endif /* CONFIG_PARAVIRT_XXL */
|
||||
|
||||
#ifdef CONFIG_PARAVIRT_SPINLOCKS
|
||||
struct patch_lock {
|
||||
unsigned char queued_spin_unlock[3];
|
||||
unsigned char vcpu_is_preempted[2];
|
||||
};
|
||||
|
||||
static const struct patch_lock patch_data_lock = {
|
||||
.vcpu_is_preempted = { 0x31, 0xc0 }, // xor %eax, %eax
|
||||
|
||||
# ifdef CONFIG_X86_64
|
||||
.queued_spin_unlock = { 0xc6, 0x07, 0x00 }, // movb $0, (%rdi)
|
||||
# else
|
||||
.queued_spin_unlock = { 0xc6, 0x00, 0x00 }, // movb $0, (%eax)
|
||||
# endif
|
||||
};
|
||||
#endif /* CONFIG_PARAVIRT_SPINLOCKS */
|
||||
|
||||
unsigned int native_patch(u8 type, void *insn_buff, unsigned long addr,
|
||||
unsigned int len)
|
||||
{
|
||||
switch (type) {
|
||||
|
||||
#ifdef CONFIG_PARAVIRT_XXL
|
||||
PATCH_CASE(irq, save_fl, xxl, insn_buff, len);
|
||||
PATCH_CASE(irq, irq_enable, xxl, insn_buff, len);
|
||||
PATCH_CASE(irq, irq_disable, xxl, insn_buff, len);
|
||||
|
||||
PATCH_CASE(mmu, read_cr2, xxl, insn_buff, len);
|
||||
PATCH_CASE(mmu, read_cr3, xxl, insn_buff, len);
|
||||
PATCH_CASE(mmu, write_cr3, xxl, insn_buff, len);
|
||||
|
||||
PATCH_CASE(cpu, wbinvd, xxl, insn_buff, len);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PARAVIRT_SPINLOCKS
|
||||
case PARAVIRT_PATCH(lock.queued_spin_unlock):
|
||||
if (pv_is_native_spin_unlock())
|
||||
return PATCH(lock, queued_spin_unlock, insn_buff, len);
|
||||
break;
|
||||
|
||||
case PARAVIRT_PATCH(lock.vcpu_is_preempted):
|
||||
if (pv_is_native_vcpu_is_preempted())
|
||||
return PATCH(lock, vcpu_is_preempted, insn_buff, len);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return paravirt_patch_default(type, insn_buff, addr, len);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue