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[media] nuvoton-cir: fix setting ioport base address

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At least on Zotac CI321 ACPI provides an ioport range for the wake up part
but accessing these ioports has no effect.
Instead the ioport base address is set to another value already
(0xa20 in my case) and accessing this ioport range works.

Therefore set a new ioport base address only if the current ioport base
address is 0 (register reset default).

The need to use the existing base address instead of trying to set
an own one doesn't seem to be limited to this specific device as other
drivers like hwmon/nct6775 do it the same way.

This change was successfully tested on the mentioned device.
And the change should be generic enough to not break the driver for
other chips (however due to lack of appropriate hardware I wasn't
able to test this).

[mchehab@osg.samsung.com: Tested on Intel NUC NUC5i7RYB with BIOS
 version RYBDWi35.86A.0350.2015.0812.1722]

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Tested-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Heiner Kallweit 2015-12-30 14:42:05 -02:00 committed by Mauro Carvalho Chehab
parent d790c9b93b
commit fb16aaf58c
1 changed files with 18 additions and 4 deletions
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22
drivers/media/rc/nuvoton-cir.c
View file

@ -161,6 +161,22 @@ static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
return val;
}
/* don't override io address if one is set already */
static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
{
unsigned long old_addr;
old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
if (old_addr)
*ioaddr = old_addr;
else {
nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
}
}
/* dump current cir register contents */
static void cir_dump_regs(struct nvt_dev *nvt)
{
@ -332,8 +348,7 @@ static void nvt_cir_ldev_init(struct nvt_dev *nvt)
/* Select CIR logical device */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_set_ioaddr(nvt, &nvt->cir_addr);
nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
@ -356,8 +371,7 @@ static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
/* Select CIR Wake logical device */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);