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KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq field, we can encode that information into the list registers. This patch provides implementations for both GICv2 and GICv3. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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32d2d8010c
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4 changed files with 38 additions and 5 deletions
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@ -268,9 +268,12 @@
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#define ICH_LR_EOI (1UL << 41)
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#define ICH_LR_GROUP (1UL << 60)
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#define ICH_LR_HW (1UL << 61)
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#define ICH_LR_STATE (3UL << 62)
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#define ICH_LR_PENDING_BIT (1UL << 62)
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#define ICH_LR_ACTIVE_BIT (1UL << 63)
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#define ICH_LR_PHYS_ID_SHIFT 32
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#define ICH_LR_PHYS_ID_MASK (0x3ffUL << ICH_LR_PHYS_ID_SHIFT)
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#define ICH_MISR_EOI (1 << 0)
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#define ICH_MISR_U (1 << 1)
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@ -71,11 +71,12 @@
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#define GICH_LR_VIRTUALID (0x3ff << 0)
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#define GICH_LR_PHYSID_CPUID_SHIFT (10)
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#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT)
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#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
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#define GICH_LR_STATE (3 << 28)
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#define GICH_LR_PENDING_BIT (1 << 28)
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#define GICH_LR_ACTIVE_BIT (1 << 29)
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#define GICH_LR_EOI (1 << 19)
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#define GICH_LR_HW (1 << 31)
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#define GICH_VMCR_CTRL_SHIFT 0
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#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT)
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@ -48,6 +48,10 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
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lr_desc.state |= LR_STATE_ACTIVE;
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if (val & GICH_LR_EOI)
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lr_desc.state |= LR_EOI_INT;
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if (val & GICH_LR_HW) {
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lr_desc.state |= LR_HW;
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lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;
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}
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return lr_desc;
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}
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@ -55,7 +59,9 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
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static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
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struct vgic_lr lr_desc)
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{
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u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq;
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u32 lr_val;
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lr_val = lr_desc.irq;
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if (lr_desc.state & LR_STATE_PENDING)
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lr_val |= GICH_LR_PENDING_BIT;
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@ -64,6 +70,14 @@ static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
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if (lr_desc.state & LR_EOI_INT)
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lr_val |= GICH_LR_EOI;
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if (lr_desc.state & LR_HW) {
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lr_val |= GICH_LR_HW;
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lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;
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}
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if (lr_desc.irq < VGIC_NR_SGIS)
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lr_val |= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);
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vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
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}
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@ -67,6 +67,10 @@ static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
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lr_desc.state |= LR_STATE_ACTIVE;
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if (val & ICH_LR_EOI)
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lr_desc.state |= LR_EOI_INT;
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if (val & ICH_LR_HW) {
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lr_desc.state |= LR_HW;
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lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
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}
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return lr_desc;
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}
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@ -84,10 +88,17 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
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* Eventually we want to make this configurable, so we may revisit
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* this in the future.
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*/
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if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
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switch (vcpu->kvm->arch.vgic.vgic_model) {
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case KVM_DEV_TYPE_ARM_VGIC_V3:
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lr_val |= ICH_LR_GROUP;
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else
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lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
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break;
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case KVM_DEV_TYPE_ARM_VGIC_V2:
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if (lr_desc.irq < VGIC_NR_SGIS)
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lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
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break;
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default:
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BUG();
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}
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if (lr_desc.state & LR_STATE_PENDING)
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lr_val |= ICH_LR_PENDING_BIT;
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@ -95,6 +106,10 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
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lr_val |= ICH_LR_ACTIVE_BIT;
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if (lr_desc.state & LR_EOI_INT)
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lr_val |= ICH_LR_EOI;
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if (lr_desc.state & LR_HW) {
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lr_val |= ICH_LR_HW;
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lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
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}
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vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val;
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}
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