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dmaengine: vdma: Add config structure to differentiate dmas
This patch adds config structure in the driver to differentiate AXI DMA's and to add more features(clock support etc..) to these DMA's. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
parent
07b0e7d49c
commit
fb2366675e
1 changed files with 51 additions and 32 deletions
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@ -342,6 +342,10 @@ struct xilinx_dma_chan {
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void (*start_transfer)(struct xilinx_dma_chan *chan);
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};
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struct xilinx_dma_config {
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enum xdma_ip_type dmatype;
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};
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/**
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* struct xilinx_dma_device - DMA device structure
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* @regs: I/O mapped base address
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@ -351,7 +355,7 @@ struct xilinx_dma_chan {
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* @has_sg: Specifies whether Scatter-Gather is present or not
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* @flush_on_fsync: Flush on frame sync
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* @ext_addr: Indicates 64 bit addressing is supported by dma device
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* @dmatype: DMA ip type
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* @dma_config: DMA config structure
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*/
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struct xilinx_dma_device {
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void __iomem *regs;
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@ -361,7 +365,7 @@ struct xilinx_dma_device {
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bool has_sg;
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u32 flush_on_fsync;
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bool ext_addr;
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enum xdma_ip_type dmatype;
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const struct xilinx_dma_config *dma_config;
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};
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/* Macros */
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@ -572,12 +576,12 @@ xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
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if (!desc)
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return;
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if (chan->xdev->dmatype == XDMA_TYPE_VDMA) {
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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list_for_each_entry_safe(segment, next, &desc->segments, node) {
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list_del(&segment->node);
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xilinx_vdma_free_tx_segment(chan, segment);
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}
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} else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) {
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} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
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list_for_each_entry_safe(cdma_segment, cdma_next,
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&desc->segments, node) {
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list_del(&cdma_segment->node);
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@ -640,7 +644,7 @@ static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
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dev_dbg(chan->dev, "Free all channel resources.\n");
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xilinx_dma_free_descriptors(chan);
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if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA)
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
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xilinx_dma_free_tx_segment(chan, chan->seg_v);
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dma_pool_destroy(chan->desc_pool);
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chan->desc_pool = NULL;
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@ -710,13 +714,13 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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* We need the descriptor to be aligned to 64bytes
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* for meeting Xilinx VDMA specification requirement.
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*/
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if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) {
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
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chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool",
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chan->dev,
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sizeof(struct xilinx_axidma_tx_segment),
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__alignof__(struct xilinx_axidma_tx_segment),
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0);
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} else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) {
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} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
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chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
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chan->dev,
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sizeof(struct xilinx_cdma_tx_segment),
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@ -737,7 +741,7 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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return -ENOMEM;
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}
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if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA)
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
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/*
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* For AXI DMA case after submitting a pending_list, keep
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* an extra segment allocated so that the "next descriptor"
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@ -750,7 +754,7 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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dma_cookie_init(dchan);
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if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) {
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
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/* For AXI DMA resetting once channel will reset the
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* other channel as well so enable the interrupts here.
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*/
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@ -758,7 +762,7 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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XILINX_DMA_DMAXR_ALL_IRQ_MASK);
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}
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if ((chan->xdev->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
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if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
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dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
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XILINX_CDMA_CR_SGMODE);
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@ -789,7 +793,7 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
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if (ret == DMA_COMPLETE || !txstate)
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return ret;
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if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) {
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
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spin_lock_irqsave(&chan->lock, flags);
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desc = list_last_entry(&chan->active_list,
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@ -1331,12 +1335,12 @@ static void append_desc_queue(struct xilinx_dma_chan *chan,
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*/
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tail_desc = list_last_entry(&chan->pending_list,
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struct xilinx_dma_tx_descriptor, node);
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if (chan->xdev->dmatype == XDMA_TYPE_VDMA) {
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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tail_segment = list_last_entry(&tail_desc->segments,
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struct xilinx_vdma_tx_segment,
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node);
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tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
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} else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) {
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} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
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cdma_tail_segment = list_last_entry(&tail_desc->segments,
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struct xilinx_cdma_tx_segment,
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node);
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@ -1356,8 +1360,8 @@ static void append_desc_queue(struct xilinx_dma_chan *chan,
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list_add_tail(&desc->node, &chan->pending_list);
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chan->desc_pendingcount++;
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if (chan->has_sg && (chan->xdev->dmatype == XDMA_TYPE_VDMA) &&
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unlikely(chan->desc_pendingcount > chan->num_frms)) {
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if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
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&& unlikely(chan->desc_pendingcount > chan->num_frms)) {
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dev_dbg(chan->dev, "desc pendingcount is too high\n");
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chan->desc_pendingcount = chan->num_frms;
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}
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@ -1810,7 +1814,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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chan->id = 0;
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chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
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if (xdev->dmatype == XDMA_TYPE_VDMA) {
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
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if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
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@ -1823,7 +1827,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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chan->id = 1;
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chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
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if (xdev->dmatype == XDMA_TYPE_VDMA) {
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
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if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
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@ -1844,9 +1848,9 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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return err;
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}
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if (xdev->dmatype == XDMA_TYPE_AXIDMA)
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if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
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chan->start_transfer = xilinx_dma_start_transfer;
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else if (xdev->dmatype == XDMA_TYPE_CDMA)
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else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
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chan->start_transfer = xilinx_cdma_start_transfer;
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else
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chan->start_transfer = xilinx_vdma_start_transfer;
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@ -1893,13 +1897,22 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
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return dma_get_slave_channel(&xdev->chan[chan_id]->common);
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}
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static const struct xilinx_dma_config axidma_config = {
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.dmatype = XDMA_TYPE_AXIDMA,
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};
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static const struct xilinx_dma_config axicdma_config = {
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.dmatype = XDMA_TYPE_CDMA,
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};
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static const struct xilinx_dma_config axivdma_config = {
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.dmatype = XDMA_TYPE_VDMA,
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};
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static const struct of_device_id xilinx_dma_of_ids[] = {
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{ .compatible = "xlnx,axi-dma-1.00.a",
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.data = (void *)XDMA_TYPE_AXIDMA },
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{ .compatible = "xlnx,axi-cdma-1.00.a",
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.data = (void *)XDMA_TYPE_CDMA },
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{ .compatible = "xlnx,axi-vdma-1.00.a",
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.data = (void *)XDMA_TYPE_VDMA },
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{ .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
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{ .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
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{ .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
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{}
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};
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MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
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@ -1914,7 +1927,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct xilinx_dma_device *xdev;
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struct device_node *child;
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struct device_node *child, *np = pdev->dev.of_node;
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struct resource *io;
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u32 num_frames, addr_width;
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int i, err;
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@ -1925,7 +1938,13 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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return -ENOMEM;
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xdev->dev = &pdev->dev;
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xdev->dmatype = (enum xdma_ip_type)of_device_get_match_data(&pdev->dev);
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if (np) {
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const struct of_device_id *match;
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match = of_match_node(xilinx_dma_of_ids, np);
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if (match && match->data)
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xdev->dma_config = match->data;
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}
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/* Request and map I/O memory */
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io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -1936,7 +1955,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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/* Retrieve the DMA engine properties from the device tree */
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xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
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if (xdev->dmatype == XDMA_TYPE_VDMA) {
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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err = of_property_read_u32(node, "xlnx,num-fstores",
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&num_frames);
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if (err < 0) {
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@ -1968,7 +1987,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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xdev->common.dev = &pdev->dev;
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INIT_LIST_HEAD(&xdev->common.channels);
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if (!(xdev->dmatype == XDMA_TYPE_CDMA)) {
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if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
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dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
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dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
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}
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@ -1980,12 +1999,12 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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xdev->common.device_terminate_all = xilinx_dma_terminate_all;
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xdev->common.device_tx_status = xilinx_dma_tx_status;
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xdev->common.device_issue_pending = xilinx_dma_issue_pending;
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if (xdev->dmatype == XDMA_TYPE_AXIDMA) {
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if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
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xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
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/* Residue calculation is supported by only AXI DMA */
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xdev->common.residue_granularity =
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DMA_RESIDUE_GRANULARITY_SEGMENT;
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} else if (xdev->dmatype == XDMA_TYPE_CDMA) {
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} else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
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dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
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xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
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} else {
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@ -2002,7 +2021,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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goto error;
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}
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if (xdev->dmatype == XDMA_TYPE_VDMA) {
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
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if (xdev->chan[i])
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xdev->chan[i]->num_frms = num_frames;
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