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Merge branch 'pci/controller/xilinx-ecam'
- Drop xilinx-nwl updates of bridge bus number fields, since PCI core already does that (Thippeswamy Havalige) - Update xilinx-nwl driver and ECAM size in devicetree example to allow up to 256 buses (Thippeswamy Havalige) * pci/controller/xilinx-ecam: PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields
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commit
fb3d102fc2
2 changed files with 4 additions and 16 deletions
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@ -118,7 +118,7 @@ examples:
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compatible = "xlnx,nwl-pcie-2.11";
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reg = <0x0 0xfd0e0000 0x0 0x1000>,
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<0x0 0xfd480000 0x0 0x1000>,
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<0x80 0x00000000 0x0 0x1000000>;
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<0x80 0x00000000 0x0 0x10000000>;
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reg-names = "breg", "pcireg", "cfg";
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ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
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<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
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@ -126,7 +126,7 @@
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#define E_ECAM_CR_ENABLE BIT(0)
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#define E_ECAM_SIZE_LOC GENMASK(20, 16)
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#define E_ECAM_SIZE_SHIFT 16
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#define NWL_ECAM_VALUE_DEFAULT 12
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#define NWL_ECAM_MAX_SIZE 16
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#define CFG_DMA_REG_BAR GENMASK(2, 0)
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#define CFG_PCIE_CACHE GENMASK(7, 0)
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@ -165,8 +165,6 @@ struct nwl_pcie {
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u32 ecam_size;
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int irq_intx;
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int irq_misc;
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u32 ecam_value;
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u8 last_busno;
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struct nwl_msi msi;
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struct irq_domain *legacy_irq_domain;
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struct clk *clk;
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@ -625,7 +623,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct platform_device *pdev = to_platform_device(dev);
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u32 breg_val, ecam_val, first_busno = 0;
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u32 breg_val, ecam_val;
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int err;
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breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
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@ -675,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
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E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
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nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
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(pcie->ecam_value << E_ECAM_SIZE_SHIFT),
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(NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),
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E_ECAM_CONTROL);
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nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
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@ -683,15 +681,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
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nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
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E_ECAM_BASE_HI);
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/* Get bus range */
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ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
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pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
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/* Write primary, secondary and subordinate bus numbers */
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ecam_val = first_busno;
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ecam_val |= (first_busno + 1) << 8;
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ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
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writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
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if (nwl_pcie_link_up(pcie))
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dev_info(dev, "Link is UP\n");
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else
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@ -792,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
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pcie = pci_host_bridge_priv(bridge);
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pcie->dev = dev;
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pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
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err = nwl_pcie_parse_dt(pcie, pdev);
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if (err) {
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