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Blackfin: handle BF561 Core B memory regions better when SMP=n
Rather than assume Core B is always run with caches turned on, let people load into any of the on-chip memory regions. It is their business how the SRAM/Cache regions are utilized, so don't prevent them from being able to load into them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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2 changed files with 29 additions and 8 deletions
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@ -361,7 +361,7 @@ static inline
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int in_mem_const(unsigned long addr, unsigned long size,
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unsigned long const_addr, unsigned long const_size)
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{
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return in_mem_const_off(addr, 0, size, const_addr, const_size);
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return in_mem_const_off(addr, size, 0, const_addr, const_size);
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}
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#define IN_ASYNC(bnum, bctlnum) \
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({ \
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@ -390,13 +390,13 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
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if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
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return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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#ifdef COREB_L1_CODE_START
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if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
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if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
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if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
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if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
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if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
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if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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#endif
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if (in_mem_const(addr, size, L2_START, L2_LENGTH))
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@ -472,13 +472,13 @@ int _access_ok(unsigned long addr, unsigned long size)
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if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
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return 1;
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#ifdef COREB_L1_CODE_START
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if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
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if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
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return 1;
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if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
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return 1;
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if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
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if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
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return 1;
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if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
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if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
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return 1;
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#endif
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if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
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@ -37,7 +37,6 @@
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/* Memory Map for ADSP-BF561 processors */
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#ifdef CONFIG_BF561
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#define COREA_L1_CODE_START 0xFFA00000
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#define COREA_L1_DATA_A_START 0xFF800000
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#define COREA_L1_DATA_B_START 0xFF900000
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@ -74,6 +73,28 @@
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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/*
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* If we are in SMP mode, then the cache settings of Core B will match
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* the settings of Core A. If we aren't, then we assume Core B is not
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* using any cache. This allows the rest of the kernel to work with
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* the core in either mode as we are only loading user code into it and
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* it is the user's problem to make sure they aren't doing something
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* stupid there.
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*
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* Note that we treat the L1 code region as a contiguous blob to make
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* the rest of the kernel simpler. Easier to check one region than a
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* bunch of small ones. Again, possible misbehavior here is the fault
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* of the user -- don't try to use memory that doesn't exist.
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*/
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#ifdef CONFIG_SMP
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# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
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# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
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# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
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#else
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# define COREB_L1_CODE_LENGTH 0x14000
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# define COREB_L1_DATA_A_LENGTH 0x8000
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# define COREB_L1_DATA_B_LENGTH 0x8000
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#endif
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/* Level 2 Memory */
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