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PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
While the Designware controller appears to hard code the PCI_CAP_ID_EXP capability register at 0x70, there's no need to hard code this in the driver as it is discoverable. Link: https://lore.kernel.org/r/20200821035420.380495-31-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: linux-omap@vger.kernel.org
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3 changed files with 7 additions and 12 deletions
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@ -73,8 +73,6 @@
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#define LINK_UP BIT(16)
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#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
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#define EXP_CAP_ID_OFFSET 0x70
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#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
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#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
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@ -142,7 +140,7 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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struct device *dev = pci->dev;
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u32 reg;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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if (dw_pcie_link_up(pci)) {
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dev_err(dev, "link is already up\n");
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@ -96,8 +96,6 @@
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#define LEG_EP 0x1
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#define RC 0x2
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#define EXP_CAP_ID_OFFSET 0x70
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#define KS_PCIE_SYSCLOCKOUTEN BIT(0)
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#define AM654_PCIE_DEV_TYPE_MASK 0x3
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@ -1125,22 +1123,23 @@ static int ks_pcie_am654_set_mode(struct device *dev,
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static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed)
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{
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u32 val;
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u32 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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dw_pcie_dbi_ro_wr_en(pci);
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val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP);
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val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
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if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
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val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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val |= link_speed;
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dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP,
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP,
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val);
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}
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val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2);
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val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
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if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
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val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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val |= link_speed;
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dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2,
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2,
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val);
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}
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@ -65,8 +65,6 @@ struct pcie_app_reg {
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/* CR6 */
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#define MSI_CTRL_INT (1 << 26)
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#define EXP_CAP_ID_OFFSET 0x70
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#define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
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static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
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@ -75,7 +73,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
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struct pcie_port *pp = &pci->pp;
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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u32 val;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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if (dw_pcie_link_up(pci)) {
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dev_err(pci->dev, "link already up\n");
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