mvebu dt for 4.9 (part 2)
- convert orion5x based SoC Netgear WNR854T to devicetree - remove obsolete orion-gpio binding description -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlfZac0ACgkQCwYYjhRyO9XfyQCgrTqHFOxoFH7T/MKeGMssVnSS TawAnR1gDDc313Fs6qZGeG9MWAhyzAG1 =0M3s -----END PGP SIGNATURE----- Merge tag 'mvebu-dt-4.9-2' of git://git.infradead.org/linux-mvebu into next/dt Pull "mvebu dt for 4.9 (part 2)" from Gregory CLEMENT: - convert orion5x based SoC Netgear WNR854T to devicetree - remove obsolete orion-gpio binding description * tag 'mvebu-dt-4.9-2' of git://git.infradead.org/linux-mvebu: ARM: dts: orion5x: Configure WNR854T ethernet PHY LEDs ARM: dts: orion5x: Add description for Netgear WNR854T ARM: dts: arm: orion5x: Add DT include for mv88f5181 dt-bindings: arm: add DT binding for Marvell Orion5x SoC family ARM: dts: orion5x: Add required properties for orion-wdt to DT node dt-binding: mrvl-gpio: remove orion-gpio description
This commit is contained in:
Arnd Bergmann
commit
fb90bc5060
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@ -0,0 +1,25 @@
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Marvell Orion SoC Family Device Tree Bindings
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---------------------------------------------
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Boards with a SoC of the Marvell Orion family, eg 88f5181
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* Required root node properties:
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compatible: must contain "marvell,orion5x"
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In addition, the above compatible shall be extended with the specific
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SoC. Currently known SoC compatibles are:
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"marvell,orion5x-88f5181"
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"marvell,orion5x-88f5182"
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And in addition, the compatible shall be extended with the specific
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board. Currently known boards are:
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"buffalo,lsgl"
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"buffalo,lswsgl"
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"buffalo,lswtgl"
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"lacie,ethernet-disk-mini-v2"
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"lacie,d2-network"
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"marvell,rd-88f5182-nas"
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"maxtor,shared-storage-2"
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"netgear,wnr854t"
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@ -44,26 +44,3 @@ Example for a PXA3xx platform:
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interrupt-controller;
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#interrupt-cells = <0x2>;
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};
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* Marvell Orion GPIO Controller
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Required properties:
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- compatible : Should be "marvell,orion-gpio"
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- reg : Address and length of the register set for controller.
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- gpio-controller : So we know this is a gpio controller.
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- ngpio : How many gpios this controller has.
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- interrupts : Up to 4 Interrupts for the controller.
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Optional properties:
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- mask-offset : For SMP Orions, offset for Nth CPU
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Example:
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gpio0: gpio@10100 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0x10100 0x40>;
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ngpio = <32>;
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interrupts = <35>, <36>, <37>, <38>;
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};
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@ -598,6 +598,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
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orion5x-linkstation-lswtgl.dtb \
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orion5x-lswsgl.dtb \
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orion5x-maxtor-shared-storage-2.dtb \
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orion5x-netgear-wnr854t.dtb \
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orion5x-rd88f5182-nas.dtb
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dtb-$(CONFIG_ARCH_PRIMA2) += \
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prima2-evb.dtb
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@ -0,0 +1,49 @@
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/*
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* Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "orion5x.dtsi"
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/ {
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compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
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soc {
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compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
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internal-regs {
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pinctrl: pinctrl@10000 {
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compatible = "marvell,88f5181-pinctrl";
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reg = <0x10000 0x8>, <0x10050 0x4>;
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};
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core_clk: core-clocks@10030 {
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compatible = "marvell,mv88f5181-core-clock";
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reg = <0x10010 0x4>;
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#clock-cells = <1>;
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};
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x1500 0x20>;
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};
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};
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};
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};
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&pinctrl {
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pmx_ge: pmx-ge {
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marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11",
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"mpp12", "mpp13", "mpp14", "mpp15",
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"mpp16", "mpp17", "mpp18", "mpp19";
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marvell,function = "ge";
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};
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};
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ð {
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pinctrl-0 = <&pmx_ge>;
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pinctrl-names = "default";
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};
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@ -0,0 +1,251 @@
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/*
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* Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "orion5x-mv88f5181.dtsi"
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/ {
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model = "Netgear WNR854-t";
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compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
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"marvell,orion5x";
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aliases {
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serial0 = &uart0;
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};
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memory {
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reg = <0x00000000 0x2000000>; /* 32 MB */
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
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<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
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<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&pmx_reset_button>;
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pinctrl-names = "default";
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reset {
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label = "Reset Button";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
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pinctrl-names = "default";
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led@0 {
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label = "wnr854t:green:power";
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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};
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led@1 {
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label = "wnr854t:blink:power";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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};
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led@2 {
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label = "wnr854t:green:wan";
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gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&devbus_bootcs {
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status = "okay";
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devbus,keep-config;
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flash@0 {
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compatible = "cfi-flash";
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reg = <0 0x800000>;
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bank-width = <2>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x0 0x100000>;
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};
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partition@100000 {
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label = "rootfs";
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reg = <0x100000 0x660000>;
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};
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partition@760000 {
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label = "uboot_env";
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reg = <0x760000 0x20000>;
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};
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partition@780000 {
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label = "uboot";
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reg = <0x780000 0x80000>;
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read-only;
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};
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};
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};
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};
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&mdio {
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status = "okay";
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switch: switch@0 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-handle = <&lan3phy>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-handle = <&lan4phy>;
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};
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port@2 {
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reg = <2>;
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label = "wan";
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phy-handle = <&wanphy>;
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};
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port@3 {
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reg = <3>;
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label = "cpu";
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ethernet = <ðport>;
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};
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port@5 {
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reg = <5>;
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label = "lan1";
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phy-handle = <&lan1phy>;
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};
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port@7 {
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reg = <7>;
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label = "lan2";
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phy-handle = <&lan2phy>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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lan3phy: ethernet-phy@0 {
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/* Marvell 88E1121R (port 1) */
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compatible = "ethernet-phy-id0141.0cb0",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
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};
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lan4phy: ethernet-phy@1 {
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/* Marvell 88E1121R (port 2) */
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compatible = "ethernet-phy-id0141.0cb0",
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"ethernet-phy-ieee802.3-c22";
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reg = <1>;
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marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
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};
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wanphy: ethernet-phy@2 {
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/* Marvell 88E1121R (port 1) */
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compatible = "ethernet-phy-id0141.0cb0",
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"ethernet-phy-ieee802.3-c22";
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reg = <2>;
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marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
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};
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lan1phy: ethernet-phy@5 {
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/* Marvell 88E1112 */
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compatible = "ethernet-phy-id0141.0cb0",
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"ethernet-phy-ieee802.3-c22";
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reg = <5>;
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marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
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};
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lan2phy: ethernet-phy@7 {
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/* Marvell 88E1112 */
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compatible = "ethernet-phy-id0141.0cb0",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
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};
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};
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};
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};
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ð {
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status = "okay";
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ethernet-port@0 {
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/* Hardwired to DSA switch */
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speed = <1000>;
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duplex = <1>;
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};
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};
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&pinctrl {
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pinctrl-0 = <&pmx_pci_gpios>;
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pinctrl-names = "default";
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pmx_power_led: pmx-power-led {
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marvell,pins = "mpp0";
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marvell,function = "gpio";
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};
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pmx_reset_button: pmx-reset-button {
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marvell,pins = "mpp1";
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marvell,function = "gpio";
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};
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pmx_power_led_blink: pmx-power-led-blink {
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marvell,pins = "mpp2";
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marvell,function = "gpio";
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};
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pmx_wan_led: pmx-wan-led {
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marvell,pins = "mpp3";
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marvell,function = "gpio";
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};
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pmx_pci_gpios: pmx-pci-gpios {
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marvell,pins = "mpp4";
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marvell,function = "gpio";
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};
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};
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&uart0 {
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/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
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status = "okay";
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};
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@ -144,9 +144,10 @@
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wdt: wdt@20300 {
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>;
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reg = <0x20300 0x28>, <0x20108 0x4>;
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interrupt-parent = <&bridge_intc>;
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interrupts = <3>;
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clocks = <&core_clk 0>;
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status = "okay";
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};
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