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PCI: keystone: Add support to set the max link speed from DT

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PCIe in TI's AM654 devices is by default configured to work in GEN3 mode.

However PCIe does not work reliably in GEN3 mode because of SERDES
configuration.

Add support to set the link speed to GEN1, GEN2 or GEN3 based on
"max-link-speed" DT property with GEN2 as the default speed if
"max-link-speed" is absent.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
Kishon Vijay Abraham I 2019-03-25 15:09:38 +05:30 committed by Lorenzo Pieralisi
parent 40e5d614a0
commit fbb2de891c
1 changed files with 35 additions and 0 deletions
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35
drivers/pci/controller/dwc/pci-keystone.c
View file

@ -28,6 +28,7 @@
#include <linux/resource.h>
#include <linux/signal.h>
#include "../../pci.h"
#include "pcie-designware.h"
#define PCIE_VENDORID_MASK 0xffff
@ -89,6 +90,8 @@
#define LEG_EP 0x1
#define RC 0x2
#define EXP_CAP_ID_OFFSET 0x70
#define KS_PCIE_SYSCLOCKOUTEN BIT(0)
#define AM654_PCIE_DEV_TYPE_MASK 0x3
@ -971,6 +974,31 @@ static int ks_pcie_am654_set_mode(struct device *dev)
return 0;
}
static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed)
{
u32 val;
dw_pcie_dbi_ro_wr_en(pci);
val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP);
if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
val &= ~((u32)PCI_EXP_LNKCAP_SLS);
val |= link_speed;
dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP,
val);
}
val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2);
if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
val &= ~((u32)PCI_EXP_LNKCAP_SLS);
val |= link_speed;
dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2,
val);
}
dw_pcie_dbi_ro_wr_dis(pci);
}
static const struct ks_pcie_of_data ks_pcie_rc_of_data = {
.host_ops = &ks_pcie_host_ops,
.version = 0x365A,
@ -1011,6 +1039,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
void __iomem *base;
u32 num_viewport;
struct phy **phy;
int link_speed;
u32 num_lanes;
char name[10];
int ret;
@ -1165,6 +1194,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
gpiod_set_value_cansleep(gpiod, 1);
}
link_speed = of_pci_get_max_link_speed(np);
if (link_speed < 0)
link_speed = 2;
ks_pcie_set_link_speed(pci, link_speed);
pci->pp.ops = host_ops;
ret = ks_pcie_add_pcie_port(ks_pcie, pdev);
if (ret < 0)